CN117195785A

CN117195785A - Bus verification method and intellectual property core verification system

Info

Publication number: CN117195785A
Application number: CN202311129390.8A
Authority: CN
Inventors: 李若愚; 银磊; 王�锋
Original assignee: New H3C Semiconductor Technology Co Ltd
Current assignee: New H3C Semiconductor Technology Co Ltd
Priority date: 2023-09-01
Filing date: 2023-09-01
Publication date: 2023-12-08

Abstract

The embodiment of the application provides a bus verification method and a verification intellectual property core system, which relate to the technical field of chips, and are applied to the verification of the intellectual property core system, wherein the verification intellectual property core system comprises a first acquisition component, a second acquisition component, a driving component and a verification component, and the first acquisition component and the second acquisition component are respectively connected with the verification component; the method comprises the following steps: the driving component drives the data packet to the tested circuit; the first acquisition component acquires a first signal of a data packet sent by the driving component to the tested circuit; the second acquisition component acquires a second signal of the tested circuit for sending and receiving the data packet to the driving component; the verification component acquires a first signal from the first acquisition component and acquires a second signal from the second acquisition component; based on the first signal and the second signal, the circuit under test is verified. By applying the technical scheme provided by the embodiment of the application, the time consumption for building the VIP can be reduced, the labor cost for building the VIP is reduced, and the quality of the VIP is improved.

Description

Bus verification method and intellectual property core verification system

Technical Field

The application relates to the technical field of chips, in particular to a bus verification method and an intellectual property verification core system.

Background

In chip design, various interface buses are important bridges for communication between modules or between dies (Die) and Die. The complexity of various interface buses is different, and the use requirements of actual chip projects are also different. In bus Verification, one or more VIPs (Verification IP) are set up according to the chip project use requirements to perform Verification. The complexity of the VIP of different interface buses is high, and the cost of learning by the verifier is high by using the complex VIP, so that the labor cost is greatly increased, the time for building the VIP is too long, and the quality of the VIP is difficult to guarantee.

Disclosure of Invention

The embodiment of the application aims to provide a bus verification method and an intellectual property core system for reducing the time consumption for building VIP, reducing the labor cost for building VIP and improving the quality of VIP. The specific technical scheme is as follows:

in a first aspect, an embodiment of the present application provides a bus verification method, which is applied to a verification intellectual property core system, where the verification intellectual property core system includes a first acquisition component, a second acquisition component, a driving component and a verification component, where the first acquisition component and the second acquisition component are respectively connected with the verification component; the method comprises the following steps:

The driving component drives the data packet to the tested circuit;

the first acquisition component acquires a first signal of the data packet sent by the driving component to the tested circuit;

the second acquisition component acquires a second signal of the tested circuit for sending and receiving the data packet to the driving component;

the verification component acquires the first signal from the first acquisition component and acquires the second signal from the second acquisition component; and verifying the tested circuit based on the first signal and the second signal.

In some embodiments, the first signal indicates that the drive assembly has sent a data packet and the second signal indicates that the circuit under test has received the data packet; the verification assembly includes a flow control sub-assembly;

the verification component verifies the circuit under test based on the first signal and the second signal, including:

the flow control subassembly reduces the value of a preset counter by 1 after acquiring the first signal; after the second signal is acquired, adding 1 to the value of the preset counter; and outputting an error alarm when the value of the preset counter is smaller than a set threshold value.

In some embodiments, the first signal indicates whether the drive assembly is ready to transmit the data packet and the second signal indicates whether the circuit under test is ready to receive the data packet; the verification assembly includes a flow control sub-assembly;

the flow control sub-assembly outputs an error alarm when the first signal and the second signal meet preset conditions;

wherein, the preset conditions are as follows:

the first signal indicates that the drive assembly is ready to transmit the data packet and the second signal indicates that the circuit under test is not ready to receive the data packet; or (b)

The first signal indicates that the drive assembly is not ready to transmit the data packet and the second signal indicates that the circuit under test is ready to receive the data packet.

In some embodiments, the verification intellectual property core system further comprises a decision component and a selector, the decision component and the second collection component are respectively connected with the selector, the decision component is connected with the second collection component, and the selector is connected with the flow control sub-component; the method further comprises the steps of:

The decision component acquires the second signal acquired by the second acquisition component;

the selector selects one second signal from the decision component and the second signal from the second acquisition component and sends the selected second signal to the flow control sub-component.

In some embodiments, the decision component is coupled to the drive component; the method further comprises the steps of:

and the decision component controls the driving component to send the data packet to the tested circuit according to the second signal.

In some embodiments, the verification intellectual property core system further comprises a first-in first-out pipeline; the decision component is connected with the first-in first-out pipeline, and the first-in first-out pipeline is connected with the second acquisition component; the method further comprises the steps of:

the decision component obtaining the second signal acquired by the second acquisition component includes:

the second acquisition component caches the acquired second signal to the first-in first-out pipeline;

the decision component obtains the second signal from the first-in-first-out pipeline.

In some embodiments, the verification intellectual property core system further comprises a first conversion component and a second conversion component, the verification component comprising a comparison sub-component; the comparison sub-assembly is respectively connected with the first conversion assembly and the second conversion assembly, the first conversion assembly is connected with the first acquisition assembly, and the second conversion assembly is connected with the second acquisition assembly; the method further comprises the steps of:

The first conversion component converts the first signal acquired by the first acquisition component into first intermediate data;

the second conversion component converts the second signal acquired by the second acquisition component into second intermediate data;

the comparison sub-component compares the first intermediate data with the second intermediate data; and outputting an error alarm under the condition that the first intermediate data and the second intermediate data are inconsistent.

In some embodiments, the verification intellectual property core system further comprises a second first-in first-out pipeline; the first conversion assembly is connected with the second first-in first-out pipeline, and the second first-out pipeline is connected with the comparison sub-assembly; the method further comprises the steps of:

the first conversion component caches the first intermediate data to the second first-in first-out pipeline;

the comparison sub-assembly obtains the first intermediate data from the second first-in-first-out pipeline.

In some embodiments, the first signal indicates a data packet that the drive assembly has sent, and the second signal indicates the data packet that the circuit under test has received; the validation component includes a significant capability validation sub-component;

the significant capability verification sub-component extracts a first tag carried by the data packet from the first signal and extracts a second tag carried by the data packet from the second signal; comparing the first label with the second label, and outputting an error alarm if the first label is inconsistent with the second label.

In some embodiments, the method further comprises:

the salient capability verification sub-component randomly generates a plurality of tags;

the significant capability verification sub-component compares the first tag with the second tag, and if the first tag and the second tag are not identical, outputs an error alert, including:

the significant capability verification sub-component registers the first tag of the plurality of tags as a non-empty state after extracting the first tag; and after the second label is extracted, outputting an error alarm if the second label in the plurality of labels is not in a non-empty state.

In some embodiments, before the driving component drives the data packet to the circuit under test, the method further comprises:

Acquiring a configuration file of the verification intellectual property core system;

and configuring each connection port, output signal and input signal in the verification intellectual property core system by using the configuration file.

In a second aspect, an embodiment of the present application provides an intellectual property verification core system, where the intellectual property verification core system includes a first acquisition component, a second acquisition component, a driving component, and a verification component, where the first acquisition component and the second acquisition component are respectively connected with the verification component;

the driving component is used for driving the data packet to the tested circuit;

the first acquisition component is used for acquiring a first signal of the data packet sent by the driving component to the tested circuit;

the second acquisition component is used for acquiring a second signal of the data packet sent and received by the tested circuit to the driving component;

the verification component is used for acquiring the first signal from the first acquisition component and acquiring the second signal from the second acquisition component; and verifying the tested circuit based on the first signal and the second signal.

The flow control subassembly is used for subtracting 1 from the value of a preset counter after the first signal is acquired; after the second signal is acquired, adding 1 to the value of the preset counter; and outputting an error alarm when the value of the preset counter is smaller than a set threshold value.

the flow control subassembly is used for outputting an error alarm when the first signal and the second signal meet preset conditions;

wherein, the preset conditions are as follows:

In some embodiments, the verification intellectual property core system further comprises a decision component and a selector, the decision component and the second collection component are respectively connected with the selector, the decision component is connected with the second collection component, and the selector is connected with the flow control sub-component;

The decision component is used for acquiring the second signal acquired by the second acquisition component;

the selector is used for selecting one second signal from the decision component and the second signal from the second acquisition component and sending the selected second signal to the flow control sub-component.

In some embodiments, the decision component is coupled to the drive component;

and the decision component is also used for controlling the driving component to send the data packet to the tested circuit according to the second signal.

In some embodiments, the verification intellectual property core system further comprises a first-in first-out pipeline; the decision component is connected with the first-in first-out pipeline, and the first-in first-out pipeline is connected with the second acquisition component;

the second acquisition assembly is further used for buffering the acquired second signals to the first-in first-out pipeline;

the decision component is specifically configured to obtain the second signal from the first fifo pipe.

In some embodiments, the verification intellectual property core system further comprises a first conversion component and a second conversion component, the verification component comprising a comparison sub-component; the comparison sub-assembly is respectively connected with the first conversion assembly and the second conversion assembly, the first conversion assembly is connected with the first acquisition assembly, and the second conversion assembly is connected with the second acquisition assembly;

The first conversion component is used for converting the first signal acquired by the first acquisition component into first intermediate data;

the second conversion component is used for converting the second signal acquired by the second acquisition component into second intermediate data;

the comparison sub-assembly is used for comparing the first intermediate data with the second intermediate data; and outputting an error alarm under the condition that the first intermediate data and the second intermediate data are inconsistent.

In some embodiments, the verification intellectual property core system further comprises a second first-in first-out pipeline; the first conversion assembly is connected with the second first-in first-out pipeline, and the second first-out pipeline is connected with the comparison sub-assembly;

the first conversion component is further configured to buffer the first intermediate data to the second fifo pipe;

the comparison subassembly is further configured to obtain the first intermediate data from the second fifo pipe.

The significant capability verification sub-component is configured to extract a first tag carried by the data packet from the first signal, and extract a second tag carried by the data packet from the second signal; comparing the first label with the second label, and outputting an error alarm if the first label is inconsistent with the second label.

In some embodiments, the salient capability verification sub-component is further for randomly generating a plurality of tags;

the significant capability verification sub-component is specifically configured to register the first tag in the plurality of tags as a non-empty state after the first tag is extracted; and after the second label is extracted, outputting an error alarm if the second label in the plurality of labels is not in a non-empty state.

In some embodiments, the drive assembly is further configured to:

before driving a data packet to a tested circuit, acquiring a configuration file of the verification intellectual property core system;

In a third aspect, an embodiment of the present application provides an electronic device, including a processor, a communication interface, a memory, and a communication bus, where the processor, the communication interface, and the memory complete communication with each other through the communication bus;

A memory for storing a computer program;

and a processor, configured to implement the method steps described in the first aspect when executing the program stored in the memory.

In a fourth aspect, embodiments of the present application provide a computer-readable storage medium having stored therein a computer program which, when executed by a processor, implements the method steps of the first aspect described above.

In a further embodiment of the present application, there is also provided a computer program product comprising instructions which, when run on a computer, cause the computer to perform the method steps of the first aspect of the above embodiments.

The embodiment of the application has the beneficial effects that:

in the technical scheme provided by the embodiment of the application, the verification intellectual property core system is a universal bus verification framework. When bus verification is carried out, the corresponding bus verification can be completed by utilizing the verification component only by simply configuring the output signal, the input signal, the active mode of the component and the like of the verification intellectual property core system, and the verification personnel are not required to learn the building of the corresponding components of different interface buses, so that the building time of the VIP is reduced, and the labor cost is reduced. In addition, as the verification intellectual property core system adopts a universal bus verification framework, the construction of the verification intellectual property core system is not influenced by the construction level of verification personnel, and the VIP quality is improved.

Of course, it is not necessary for any one product or method of practicing the application to achieve all of the advantages set forth above at the same time.

Drawings

In order to more clearly illustrate the embodiments of the application or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the application, and other embodiments may be obtained according to these drawings to those skilled in the art.

FIG. 1 is a first schematic diagram of a flow control mechanism;

FIG. 2 is a second schematic diagram of a flow control mechanism;

fig. 3 is a schematic diagram of a first structure of a VIP system according to an embodiment of the present application;

FIG. 4 is a schematic diagram of a significant capability verification sub-assembly provided by an embodiment of the application for significant capability verification;

fig. 5 is a schematic diagram of a second structure of the VIP system provided in the application embodiment;

fig. 6 is a schematic diagram of a third structure of a VIP system according to an embodiment of the present application;

fig. 7 is a schematic diagram of a fourth structure of a VIP system according to an embodiment of the present application;

fig. 8 is a fifth structural schematic diagram of the VIP system provided in the application embodiment;

Fig. 9 is a schematic diagram of a VIP system implementation flow provided in the application embodiment;

fig. 10 is a sixth structural schematic diagram of a VIP system provided in the application embodiment;

FIG. 11 is a schematic flow chart of a bus verification method according to an embodiment of the present application;

fig. 12 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

Detailed Description

The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. Based on the embodiments of the present application, all other embodiments obtained by the person skilled in the art based on the present application are included in the scope of protection of the present application.

In chip design, various interface buses are important bridges for communication between modules or between Die and Die. The complexity of various interface buses is different, and the use requirements of actual chip projects are also different. In bus verification, one or more VIPs need to be built for verification according to chip project use requirements. The complexity of the VIP of different interface buses is high, and the cost of learning by the verifier is high by using the complex VIP, so that the labor cost is greatly increased, the time for building the VIP is too long, and the quality of the VIP is difficult to guarantee.

In high speed buses, there is basically the idea of a flow control, remarkable (outlining) capability. The flow control is simply that when the receiving end cannot receive the data, the transmitting end will not transmit the data. The so-called outturn capability issues multiple write or read instructions for the bus in succession without waiting for a response signal. The stronger the outlining capability, the higher the bus utilization.

In the bus handshake mechanism, two handshake mechanisms are common to implement the flow control mechanism.

A first flow control mechanism is shown in fig. 1. The sending end and the receiving end can control the information transmission rate, the sending end takes effect and VALID indicates that information (information) such as address, data and control signals is READY, the receiving end takes effect and READY indicates that the data is READY to be received, and the transmission is performed according to a clock signal (such as ACLK) only when the VALID and the READY take effect.

A second flow control mechanism is shown in fig. 2. SOP (start of packet) denotes the header and EOP (end of packet) denotes the trailer. The sender sends SOP, EOP, and data based on a clock signal (e.g., CLK) at each PUSH (PUSH) stage. After the receiving end receives the SOP, the EOP and the data, based on a clock signal (such as CLK), an acknowledgement signal such as a DCACK or a CCACK is fed back, and the transmitting end decides whether to transmit the data according to the received DCACK or CCACK.

For the implementation of the outlining capability, one key technique is: the data sent by the sending end needs to contain a specific TAG (TAG) signal, and the receiving end can determine whether the data is valid or not according to the received TAG.

In order to achieve the above flow control and verification of the outloding capability, reduce VIP construction time, reduce VIP construction labor cost, and improve VIP quality, the embodiment of the present application provides a VIP system, as shown in fig. 3, which includes a first collecting assembly 31, a second collecting assembly 32, a driving assembly 33, and a verification assembly 34, wherein the first collecting assembly 31 and the second collecting assembly 32 are respectively connected with the verification assembly 34. When bus verification is performed, the first acquisition component 31 and the driving component 33 are connected with an input interface of a tested circuit, and the second acquisition component 32 is connected with an output interface of the tested circuit. The input interface is an interface of the tested circuit for receiving the signal sent by the driving component 33, and the output interface is an interface of the tested circuit for sending the signal to the driving component 33.

A driving component 33, configured to drive the data packet to the circuit under test;

the first acquisition component 31 is used for acquiring a first signal of a data packet sent by the driving component 33 to the tested circuit;

a second acquisition component 32, configured to acquire a second signal of the detected circuit that sends and receives the data packet to the driving component 33;

A verification component 34 for acquiring a first signal from the first acquisition component 31 and a second signal from the second acquisition component 32; based on the first signal and the second signal, the circuit under test is verified.

In the embodiment of the present application, the types of signals collected by the first collection assembly 31 and the second collection assembly 32 may be configured through a configuration file, and the first collection assembly 31 and the second collection assembly 32 collect corresponding signals according to the configuration, such as VALID, READY, SOP, EOP and data packets. The verification component 34 performs verification of the corresponding flow control, outloding capabilities based on the signals acquired by the first acquisition component 31 and the second acquisition component 32.

In some embodiments, verification component 34 may include a flow control sub-component for flow control verification of the circuit under test based on the first signal and the second signal.

For the flow control mechanism as shown in fig. 1. The first signal indicates whether the drive assembly is ready to transmit a data packet and the second signal indicates whether the circuit under test is ready to receive a data packet. For example, the first signal is a VALID signal indicating that the driving assembly is READY to send a data packet, and the second signal is a READY signal indicating that the circuit under test is READY to receive a data packet.

In this case, the flow control sub-assembly is configured to output a false alarm when the first signal and the second signal satisfy a preset condition.

The preset conditions may be:

the first signal indicates that the driving assembly is ready for sending the data packet, and the second signal indicates that the tested circuit is not ready for receiving the data packet; or (b)

The first signal indicates that the drive assembly is not ready to transmit a data packet and the second signal indicates that the circuit under test is ready to receive a data packet.

For the flow control mechanism as shown in fig. 2. The first signal indicates that the driving assembly has sent the data packet, and the second signal indicates that the tested circuit has received the data packet; for example, the first signal is a PUSH signal, an SOP signal, an EOP signal, or a data packet, and the second signal is a DCACK signal, a CCACK signal, or the like.

In this case, the flow control subassembly is configured to decrement the value of the preset counter by 1 after the first signal is acquired; after the second signal is obtained, adding 1 to the value of a preset counter; and outputting an error alarm when the value of the preset counter is smaller than the set threshold value.

The set threshold may be set according to actual requirements, for example, the set threshold may be 0, 1, 5, or the like.

In the embodiment of the application, in order to realize verification of various flow controls, the verification assembly can comprise a plurality of flow control subassemblies, and different flow control subassemblies process different signals. For example, the validation component may include 2 flow control sub-components, one flow control sub-component handling validation of the DCACK signal associated flow control and one flow control sub-component handling validation of the CCACK signal associated flow control.

In some embodiments, verification component 34 may include a significant capability verification sub-component for performing an outlining capability verification on the circuit under test based on the first signal and the second signal.

For an implementation of the outlining capability, the first signal indicates a data packet that has been sent by the drive component 33 and the second signal indicates a data packet that has been received by the circuit under test.

In this case, the significant capability verification sub-component is configured to extract a first tag carried by the data packet from the first signal, and extract a second tag carried by the data packet from the second signal; comparing the first label with the second label; and if the first label is inconsistent with the second label, outputting an error alarm.

In order to facilitate the outlining capability verification, the significant capability verification sub-component may implement the outlining capability verification through a string array. Specifically, the significant capability verification sub-component randomly generates a plurality of TAGs (TAGs); after extracting the first label, registering the first label of the plurality of labels as a non-Empty state (NE); after the second tag is extracted, if the second tag in the plurality of tags is not in a non-empty state, an error alarm is output.

For example, the saliency verification sub-component randomly generates a plurality of TAGs, as shown in FIG. 4. The drive component sends one or more data packets, each carrying a randomly generated TAG. After the saliency verification sub-component obtains the first signal (i.e., the data packet) from the first acquisition component, the TAG1 is extracted from the first signal, as 1111 in fig. 4, and the state of 1111 is set to NE. After the significant capability verification sub-assembly obtains the second signal (i.e., the data packet) from the second acquisition assembly, extracting the TAG2 from the second signal, and if the TAG2 is not in a non-empty state, i.e., the TAG2 is in an empty state (E), if 1110 in fig. 4, determining that the first TAG and the second TAG are inconsistent, outputting an error alarm; if the TAG2 is in a non-null state, i.e., the TAG2 is a NE, as in 1111 of fig. 4, the verification result corresponding to the data packet is determined as follows: the tested circuit successfully passed the outlining capability verification.

Here, if the driving component sends a plurality of data packets, the verification results corresponding to the data packets are required to indicate that the tested circuit successfully passes the outlining capability verification, and then the tested circuit can be indicated to successfully pass the outlining capability verification.

In some embodiments, the VIP system may further include a decision component 35 and a selector 36, as shown in fig. 5, the decision component 35 and the second collection component 32 being connected to the selector 36, respectively, the decision component 35 being connected to the second collection component 32, the selector 36 being connected to the flow control sub-component (i.e., the validation component 34).

A decision component 35, configured to acquire the second signal acquired by the second acquisition component 32;

a selector 36 for selecting one of the second signal from the decision component 35 and the second signal from the second acquisition component 32 and transmitting the selected second signal to the flow control sub-component.

In the embodiment of the present application, the decision component 35 and the second collecting component 32 may be used to drive the flow control sub-component to perform flow control verification, for example, the value of the preset counter is increased by 1, and the decision component 35 and the second collecting component 32 drive the flow control sub-component to be mutually exclusive. The decision component 35 or the second acquisition component 32 is selected to drive the flow control sub-component according to actual requirements, so that the flexibility of flow control is improved.

In some embodiments, the decision component 35 is coupled to the drive component 33, as shown in FIG. 5. In this case, the decision component 35 may be further configured to control the driving component 33 to send the data packet to the circuit under test according to the second signal after the second signal is acquired.

In the embodiment of the present application, the second signal is the response data of the tested circuit collected by the second collecting component 32. The decision component 35 can determine whether the driver component 33 issues the request data (e.g., the data packet) based on the response data. Here, the connection relationship between the decision making component 35 and the second acquisition component 32 can be configured by a configuration file.

In some embodiments, to ensure that the decision component 35 obtains the second signal from the second acquisition component 32, the VIP system may further include a first fifo pipe 37, as shown in fig. 6; the decision-making component 35 is connected to a first fifo pipe 37, said first fifo pipe 37 being connected to the second acquisition component 32. In this case, the second acquisition component 32 may also be configured to buffer the acquired second signal to the first fifo pipe 37; the decision component 35 is specifically configured to obtain the second signal from the first fifo pipe 37.

In some embodiments, as shown in fig. 7, the VIP system may further include a first conversion component 38 and a second conversion component 39, and the validation component 34 may include a comparison sub-component; the comparing subassembly is connected to a first converting assembly 38 and a second converting assembly 39, respectively, the first converting assembly 38 is connected to the first collecting assembly 31, and the second converting assembly 39 is connected to the second collecting assembly 32.

In this case, the first conversion component 38 is configured to convert the first signal acquired by the first acquisition component 31 into first intermediate data;

a second conversion component 39, configured to convert the second signal acquired by the second acquisition component 32 into second intermediate data;

a comparison sub-assembly for comparing the first intermediate data with the second intermediate data; and outputting an error alarm under the condition that the first intermediate data and the second intermediate data are inconsistent.

In the embodiment of the present application, the first conversion component 38 and the second conversion component 39 are modules for implementing data format conversion, and can convert the data format of the input/output of the tested circuit into a unified data format that can be identified by the comparison sub-component. The comparison subassembly compares the first intermediate data with the second intermediate data to determine whether the output of the circuit under test meets an expected. That is, if the first intermediate data and the second intermediate data are consistent, it is determined that the output of the tested circuit meets the expectation, if the first intermediate data and the second intermediate data are inconsistent, it is determined that the output of the tested circuit does not meet the expectation, and then an error alarm is output.

In some embodiments, as shown in fig. 8, the VIP system may further include a second first in first out pipeline 310; the first conversion assembly 38 is connected to a second first-in first-out pipeline 310, and the second first-in first-out pipeline 310 is connected to the comparison subassembly. In this case, the first conversion component 38 may also be configured to buffer the first intermediate data into the second first-in-first-out pipeline; the comparison subassembly may also be configured to obtain the first intermediate data from the second first-in-first-out pipeline.

In the embodiment of the present application, the first conversion component 38 buffers the first intermediate data into the second fifo 310 after converting the first signal into the first intermediate data; the comparison sub-component in turn actively retrieves the first intermediate data (i.e., the requested data) from the second fifo pipe 310. In addition, the second conversion component 39 may actively send the second intermediate data to the comparison sub-component after converting the second signal into the second intermediate data, which is passively received by the comparison sub-component (i.e., the response data). The time of the first intermediate data is earlier, the time of the second intermediate data is later, and the comparison subassembly can improve the accuracy and timeliness of data comparison by actively acquiring the first intermediate data and passively acquiring the second intermediate data.

In the embodiment of the present application, the second conversion assembly 39 and the first fifo pipe 37 are both connected to the second acquisition assembly 32. In this case, the VIP system may further include a selector 311, the second converting element 39 and the first fifo 37 are connected to the selector 311, respectively, and the selector 311 is connected to the second collecting element 32. In this case, the selector 311 may store the second signal to the first fifo pipe 37 or send the second signal to the second conversion element 39 by selection. The specific structure can be set according to actual requirements.

In the embodiment of the application, before bus verification is performed, that is, before the driving component drives the data packet to the tested circuit, the VIP system can acquire the configuration file of the VIP system; and configuring each connection port, output signal and input signal in the verification intellectual property core system by using the configuration file. For example, the configuration file may include necessary parameters such as input signal, output signal, name of VIP, driving mode of the flow control subassembly, connection of the comparison subassembly to the second fifo pipe, input pins selected by the respective selectors, and the like; as shown in the VIP system implementation flow shown in fig. 9, the VIP system converts the configuration file into a script in JSON format, runs the script, configures the basic component library of the VIP system with necessary parameters, and obtains a universal bus verification framework. The basic component library comprises the components.

In the embodiment of the application, the VIP system may further include other components, such as a reset component, and may be specifically preconfigured in the basic component library according to actual requirements.

The VIP system provided in the embodiment of the present application is described in detail below with reference to the VIP system structure shown in fig. 10. The VIP system includes a first universal bus agent (ubagt 1) and a second universal bus agent (ubagt 2). The UNB_AGT1 and UNB_AGT2 are two virtual verification environments.

Among the UNB_AGT1, there are included a RESET component 1 (RESET_HANDEL 1), a first acquisition component (UNB_Mon1), a flow control sub-component (UNB_CRD1, UNB_CRD2), a driving component (UNB_DRV), a first conversion component (UNB_FMT1), a selector (MUX 1, MUX 2), a decision component (UNB_SQR), and a significant capability verification sub-component (UNB_TAG).

In the UNB_AGT2, a RESET component 2 (RESET_HANDEL 2), a second acquisition component (UNB_Mon2), a selector (MUX 3), a second conversion component (UNB_FMT2), and a first-in first-out pipeline (FIFO 1) are included.

The VIP system may further include a second first-in-first-out pipeline (FIFO 2) and a comparison subcomponent (ubscb).

The connection relationship of the above-described individual components can be seen in fig. 10. The UNB_CRD2 and the MUX2 can be started according to actual requirements. For example, when it is necessary to perform flow control verification based on both the DCACK signal and the CCACK signal, the unb_crd2 and MUX2 are enabled, and when flow control verification is performed based on only the DCACK signal, or flow control verification is performed based on only the CCACK signal, the unb_crd2 and MUX2 are not enabled.

Reset_hand 1 and reset_hand 2 may be enabled before configuring the individual components based on the configuration file, resetting the individual components. After each component is configured based on the configuration file, the sequence component (UNB_SEQ) inputs sequence data to the UNB_SQR and transmits the sequence data to a bus function model (Bus Functional Model, BFM) in the UNB_DRV, so that the UNB_DRV drives a data packet to a tested circuit according to the sequence. And the following components mutually transmit data to finish the flow control and the verification of the outlining capability.

This description is relatively simple and may be found in particular in the relevant description above.

According to the technical scheme provided by the embodiment of the application, the time for building the verification platform such as VIP is saved, and the verification platform can be automatically generated by utilizing the configuration file; the generated verification platform integrates a flow control related component and an outlining functional component, so that the problem that the quality of the verification platform is difficult to guarantee because of the experience capability problem of a verification person can be avoided to a certain extent.

Corresponding to the VIP system, the embodiment of the application also provides a bus verification method, which is applied to verifying an intellectual property core system as shown in fig. 11, wherein the verifying intellectual property core system comprises a first acquisition component, a second acquisition component, a driving component and a verifying component, and the first acquisition component and the second acquisition component are respectively connected with the verifying component. The method comprises the following steps:

Step S111, the driving component drives the data packet to the tested circuit;

step S112, a first acquisition component acquires a first signal of a data packet sent by a driving component to a tested circuit;

step S113, the second acquisition component acquires a second signal of the tested circuit to send and receive a data packet to the driving component;

step S114, the verification component acquires a first signal from the first acquisition component and acquires a second signal from the second acquisition component; based on the first signal and the second signal, the circuit under test is verified.

the verifying component verifies the tested circuit based on the first signal and the second signal, and can include:

after the first signal is acquired, the flow control subassembly reduces the value of a preset counter by 1; after the second signal is obtained, adding 1 to the value of a preset counter; and outputting an error alarm when the value of the preset counter is smaller than the set threshold value.

In some embodiments, the first signal indicates whether the drive assembly is ready to send data packets, and the second signal indicates whether the circuit under test is ready to receive data packets; the verification assembly includes a flow control sub-assembly;

when the first signal and the second signal meet preset conditions, the flow control subassembly outputs an error alarm;

wherein, the preset conditions are:

In some embodiments, the verification intellectual property core system may further comprise a decision component and a selector, the decision component and the second collection component being respectively connected to the selector, the decision component being connected to the second collection component, the selector being connected to the flow control sub-component; the bus verification method may further include:

the decision component acquires a second signal acquired by the second acquisition component;

the selector selects one of the second signals from the decision component and the second signal from the second acquisition component and sends the selected second signal to the flow control sub-component.

In some embodiments, the decision component is coupled to the drive component; the bus verification method may further include:

and the decision component controls the driving component to send a data packet to the tested circuit according to the second signal.

In some embodiments, the verification intellectual property core system may further comprise a first-in first-out pipeline; the decision-making component is connected with a first-in first-out pipeline which is connected with the second acquisition component;

The decision component obtaining the second signal collected by the second collection component may include:

the decision component obtains a second signal from the first fifo pipe.

In some embodiments, the verification intellectual property core system may further comprise a first conversion component and a second conversion component, the verification component comprising a comparison sub-component; the comparison sub-assembly is respectively connected with the first conversion assembly and the second conversion assembly, the first conversion assembly is connected with the first acquisition assembly, and the second conversion assembly is connected with the second acquisition assembly; the bus verification method may further include:

In some embodiments, the verification intellectual property core system may further comprise a second first-in first-out pipeline; the first conversion component is connected with a second first-in first-out pipeline, and the second first-out pipeline is connected with the comparison sub-component; the bus verification method may further include:

The first conversion component caches the first intermediate data into the second first-in first-out pipeline;

the comparison subassembly obtains the first intermediate data from the second first-in-first-out pipeline.

In some embodiments, the first signal indicates a data packet that has been sent by the drive assembly, and the second signal indicates a data packet that has been received by the circuit under test; the verification component includes a significant capability verification sub-component;

the significance capability verification sub-component extracts a first tag carried by the data packet from the first signal and extracts a second tag carried by the data packet from the second signal; and comparing the first label with the second label, and outputting an error alarm if the first label is inconsistent with the second label.

In some embodiments, the bus verification method may further include:

the saliency verification sub-component randomly generates a plurality of tags;

the saliency verification sub-assembly compares the first label with the second label, and if the first label is inconsistent with the second label, an error alarm is output, and the method comprises the following steps:

after the first label is extracted, the significant capability verification sub-component registers the first label in the plurality of labels as a non-empty state; after the second tag is extracted, if the second tag in the plurality of tags is not in a non-empty state, an error alarm is output.

In some embodiments, the bus verification method may further include, before the driving component drives the data packet to the circuit under test:

acquiring a configuration file for verifying the intellectual property core system;

and configuring and verifying each connection port, output signal and input signal in the intellectual property core system by using the configuration file.

Corresponding to the above bus verification method, the embodiment of the present application further provides an electronic device, as shown in fig. 12, including a processor 121, a communication interface 122, a memory 123, and a communication bus 124, where the processor 121, the communication interface 122, and the memory 123 complete communication with each other through the communication bus 124;

a memory 123 for storing a computer program;

processor 121, when executing programs stored on memory 123, implements any of the bus validation methods described above.

The communication bus mentioned above for the electronic devices may be a peripheral component interconnect standard (Peripheral Component Interconnect, PCI) bus or an extended industry standard architecture (Extended Industry Standard Architecture, EISA) bus, etc. The communication bus may be classified as an address bus, a data bus, a control bus, or the like. For ease of illustration, the figures are shown with only one bold line, but not with only one bus or one type of bus.

The communication interface is used for communication between the electronic device and other devices.

The Memory may include random access Memory (Random Access Memory, RAM) or may include Non-Volatile Memory (NVM), such as at least one disk Memory. Optionally, the memory may also be at least one memory device located remotely from the aforementioned processor.

The processor may be a general-purpose processor, including a central processing unit (Central Processing Unit, CPU), a network processor (Network Processor, NP), etc.; but also digital signal processors (Digital Signal Processor, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC), field programmable gate arrays (Field-Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

In yet another embodiment of the present application, a computer readable storage medium is provided, in which a computer program is stored, which when executed by a processor implements any of the above-mentioned bus validation methods.

In yet another embodiment of the present application, a computer program product containing instructions that, when run on a computer, cause the computer to perform any of the bus validation methods described above is also provided.

In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, produces a flow or function in accordance with embodiments of the present application, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in or transmitted from one computer-readable storage medium to another, for example, by wired (e.g., coaxial cable, optical fiber, digital Subscriber Line (DSL)), or wireless (e.g., infrared, wireless, microwave, etc.). The computer readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains an integration of one or more available media. The usable medium may be a magnetic medium (e.g., floppy Disk, hard Disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid State Disk (SSD)), etc.

It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

In this specification, each embodiment is described in a related manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments. In particular, for method, electronic device, storage medium and program product embodiments, the description is relatively simple as it is substantially similar to the system embodiments, as relevant points are referred to in the partial description of the system embodiments.

The foregoing description is only of the preferred embodiments of the present application and is not intended to limit the scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application are included in the protection scope of the present application.

Claims

1. The bus verification method is characterized by being applied to a verification intellectual property core system, wherein the verification intellectual property core system comprises a first acquisition component, a second acquisition component, a driving component and a verification component, and the first acquisition component and the second acquisition component are respectively connected with the verification component; the method comprises the following steps:

the driving component drives the data packet to the tested circuit;

2. The method of claim 1, wherein the first signal indicates that the drive assembly has sent a data packet and the second signal indicates that the circuit under test has received the data packet; the verification assembly includes a flow control sub-assembly;

3. The method of claim 1, wherein the first signal indicates whether the drive assembly is ready to transmit the data packet and the second signal indicates whether the circuit under test is ready to receive the data packet; the verification assembly includes a flow control sub-assembly;

wherein, the preset conditions are as follows:

4. A method according to claim 2 or 3, wherein the verification intellectual property core system further comprises a decision component and a selector, the decision component and the second collection component being connected to the selector, the decision component being connected to the second collection component, the selector being connected to the flow control sub-component; the method further comprises the steps of:

5. The method of claim 4, wherein the decision component is coupled to the drive component; the method further comprises the steps of:

6. The method of claim 4, wherein the verification intellectual property core system further comprises a first-in first-out pipeline; the decision component is connected with the first-in first-out pipeline, and the first-in first-out pipeline is connected with the second acquisition component;

7. The method of claim 1, wherein the verifying intellectual property core system further comprises a first conversion component and a second conversion component, the verifying component comprising a comparison sub-component; the comparison sub-assembly is respectively connected with the first conversion assembly and the second conversion assembly, the first conversion assembly is connected with the first acquisition assembly, and the second conversion assembly is connected with the second acquisition assembly; the method further comprises the steps of:

8. The method of claim 7, wherein the verification intellectual property core system further comprises a second first-in first-out pipeline; the first conversion assembly is connected with the second first-in first-out pipeline, and the second first-out pipeline is connected with the comparison sub-assembly; the method further comprises the steps of:

9. The method of claim 1, wherein the first signal indicates a data packet that has been transmitted by the drive assembly and the second signal indicates the data packet that has been received by the circuit under test; the validation component includes a significant capability validation sub-component;

10. The method according to claim 9, wherein the method further comprises:

11. The method of claim 1, wherein prior to the driving assembly driving the data packets to the circuit under test, the method further comprises:

12. The verification intellectual property core system is characterized by comprising a first acquisition component, a second acquisition component, a driving component and a verification component, wherein the first acquisition component and the second acquisition component are respectively connected with the verification component;

13. The electronic equipment is characterized by comprising a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory are communicated with each other through the communication bus;

A memory for storing a computer program;

a processor for carrying out the method steps of any one of claims 1-11 when executing a program stored on a memory.