CN103546240A

CN103546240A - Ethernet CRC (cyclic redundancy check) checking method

Info

Publication number: CN103546240A
Application number: CN201310438378.5A
Authority: CN
Inventors: 郑拓夫; 周水斌; 闫志辉; 宋彦峰; 马仪成
Original assignee: Xuji Group Co Ltd; XJ Electric Co Ltd; Xuchang XJ Software Technology Co Ltd
Current assignee: Xuji Group Co Ltd; XJ Electric Co Ltd; Xuchang XJ Software Technology Co Ltd
Priority date: 2013-09-24
Filing date: 2013-09-24
Publication date: 2014-01-29
Anticipated expiration: 2033-09-24
Also published as: CN103546240B

Abstract

The invention relates to an Ethernet CRC checking method. The Ethernet CRC checking method includes receiving Ethernet one frame data, performing CRC calculation to the received data one byte by one byte at the same time, recording calculated CRC and storing, and comparing calculated CRC with CRC in the last received data to realize CRC checking. The whole CRC calculating process and the decode procedure are synchronous, no extra clock period is added, and data processing speed and efficiency is greatly increased.

Description

Ethernet CRC check method

Technical field

The invention belongs to the quick braiding decoding technique field of ethernet communication, relate to a kind of Ethernet CRC check method.

Background technology

Along with increasingly extensive in industrial circle application of ethernet technology, network data communication becomes the mutual major way of industrial data, yet in Industrial Ethernet, a lot of communications protocol are all that this field is exclusive, therefore, even if the network chip of main flow can provide the help in data communication, but specific to business scope, still there is very large defect, such as filtering business datum, cannot send data etc. by accurate timing.

100 m ethernet packet all can attach the CRC check code of 32 in the end.CRC is cyclic redundancy check (CRC) code, is a kind of error check code the most frequently used in data communication field, and the length of information field and check field can be selected arbitrarily, and in ethernet communication, it is followed after effective message and sends.The essence of CRC check is that CRC multinomial and byte to be verified are done to displacement XOR, because a byte has 256 kinds of results, therefore operation result also has 256 kinds, CRC look-up table is stored in these 256 kinds of results in constant array exactly in advance, when calculating, only need be according to the direct lookup result in array position of byte representative to be verified.The algorithm of CRC check is divided into two kinds: serial bit algorithm, parallel byte algorithm.Serial bit algorithm is that each data receiving and CRC generator polynomial are done to a logical operation, until receive, the method efficiency is lower, and a clock cycle only can be calculated a data; Parallel byte efficiency of algorithm is higher, it take a byte is unit, by each byte totally 256 kinds of result stores in constant array, table look-at during calculating, a clock cycle can be calculated 8 bit data, but this algorithm generally all just starts receiving complete frame data, when network data amount is larger, still can not meet the demands, therefore need the higher technology of a kind of efficiency to support Ethernet data volume more and more at a high speed.

Summary of the invention

The object of this invention is to provide a kind of Ethernet CRC check method, to solve existing method of calibration, cannot meet the increasing problem of Ethernet data amount.

For achieving the above object, Ethernet CRC check method and technology scheme of the present invention is as follows: when receiving Ethernet one frame data to the data that receive one by one byte carry out CRC computing, record CRC storage that computing obtains, the CRC that this computing is obtained and the last CRC receiving in data compare, and realize CRC check.

Further, the data that receive are deposited successively in to the nybble CRC buffering area to be verified of a FIFO, each byte data of overflowing is tabled look-up, computing is next time brought in the CRC the storage that obtain this byte into, until receive data, complete, the CRC that last CRC buffering area to be verified is received and the CRC calculating compare, and complete CRC check.

The described data that often receive a byte deposit data buffer zone in when depositing CRC buffering area to be verified in.

The CRC that described computing obtains and the last CRC receiving in data compare, if two CRC are different, in transmitting procedure, have occurred error code, and the data of data buffer zone storage are invalid.

Describedly until to receive that data complete be to be transmitted when last byte, deposit in after CRC buffer area to be verified, four byte datas that store in CRC buffer area to be verified are CRC code to be verified; The CRC check of last valid data of the last byte of CRC code simultaneously to be verified has been calculated, and the CRC to be verified storing in CRC buffer area to be verified is compared and just can learn whether these frame data have occurred error code in transmitting procedure with the CRC calculating.

Further, in sending data procedures, the data of a byte of every transmission, just table look-up and obtain the CRC of this byte, and bring computing next time into, until data send, finish, and form final CRC Packet Generation to link.

The transmission of described data or the RMII interface receiving by PHY chip complete, and FPGA is connected by RMII interface with PHY chip.

Ethernet CRC check method of the present invention, in the process of transmitting-receiving Ethernet message, take look-up table as basis, when receiving data, sending data, carry out CRC computing, whole computational process is synchronizeed with encoding-decoding process, clock cycle outside occupying volume not, speed and the efficiency of data processing have greatly been improved; FPGA is connected by RMII interface with PHY chip, RMII interface only transmits two bits in each clock cycle, transmit a byte and need four cycles, and byte to be verified is tabled look-up, need two clock cycle, therefore, from time efficiency, analyze, when can realize reception data or sending data, carry out CRC check; The hardware structure that adopts FPGA+PHY, utilizes the abundant I/O resource of FPGA to be directly connected with the transmitting-receiving pin of a plurality of PHY chips, and utilizes the characteristic of FPGA parallel data processing, can to a plurality of network interface data, carry out encoding and decoding and CRC check simultaneously.

Accompanying drawing explanation

Fig. 1 is that CRC receives checking process figure;

Fig. 2 is that CRC sends checking process figure;

Fig. 3 is the hardware structure figure of embodiment.

Embodiment

Ethernet CRC check as shown in Figure 1, 2, 3, in sending data encoding process, the data of a byte of every transmission, just table look-up and obtain the CRC of this byte, and bring computing next time into, and until sending, data finish, form final CRC packet and send on link by PHY; FPGA receives the data that send from PHY, in receiving data decode process, and the data of a byte of every reception, just table look-up and obtain the CRC of this byte, and bring computing next time into, until receipt decoding completes, the CRC receiving and the CRC calculating are compared, complete CRC check; Whole computational process is synchronizeed with encoding-decoding process, and not the clock cycle outside occupying volume, efficiency is higher.

Be illustrated in figure 3 hardware structure figure, FPGA is connected with CPU, be connected by RMII interface with a plurality of PHY chips, FPGA is hardware programming design, can realize the customize services to various demands, and it does not have the instruction cycle, by the reconstruct of hardware circuit, carry out required function completely, sequencing control precision is also very high, and the advantage of parallel processing, also can realize the data transmit-receive to a plurality of PHY simultaneously in addition.RMII is called Media Independent Interface, and it is the Ethernet industry standard of IEEE-802.3 definition, comprises a data management interface, and the management interface between MAC and PHY.

Ethernet CRC check method realizes FPGA is inner, utilizes the abundant I/O resource of FPGA to be directly connected with the transmitting-receiving pin of a plurality of PHY chips, and utilizes the advantage of himself parallel data processing, can to these a plurality of network interface data, carry out encoding and decoding and CRC check simultaneously; In addition, FPGA can be configured and be programmed by software, thereby can resolve filtration to special packet, therefore, the CPU that can be FPGA rear end discharges a large amount of resources, shortens the time of data processing, thereby prevents that network storm from causing negative effect to the stable operation of CPU.

This Ethernet CRC check method is to be based upon CRC to table look-up on the basis of algorithm, when calculating, and only need be according to the direct lookup result in array position of byte representative to be verified.Advantage in efficiency, in the process that FPGA can receive and dispatch at Ethernet data, complete CRC check accordingly.In receipt decoding process, the data of a byte of every reception, can obtain according to algorithm the CRC of this byte, and bring computing next time into, until receipt decoding completes; In sending cataloged procedure, also to adopt in the same way, the data of a byte of every transmission, calculate CRC one time, until be sent completely, and the CRC calculating is sent on link.

1, receive data procedures

As shown in Figure 1, FPGA carries out real-time decoding to the data of the RMII interface from PHY chip, the variable of opening up one 32 is used for storing the CRC check code of tabling look-up at every turn and obtaining, in addition, except opening up the buffering area of all Ethernet datas of storage, also need to define a CRC buffering area to be verified that can store four bytes.

Often receive that a byte, after depositing data buffer zone in, deposits CRC buffering area to be verified in simultaneously.This buffering area guarantees the principle of first in first out, until the 5th byte is pressed into, first byte is postponed and rushed district's ejection, can participate in CRC check computing.

RMII interface only transmits two bits in each clock cycle, and transmitting a byte needs four cycles, and byte to be verified is tabled look-up, need two clock cycle, therefore, from time efficiency, analyze, be to complete the CRC verification of tabling look-up completely in decode procedure.

When last byte, decoded, deposited in after CRC buffer area to be verified, four byte datas that store in buffering area are just in time CRC code to be verified; Meanwhile, the CRC check of last valid data (being last valid data of the last byte of CRC code to be verified) is calculated and is also just in time completed, and both more just can be learnt to whether these frame data have occurred error code in transmitting procedure.

2, send data procedures

As shown in Figure 2, the sequential that RMII interface sends is approximate with reception, each clock cycle can only send two bits, therefore, can encode in process of transmitting at it, this byte data is carried out to CRC computation of table lookup, treat that last byte sends end, just can send to the CRC check code calculating on link.

Send data encoding process and receive data decode process and can carry out in FPGA inside simultaneously, be independent of each other, and can share a CRC table.This patent is subsidized by national high-tech research Development Technology (863 Program) problem, project number: 2012AA050206.

It should be noted last that: above embodiment is the non-limiting technical scheme of the present invention in order to explanation only, although the present invention is had been described in detail with reference to above-described embodiment, those of ordinary skill in the art is to be understood that; Still can modify or be equal to replacement the present invention, and not depart from any modification or partial replacement of the spirit and scope of the present invention, it all should be encompassed in the middle of claim scope of the present invention.

Claims

1. Ethernet CRC check method, it is characterized in that, when receiving Ethernet one frame data to the data that receive one by one byte carry out CRC computing, record CRC storage that computing obtains, the CRC that this computing is obtained and the last CRC receiving in data compare, and realize CRC check.

2. Ethernet CRC check method according to claim 1, it is characterized in that: the nybble CRC buffering area to be verified that the data that receive is deposited successively in to a FIFO, each byte data of overflowing is tabled look-up, computing is next time brought in the CRC the storage that obtain this byte into, until receive data, complete, the CRC that last CRC buffering area to be verified is received and the CRC calculating compare, and complete CRC check.

3. Ethernet CRC check method according to claim 2, is characterized in that: the described data that often receive a byte deposit data buffer zone in when depositing CRC buffering area to be verified in.

4. Ethernet CRC check method according to claim 3, it is characterized in that: the CRC that described computing obtains and the last CRC receiving in data compare, if two CRC are different, in transmitting procedure, there is error code, the data of data buffer zone storage are invalid.

5. Ethernet CRC check method according to claim 1, it is characterized in that: described until to receive that data complete be to be transmitted when last byte, deposit in after CRC buffer area to be verified, four byte datas that store in CRC buffer area to be verified are CRC code to be verified; The CRC check of last valid data of the last byte of CRC code simultaneously to be verified has been calculated, and the CRC to be verified storing in CRC buffer area to be verified is compared and just can learn whether these frame data have occurred error code in transmitting procedure with the CRC calculating.

6. according to the Ethernet CRC check method described in any one in claim 1-5, in sending data procedures, the data of a byte of every transmission, just table look-up and obtain the CRC of this byte, and bring computing next time into, and until sending, data finish, form final CRC Packet Generation to link.

7. Ethernet CRC check method according to claim 6, is characterized in that: the transmission of described data or the RMII interface receiving by PHY chip complete, and FPGA is connected by RMII interface with PHY chip.