CN103091572A - Signal testing device - Google Patents
Signal testing device Download PDFInfo
- Publication number
- CN103091572A CN103091572A CN2011103430417A CN201110343041A CN103091572A CN 103091572 A CN103091572 A CN 103091572A CN 2011103430417 A CN2011103430417 A CN 2011103430417A CN 201110343041 A CN201110343041 A CN 201110343041A CN 103091572 A CN103091572 A CN 103091572A
- Authority
- CN
- China
- Prior art keywords
- signal
- switch
- switches
- type flip
- testing apparatus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
- G01R31/2806—Apparatus therefor, e.g. test stations, drivers, analysers, conveyors
Abstract
The invention discloses a signal testing device which comprises a processing unit, a switch module, an oscilloscope and a control unit. The switch module comprises a plurality of switches, and first conducting ends of the switches are respectively connected with a plurality of testing points on a to-be-tested printed circuit board. Second conducting ends of the switches are all connected with the oscilloscope through a main signal line. The control unit is connected with control ends of the plurality of switches and used for periodically controlling conduction of the plurality of switches in sequence so that a signal received by the oscilloscope is a periodical signal sequentially comprising a plurality of testing point signals in one period. The oscilloscope further receives control signals produced by the control unit and used for controlling the plurality of switches. The processing unit is connected with the oscilloscope, restores the plurality of testing point signals according to the control signals received by the oscilloscope and the periodical signal, and tests each restored testing point signal. According to the signal testing device, collection and analyzing of the plurality of testing point signals can be achieved only by few channels of the oscilloscope.
Description
Technical field
The present invention relates to a kind of proving installation, particularly a kind of signal-testing apparatus of printed circuit board (PCB).
Background technology
At present, printed circuit board (PCB) has been widely used in the electronic installations such as computer, in the development of electronic installation, in the time of usually need to opening by electronic installation, the signal(l)ing condition of the chip pin of detecting printed circuit board (PCB) checks and carries out mistake and investigate electronic installation.Usually, the detecting point of printed circuit board (PCB) is more, needs to adopt expensive hyperchannel oscillograph, increased the cost of test, and the oscillographic number of active lanes of hyperchannel is also limited, when larger for detecting point quantity, also can't satisfy test request.
Summary of the invention
The invention provides a kind of signal-testing apparatus, it only needs to adopt the oscillograph of a small amount of passage to gather the signal of a plurality of detecting points and to test.
A kind of signal-testing apparatus is used for the some test points on printed circuit board (PCB) are tested, and this signal-testing apparatus comprises a processing unit, a switch module, an oscillograph and a control module.This switch module comprises some switches, and each switch includes the first conduction terminal, the second conduction terminal and control end, and the first conduction terminal of these some switches is connected with these some test points respectively.This oscillograph comprises one first input channel and output channel, and the second conduction terminal of each switch of this switch module all is connected with this first input channel by a main signal line.This control module all is connected with the control end of these some switches, is used for periodically controlling this some switches conducting successively, and making the signal that oscillographic input channel receives is to comprise successively the cyclical signal of these some test point signals in one-period.wherein, this oscillograph also is connected with this control module, the control signal that is used for these some switches of control of reception control unit generation, this processing unit is connected with this oscillographic output channel, for the cyclical signal of the main signal line transmission of obtaining the oscillograph reception and the control signal that control module produces, and according to this control signal, determine each time period of each switch conduction, and according to each time period of each switch conduction, the cyclical signal that oscillograph receives is sampled, the signal sampling that each time period of each switch conduction is corresponding out respectively, thereby the signal with some test points reduces respectively, and the signal of each test point of this reduction is tested.
Signal-testing apparatus of the present invention only need to be used oscillographic minority passage and can complete collection and analysis to a plurality of test point signals.
Description of drawings
Fig. 1 is the inner bay composition of signal-testing apparatus in first embodiment of the invention.
Fig. 2 is the schematic diagram of signal collected by oscillograph in signal-testing apparatus in first embodiment of the invention.
Fig. 3 is the inner bay composition of control module in signal-testing apparatus in first embodiment of the invention.
Fig. 4 is the sequential chart that in first embodiment of the invention, control module produces.
The main element symbol description
| Signal-testing apparatus | 1 |
| Printed circuit board (PCB) | 2 |
| The |
10 |
| |
20 |
| Oscillograph | 30 |
| |
40 |
| Test point | T1~T5 |
| Switch | K1~K5 |
| The first conduction terminal | 101 |
| The second conduction terminal | 102 |
| Control end | 103 |
| Main signal line | |
| Input channel | |
| 301 | |
| Output channel | 302 |
| D type flip flop | D1~ |
| Waveform generator | |
| 201 | |
| Clock pulse generator | 202 |
| Input end | D |
| Output terminal | Q、Q1~Q5 |
| The sequential end | CLK |
Following embodiment further illustrates the present invention in connection with above-mentioned accompanying drawing.
Embodiment
See also Fig. 1 and Fig. 2, be the inner bay composition of signal-testing apparatus in first embodiment of the invention.Signal-testing apparatus 1 is used for the some test point T1 on printed circuit board (PCB) 2 ~ T5 is tested.This signal-testing apparatus 1 comprises switch module 10, control module 20, oscillograph 30 and processing unit 40.This switch module 10 comprises some K switch 1 ~ K5, these some K switch 1 ~ K5 are consistent with the quantity of this some test point T1 ~ T5, and each switch includes in one first conduction terminal 101, the second conduction terminal 102 and control end 103(figure and only marks in a switch).The first conduction terminal 101 of these some K switch 1 ~ K5 is connected respectively one by one with this some test point T1 ~ T5.The second conduction terminal 102 of these some K switch 1 ~ K5 also all is connected with the input channel 301 of oscillograph 30 by a main signal line SL, and the control end 103 of these some K switch 1 ~ K5 all is connected with this control module 20.This control module 20 is used for periodically controlling the conducting successively of these some K switch 1 ~ K5, wherein, in one-period, this some K switch 1 ~ K5 conducting successively makes the signal of test point T1 ~ T5 be transferred to successively the input channel 301 of oscillograph 30 by main signal line SL.Thereby the signal that the input channel 301 of oscillograph 30 receives for as shown in Figure 2 comprise successively the cyclical signal of the signal of test point T1 ~ T5 in one-period.
Wherein, this oscillograph 30 also is connected with control module 20, the control signal of these some K switch 1 ~ K5 of control that reception control unit 20 produces.This processing unit 40 is connected with the output channel 302 of this oscillograph 30, for the cyclical signal of the main signal line SL transmission of obtaining oscillograph 30 receptions and the control signal of control module 20 generations, and according to this control signal, determine each time period of each switch conduction, each time period of K switch 1 conducting for example, each time period of K switch 2 conductings etc., obviously, each time period of each switch conduction, be the time period that in the cyclical signal of main signal line SL transmission, each test point signal exists.Wherein, after oscillograph 30 receives this cyclical signal and control signal, in the storage unit (not shown) of oscillograph 30, this processing unit 40 obtains cyclical signal and the control signal of storing in this oscillograph 30 by output channel 302 with those signal storage.
After this processing unit 40 is determined each time period of each switch conduction, according to each time period of each switch conduction, the cyclical signal that oscillograph 30 receives is sampled, the signal sampling that each time period of each switch conduction is corresponding out respectively, thereby the signal with test point T1 ~ T5 reduces respectively, this processing unit 40 is also analyzed the signal of each test point T1 ~ T5 of this reduction respectively, thereby analyzes the performance of each test point.Analyzing due to this is prior art, therefore do not add to describe at this.
Obviously, in present embodiment, the number of test point T1 ~ T5 and K switch 1 ~ K5 is 5, be only an example, the number of test point is not limited to 5, can be 8,10 etc., the number that also can measure according to actual needs determines, the number of switch equates with the number of test point.
See also Fig. 3 and Fig. 4, wherein Fig. 3 is the inner bay composition of control module 20 in first embodiment of the invention.This control module 20 comprises some d type flip flop D1 ~ D5, waveform generator 201 and clock pulse generator 202.Each d type flip flop D1 ~ D5 includes input end D, output terminal Q and sequential end CLK, and wherein, clock pulse generator 202 all is connected with the sequential end CLK of those d type flip flops D1 ~ D5, and being used for provides clock pulse signal to those d type flip flops D1 ~ D5.Those d type flip flops D1 ~ D5 adopts the structure of series connection, and the output terminal Q of each d type flip flop is connected with the input end D of next d type flip flop, and the output terminal Q of each d type flip flop also is connected with the control end 103 of a switch simultaneously.This waveform generator 201 is connected with the input end D of first d type flip flop D1, for generation of the input end D that triggers waveform to the first d type flip flop D1.
See also Fig. 4, the cycle of the clock pulse signal that this clock pulse generator 202 produces equates with the ON time of each switch, the cycle (hereinafter referred to as the triggering cycle) of the triggering waveform that this waveform generator 201 produces is the product of the ON time of switch number and each switch, in the present embodiment, the triggering cycle of the triggering waveform of these waveform generator 201 generations is the cycle of 5 times of clock pulse signals.In the present embodiment, those d type flip flops D1 ~ D5 is the d type flip flop that the time clock rising edge triggers, character according to d type flip flop, learn that easily the output terminal Q of each d type flip flop will export the high level that continues a clock cycle successively within a triggering cycle of the triggering waveform that waveform generator 201 produces.If the output terminal Q of each d type flip flop is respectively Q1 ~ Q5, as shown in Figure 4, the output terminal Q1 ~ Q5 of those d type flip flops export successively continue one clock cycle signal high level signal.In the present embodiment, these some K switch 1 ~ K5 are the high level actuating switch, thereby in the one-period of the triggering waveform that waveform generator 201 produces, these some K switch 1 ~ K5 incite somebody to action the time of a clock cycle of conducting successively, thereby make the signal of this some test point T1 ~ T5 be transferred to successively main signal line SL, and then transfer to the input channel 301 of oscillograph 30, make the signal of the reception of input channel 301 be as shown in Figure 2 the cyclical signal that comprises successively test point T1 ~ T5 signal in one-period.Wherein, in better embodiment, this K switch 1 ~ K5 is the CMOS pipe.In other embodiments, these some K switch 1 ~ K5 are NMOS pipe or NPN triode.
In the present embodiment, concrete, this waveform generator 201 and clock pulse generator 202 all are connected with oscillograph 30, this oscillograph 30 receives the triggering waveform of these waveform generator 201 generations and the clock pulse signal that clock pulse generator 202 produces, each time period that this processing unit 40 is determined each switch conduction according to triggering waveform and the clock pulse signal of oscillograph 30 receptions.Wherein, this oscillograph 30 can comprise that also two other input channel (not identifying in figure) is connected with waveform generator 201 and clock pulse generator 202 respectively, is used for receiving respectively this triggering waveform and clock pulse signal.As previously mentioned, after this processing unit 40 is determined each time period of each switch conduction, according to each time period of each switch conduction, the cyclical signal that the input channel 301 of oscillograph 30 receives is sampled, respectively the signal sampling that each time period of each switch conduction is corresponding out, thereby respectively with the reduction of the signal of test point T1 ~ T5.
Thereby the present invention only utilizes oscillographic single passage to receive the signal of a plurality of test points, can complete the collection analysis to the test point signal.
Claims (7)
1. a signal-testing apparatus, be used for the some test points on printed circuit board (PCB) are tested, and this signal-testing apparatus comprises a processing unit, it is characterized in that, this signal-testing apparatus also comprises:
One switch module comprises some switches, and each switch includes the first conduction terminal, the second conduction terminal and control end, and the first conduction terminal of these some switches is connected with these some test points respectively;
One oscillograph comprises one first input channel and output channel, and the second conduction terminal of each switch of this switch module all is connected with this first input channel by a main signal line;
One control module, this control module all is connected with the control end of these some switches, be used for periodically controlling this some switches conducting successively, making the signal that oscillographic the first input channel receives is to comprise successively the cyclical signal of these some test point signals in one-period;
wherein, this oscillograph also is connected with this control module, the control signal that is used for these some switches of control of reception control unit generation, this processing unit is connected with this oscillographic output channel, for the cyclical signal of the main signal line transmission of obtaining the oscillograph reception and the control signal that control module produces, and according to this control signal, determine each time period of each switch conduction, and according to each time period of each switch conduction, the cyclical signal that oscillograph receives is sampled, the signal sampling that each time period of each switch conduction is corresponding out respectively, thereby the signal with some test points reduces respectively, and the signal of each test point of this reduction is tested.
2. signal-testing apparatus as claimed in claim 1, it is characterized in that, this control module comprises some d type flip flops, a waveform generator and a clock pulse generator, each d type flip flop includes input end, output terminal and sequential end, wherein, clock pulse generator all is connected with the sequential end of those d type flip flops, and being used for provides clock pulse signal to those d type flip flops; Those d type flip flops adopt the structure of series connection, and the output terminal of each d type flip flop is connected with the input end of next d type flip flop, and the output terminal of each d type flip flop also is connected with the control end of a switch simultaneously; This waveform generator is connected with the input end of first d type flip flop, for generation of triggering the input end of waveform to first d type flip flop.
3. signal-testing apparatus as claimed in claim 2, it is characterized in that, the cycle of the clock pulse signal that this clock pulse generator produces equates with the ON time of each switch, and the triggering cycle of the triggering waveform that this waveform generator produces is the product of the ON time of switch number and each switch.
4. signal-testing apparatus as claimed in claim 3, it is characterized in that, these some switches are the high level actuating switch, within a triggering cycle of the triggering waveform that waveform generator produces, the output terminal of each d type flip flop will be exported the high level that continues a clock cycle successively, thereby in the one-period of the triggering waveform that waveform generator produces, these some switches are incited somebody to action the time of a clock cycle of conducting successively, thereby make the signal of these some test points be transferred to successively main signal line, and then transfer to oscillographic the first input channel, make the signal of the reception of the first input channel comprise successively the cyclical signal of test point signal in one-period.
5. signal-testing apparatus as claimed in claim 3, it is characterized in that, this oscillograph also comprises second, third input channel, this second, third input channel is connected with waveform generator and clock pulse generator respectively, be respectively used to receive this triggering waveform and this clock pulse signal, each time period that this processing unit is determined each switch conduction according to triggering waveform and the clock pulse signal of oscillograph reception.
6. signal-testing apparatus as claimed in claim 4, is characterized in that, these some switches are the CMOS pipe.
7. signal-testing apparatus as claimed in claim 4, is characterized in that, these some switches are NMOS pipe or 0NPN triode.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011103430417A CN103091572A (en) | 2011-11-03 | 2011-11-03 | Signal testing device |
| TW100140801A TW201319593A (en) | 2011-11-03 | 2011-11-08 | Signal testing device |
| US13/491,619 US20130116949A1 (en) | 2011-11-03 | 2012-06-08 | Testing device for testing printed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011103430417A CN103091572A (en) | 2011-11-03 | 2011-11-03 | Signal testing device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103091572A true CN103091572A (en) | 2013-05-08 |
Family
ID=48204382
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011103430417A Pending CN103091572A (en) | 2011-11-03 | 2011-11-03 | Signal testing device |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US20130116949A1 (en) |
| CN (1) | CN103091572A (en) |
| TW (1) | TW201319593A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106872813A (en) * | 2015-12-10 | 2017-06-20 | 中国船舶工业系统工程研究院 | A kind of test equipment universal signal method of testing |
| CN109342927A (en) * | 2018-11-01 | 2019-02-15 | 郑州云海信息技术有限公司 | A kind of measuring signal integrality method and apparatus |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105301476B (en) * | 2015-10-14 | 2018-06-22 | 京东方科技集团股份有限公司 | For the signal-testing apparatus of printed circuit board |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5853774B2 (en) * | 1978-12-29 | 1983-12-01 | 株式会社日立製作所 | information processing equipment |
| US5376834A (en) * | 1993-03-05 | 1994-12-27 | Sgs-Thomson Microelectronics, Inc. | Initialization circuit for automatically establishing an output to zero or desired reference potential |
| TW559668B (en) * | 1999-02-08 | 2003-11-01 | Advantest Corp | Apparatus for and method of measuring a jitter |
| JP5194890B2 (en) * | 2008-03-05 | 2013-05-08 | 富士通セミコンダクター株式会社 | Semiconductor integrated circuit |
| CN101770415A (en) * | 2008-12-27 | 2010-07-07 | 鸿富锦精密工业（深圳）有限公司 | Signal testing device |
| CN101865975B (en) * | 2009-04-16 | 2012-11-21 | 鸿富锦精密工业（深圳）有限公司 | Main board testing system and method |
| US20110234282A1 (en) * | 2010-03-23 | 2011-09-29 | Mosys, Inc. | Method And Circuit For Testing And Characterizing High Speed Signals Using An ON-Chip Oscilloscope |
| US9519020B2 (en) * | 2010-03-31 | 2016-12-13 | SK Hynix Inc. | Semiconductor apparatus and chip selecting method thereof |
| US8901946B2 (en) * | 2010-05-24 | 2014-12-02 | International Business Machines Corporation | Identifying a signal on a printed circuit board under test |
-
2011
- 2011-11-03 CN CN2011103430417A patent/CN103091572A/en active Pending
- 2011-11-08 TW TW100140801A patent/TW201319593A/en unknown
-
2012
- 2012-06-08 US US13/491,619 patent/US20130116949A1/en not_active Abandoned
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106872813A (en) * | 2015-12-10 | 2017-06-20 | 中国船舶工业系统工程研究院 | A kind of test equipment universal signal method of testing |
| CN109342927A (en) * | 2018-11-01 | 2019-02-15 | 郑州云海信息技术有限公司 | A kind of measuring signal integrality method and apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201319593A (en) | 2013-05-16 |
| US20130116949A1 (en) | 2013-05-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100367045C (en) | Circuit connecting line conducting test method based on dichotomy | |
| CN101207591A (en) | Method and system for measuring signal characteristics of data signals transmitted between integrated circuit chips | |
| CN102928772A (en) | Time sequence testing system and testing method thereof | |
| CN102012444A (en) | Oscilloscope and method for testing serial bus signal by using same | |
| CN103091572A (en) | Signal testing device | |
| CN101661078A (en) | Circuit board and testing device thereof | |
| CN103267940A (en) | Multi-module parallel test system and multi-module parallel test method | |
| CN102353867A (en) | Interconnection test equipment and method | |
| CN101452048B (en) | Integrated circuit chip temperature test device and method | |
| CN103336237B (en) | Built-in endurance test system, ageing tester and corresponding endurance test method | |
| CN101706553B (en) | On-chip access time delay measuring circuit and method | |
| CN103267942B (en) | Fault detection method of analog circuit | |
| CN207502674U (en) | A kind of new integrated circuit tester test extended channel system | |
| CN101068264B (en) | Signal collecting device in USB test and USB signal testing method | |
| CN202758047U (en) | Circuit for timely detecting time performance of signal relay of test equipment | |
| CN201804046U (en) | On-line low resistance measurement system under environmental test conditions | |
| CN201251781Y (en) | Signal measuring device | |
| CN201060250Y (en) | Digital type alternating current-direct current local discharge testing apparatus | |
| CN208521158U (en) | A kind of air plug interface signal automatic selection output device | |
| CN105425220B (en) | A kind of digital T/R components transmitting-receiving conversion and reception cloth phase Method Of Time Measurement | |
| CN102109552A (en) | High-frequency and high-speed frequency testing system and method based on phase locking technique | |
| CN102096049A (en) | Testing method of instantaneous power consumption of dynamic power supply | |
| US8008935B1 (en) | Tester and a method for testing an integrated circuit | |
| CN103207367A (en) | Multi-path signal testing method, system and device for printed board | |
| CN100510766C (en) | Test circuit for input-to output speed measurement |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20130508 |