CN101706553B - On-chip access time delay measuring circuit and method - Google Patents
On-chip access time delay measuring circuit and method Download PDFInfo
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- CN101706553B CN101706553B CN2009102368483A CN200910236848A CN101706553B CN 101706553 B CN101706553 B CN 101706553B CN 2009102368483 A CN2009102368483 A CN 2009102368483A CN 200910236848 A CN200910236848 A CN 200910236848A CN 101706553 B CN101706553 B CN 101706553B
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Abstract
The invention discloses an on-chip access time delay measuring circuit and an on-chip access time delay measuring method. The measuring circuit comprises a plurality of stages of measuring units; and from the last stage of measuring unit to the first stage of measuring unit, the resolution of the stages of measuring units is increased progressively in the multiple of 2; and each stage of measuring unit comprises a first multi-route selector, a second multi-route selector, a third multi-route selector, a fourth multi-route selector, a raising edge sensitive trigger, a first time delay unit, a second time delay unit, a third time delay unit, a fourth time delay unit, a fifth time delay unit and a sixth time delay unit.
Description
Technical field
The present invention relates to the semiconductor process techniques field, particularly relate to a kind of on-chip access time delay measuring circuit and method.
Background technology
Along with the development of semiconductor process techniques, transistorized characteristic dimension has been stepped into to the deep-submicron epoch in the current integrated circuit, chip on complexity and the integrated level of design also in continuous raising.Under deep submicron process; The manufacture process of the IC products difficulty that become is controlled, causes chip on logic gate after the manufacturing and path, to have very big time-delay deviation the most at last owing to make the variation of the electrical parameters such as the device saturation current that fluctuation caused, threshold voltage of the various technological parameters that bring.In addition, because the more and more general various defectives that manufacturing process is brought like resistive open circuit, resistive short circuit and the inefficacy of gate oxide transistor layer etc., also will be brought a large amount of time delay defectives to circuit.Thereby, be necessary that very circuit is carried out effective delay testing guarantees that chip can be operated under the specified clock frequency in order to guarantee the quality of chip.In addition, even the defective of hour prolonging that exists in the circuit does not influence circuit and can be operated in specified clock frequency, also will bring serious challenge to chip reliability.For the yield that improves chip and the Time To Market of speed-up chip.Usually just need before the chip volume production, at first carry out chip debugs and corrects the bottle neck area that wrong and identification and the improvement of chip when design influences chip performance.If yet come chip is debugged through the fail message that uses external testing appearance ATE equipment to collect chip.On the one hand, the price of the external testing appearance of high speed is very expensive.In addition, its validity also will receive the influence of using the factors such as dead resistance, stray capacitance and transmission line impedance that the external testing appearance brought.Therefore; Effectively detect through not only can and hour prolonging defective to the long time delay fault in the chip at IC chip indoor design respective via time-delay measuring unit; But also the mistake that can very effective collection chip design and the bottleneck of system performance; Thereby be the information that the debugging of chip before volume production provides mass efficient, reduce the number of times of chip correction, thereby the Time To Market of expedite product.
External researcher has launched corresponding research.There is the researcher to propose scheme of carrying out sheet inner gateway latency measurement based on the vernier lag line as shown in Figure 1.Measure in order to carry out path time delay; It can at first be the test vector that tested path generates a unipath sensitization; Then through tested path is applied this test vector, thereby can produce a corresponding skip signal respectively at the input and output side of tested path.The latency measurement that input port y through being incorporated into the skip signal in the input and output on the tested path respectively metering circuit and x carry out path.Carrying out when path time delay measures, can be through carrying out set to the mode signal, thus the skip signal of being imported by the y end will be selected the data input pin that is input to trigger then through a time delay unit.Similar, the skip signal of importing from the x end will be selected the input end of clock that is input to trigger through the relative less time delay of another time delay value unit.Hence one can see that, and the delay inequality between two skip signal will reduce step by step, thereby can obtain the time delay value size of tested path according to the save value on the trigger in the delay inequality of two time delay unit on every grade of measuring unit and the metering circuit.Obviously, the measurement of carrying out path time delay based on the method for the delay inequality of utilizing two time delay unit can significantly promote the resolution of metering circuit.
Yet this method; Though guaranteed metering circuit a high measuring accuracy can be arranged; But need the measurement range that very many measurement progression reaches to be needed, thereby the area overhead that not only makes metering circuit realize increases significantly, has also reduced the degrees of tolerance of metering circuit to process deviation.In addition, because the result who measures also need read the saving result value in each grade measuring unit in the metering circuit through the scan chain displacement, also make this metering circuit considerable at the time overhead of path time delay measurement.
Summary of the invention
The object of the present invention is to provide a kind of on-chip access time delay measuring circuit and method; It is through in metering circuit, having designed multistage measuring unit; To first order measuring unit, its Measurement Resolution of corresponding every grade increases progressively with two multiple from the afterbody measuring unit; And select whether should deduct Measurement Resolution at the corresponding levels to delay inequality between the input signal of sending into the next stage measuring unit with the comparative result of this grade measuring unit resolution according to the delay inequality between the measurement input signal of every grade of measuring unit; Realize reaching bigger measurement range with considerably less measuring unit progression; Thereby this metering circuit needed time overhead when path time delay is measured is less; And the design hardware expense of this circuit is very little, can provide the good tolerance of process deviation.
Be a kind of on-chip access time delay measuring circuit of realizing that the object of the invention provides, said metering circuit comprises multistage measuring unit, and each grade measuring unit comprises: MUX, rising edge sensitive trigger device and time delay unit, wherein:
First MUX and second MUX, the data terminal with said rising edge sensitive trigger device is connected with clock end respectively, is used for two skip signal of input are transferred to the data terminal and the clock end of said rising edge sensitive trigger device;
The 3rd MUX; Input is the signal that transmits through the 3rd time delay unit and the 5th time delay unit respectively; Output is to be connected with an output of said measuring unit, and being used to select from the signal that measuring unit at the corresponding levels is imported is the output as measuring unit at the corresponding levels of the signal that transmits through the first time delay unit and the 5th time delay unit or the signal that transmits through the 3rd time delay unit;
The 4th MUX; Input is the signal that transmits through the 4th time delay unit and the 6th time delay unit respectively; Output is to be connected with another output of said measuring unit, and being used to select from another signal of measuring unit input at the corresponding levels is another output as measuring unit at the corresponding levels of the signal that transmits through the second time delay unit and the 6th time delay unit or through the 4th time delay unit;
Rising edge sensitive trigger device; Be used for delay inequality according to two skip signal that receive; Judge whether resolution greater than measuring unit at the corresponding levels; If two input skip signal are then respectively through the first time delay unit and the second time delay unit and the 5th time delay unit and the arrival output of the 6th time delay unit, the delay inequality between said two output hopping signals deducts the value of the Measurement Resolution of measuring unit at the corresponding levels; Otherwise, arriving output through the 3rd time delay unit and the 4th time delay unit, the delay inequality between said two output hopping signals remains unchanged;
The first time delay unit and the second time delay unit are connected with two inputs of said measuring unit respectively, and are connected to two output terminals of said measuring unit through the 5th and the 6th time delay unit and the 3rd MUX and the 4th MUX respectively;
The 3rd time delay unit and the 4th time delay unit are connected with the 4th MUX with two inputs and the 3rd MUX respectively;
The 5th time delay unit and the 6th time delay unit are connected with the 4th MUX with the second time delay unit and the 3rd MUX with the first time delay unit respectively.
In the said multistage measuring unit, to first order measuring unit, the Measurement Resolution of every grade of measuring unit increases progressively with 2 multiple from the afterbody measuring unit.
Said the 3rd time delay unit and the 4th time delay unit; In each grade measuring unit, have identical time delay value size, and the size of this time delay value need guarantee that signal saltus step rising edge sensitive trigger device in this grade measuring unit before arriving third and fourth MUX has had a stable save value.
Said the 5th time delay unit and the 6th time delay unit; In each grade measuring unit, have identical time delay value size, and the size of this time delay value need guarantee that signal saltus step rising edge sensitive trigger device in this grade measuring unit before arriving third and fourth MUX has had a stable save value.
Said metering circuit also comprises:
The delay compensation module; Be arranged on the input end of said metering circuit; Comprise the first delay compensation unit and the second delay compensation unit, compensate each grade measuring unit storage data needed Times Created through utilizing time delay value between the said first delay compensation unit and the second delay compensation unit.
Said metering circuit also comprises:
Two signal saltus step direction conversioning circuit modules, the two ends of the tested path that is connected to through two MUXs respectively, and be connected with two inputs of said metering circuit, be used for converting any direction skip signal of input to the rising skip signal.
For realizing the object of the invention, a kind of on-chip access time delay measuring method also is provided, said method comprises the following steps:
Step 200. is from said crucial path, and selection need be carried out the destination path of latency measurement;
Step 500: metering circuit is configured to shift mode to metering circuit through the mode signal that resets after accomplishing latency measurement, reads through displacement scanning the Measurement Resolution of the said measuring unit of preserving at the corresponding levels at output terminal;
Step 600: return step 100, select other crucial path to proceed the path time delay measurement.
Said step 400 comprises the following steps:
The test vector that step 410. will generate for tested path in advance is to being applied to said destination path; Make the input and output at said destination path produce a corresponding skip signal; And the skip signal of said input is input to said metering circuit first order measuring unit one measure input end, another of first order measuring unit that the skip signal of said output is input to said metering circuit measured input end;
The skip signal of the said input of step 420. arrives first MUX of measuring unit at the corresponding levels through the first time delay unit of measuring unit at the corresponding levels; Arrive the data terminal of the rising edge sensitive trigger device of measuring unit at the corresponding levels again; The skip signal of said output arrives the clock end of the rising edge sensitive trigger device of measuring unit at the corresponding levels through the second time delay unit of measuring unit at the corresponding levels, the skip signal of said input and the skip signal of output also will be respectively through the 3rd time delay unit and the 4th time delay unit of measuring unit at the corresponding levels;
The rising edge sensitive trigger device of the said measuring unit at the corresponding levels of step 430. judges whether the resolution greater than measuring unit at the corresponding levels according to the delay inequality of two skip signal that receive, if, execution in step 440; Otherwise, execution in step 450;
The rising edge sensitive trigger device of step 440. measuring unit at the corresponding levels is preserved a logic high; Two input signals of measuring unit will be respectively through the first time delay unit and the 5th time delay unit and the second time delay unit and the arrival output of the 6th time delay unit of measuring unit at the corresponding levels, and the delay inequality of two output hopping signals of measuring unit at the corresponding levels will deduct the Measurement Resolution of measuring unit at the corresponding levels;
The delay inequality that step 450. is exported between said two skip signal through the 3rd time delay unit and the 4th time delay unit of measuring unit at the corresponding levels remains unchanged;
For realizing that the object of the invention also provides a kind of measuring unit that is used for on-chip access time delay measuring circuit, said measuring unit comprises: MUX, rising edge sensitive trigger device and time delay unit, wherein:
First MUX and second MUX, the data terminal with said rising edge sensitive trigger device is connected with clock end respectively, is used for two skip signal of input are transferred to the data terminal and the clock end of said rising edge sensitive trigger device;
The 3rd MUX; Input is the signal that transmits through the 3rd time delay unit and the 5th time delay unit respectively; Output is to be connected with an output of said measuring unit, and being used to select from the signal that measuring unit at the corresponding levels is imported is the output as measuring unit at the corresponding levels of the signal that transmits through the first time delay unit and the 5th time delay unit or the signal that transmits through the 3rd time delay unit;
The 4th MUX; Input is the signal that transmits through the 4th time delay unit and the 6th time delay unit respectively; Output is to be connected with another output of said measuring unit, and being used to select from another signal of measuring unit input at the corresponding levels is another output as measuring unit at the corresponding levels of the signal that transmits through the second time delay unit and the 6th time delay unit or through the 4th time delay unit;
Rising edge sensitive trigger device; Be used for delay inequality according to two skip signal that receive; Judge whether resolution greater than measuring unit at the corresponding levels; If two input skip signal are then respectively through the first time delay unit and the second time delay unit and the 5th time delay unit and the arrival output of the 6th time delay unit, the delay inequality between said two output hopping signals deducts the value of the Measurement Resolution of measuring unit at the corresponding levels; Otherwise, arriving output through the 3rd time delay unit and the 4th time delay unit, the delay inequality between said two output hopping signals remains unchanged;
The first time delay unit and the second time delay unit are connected with two inputs of said measuring unit respectively, and are connected to two output terminals of said measuring unit through the 5th and the 6th time delay unit and the 3rd MUX and the 4th MUX respectively;
The 3rd time delay unit and the 4th time delay unit are connected with the 4th MUX with two inputs and the 3rd MUX respectively;
The 5th time delay unit and the 6th time delay unit are connected with the 4th MUX with the second time delay unit and the 3rd MUX with the first time delay unit respectively.
Said the 3rd time delay unit and the 4th time delay unit; In each grade measuring unit, have identical time delay value size, and this time delay value need guarantee that signal saltus step rising edge sensitive trigger device in this grade measuring unit before arriving third and fourth MUX has had a stable save value.
Said the 5th time delay unit and the 6th time delay unit; In each grade measuring unit, have identical time delay value size, and the size of this time delay value need guarantee that signal saltus step rising edge sensitive trigger device in this grade measuring unit before arriving third and fourth MUX has had a stable save value.
The invention has the beneficial effects as follows:
1. a kind of on-chip access time delay measuring circuit of the present invention and method can be used in the delay failure of IC products and hour prolong defective and effectively detect, thereby guarantee the Performance And Reliability of circuit.In addition, can also a large amount of effective informations relevant with the chip failure type be provided for the debugging of chip before volume production;
2. a kind of on-chip access time delay measuring circuit of the present invention and method can reach bigger measurement range with considerably less measuring unit progression, thereby this metering circuit needed time overhead when path time delay is measured are less;
3. a kind of on-chip access time delay measuring circuit of the present invention, the design hardware expense is very little, and can provide the good tolerance of process deviation;
4. the delay compensation unit among the present invention can improve the accuracy of time delay measures and the minimum Measurement Resolution that improves metering circuit.
Description of drawings
Fig. 1 is the circuit structure diagram that carries out sheet inner gateway latency measurement in the prior art based on the vernier lag line;
Fig. 2 is the structural representation of a kind of on-chip access time delay measuring circuit of the present invention;
Fig. 3 is the structural representation of measuring unit among the present invention;
Fig. 4 is the structural representation of an embodiment of a kind of on-chip access time delay measuring circuit of the present invention;
Fig. 5 is the structural representation of a kind of on-chip access time delay measuring circuit of the present invention on IC chip;
Fig. 6 is the signal saltus step direction conversioning circuit structural drawing that is proposed in the document;
Fig. 7 (a) and Fig. 7 (b) are respectively when having different delay inequalities between measurement input signal y1 and the x1 of corresponding first order time-delay measuring unit, the variation relation synoptic diagram of the delay inequality between itself and measurement output signals y2 and the x2;
Fig. 8 is the process flow diagram of a kind of on-chip access time delay measuring method of the present invention;
Fig. 9 is the process flow diagram of step 400 among the present invention.
Embodiment
In order to make the object of the invention, technical scheme and advantage clearer,, a kind of on-chip access time delay measuring circuit of the present invention and method are further elaborated below in conjunction with accompanying drawing and embodiment.Should be appreciated that specific embodiment described herein only in order to explanation the present invention, and be not used in qualification the present invention.
A kind of on-chip access time delay measuring circuit of the present invention and method; Be a kind of integrated circuit on-chip access time delay measuring circuit and method of the low expense based on vernier lag line principle; It is through in metering circuit, having designed multistage measuring unit; To first order measuring unit, its Measurement Resolution of corresponding every grade increases progressively with two multiple from the afterbody measuring unit; And select whether should deduct Measurement Resolution at the corresponding levels to delay inequality between the input signal of sending into the next stage measuring unit with the comparative result of this grade measuring unit resolution according to the delay inequality between the measurement input signal of every grade of measuring unit; Realize reaching bigger measurement range with considerably less measuring unit progression; Thereby this metering circuit needed time overhead when path time delay is measured is less; And the design hardware expense of this circuit is very little, can provide the good tolerance of process deviation.
Sort circuit and method can be used for IC products is carried out the test of delay failure and the debugging before the chip volume production.
Introduce a kind of on-chip access time delay measuring circuit of the present invention in detail below in conjunction with above-mentioned target, Fig. 2 is the structural representation of a kind of on-chip access time delay measuring circuit of the present invention, and is as shown in Figure 2, and said metering circuit 10 comprises:
The delay inequality of comparing two time delay unit of available technology adopting is carried out the method for latency measurement; Metering circuit of the present invention only needs considerably less measuring unit progression just can reach very large latency measurement scope, thus the time overhead that is spent can realize less area expense and latency measurement the time.
Fig. 3 is the structural representation of measuring unit among the present invention, and is as shown in Figure 3, and said measuring unit 1 comprises:
The first MUX M1 is connected with the data terminal of said rising edge sensitive trigger device 2, is used for a skip signal of input is transferred to the data terminal of said rising edge sensitive trigger device 2;
The second MUX M2 is connected with the clock end of said rising edge sensitive trigger device 2, is used for another skip signal of input is transferred to the clock end of said rising edge sensitive trigger device 2;
The 3rd MUX M3; Input is the signal that the 3rd time delay unit A1 and the 5th time delay unit B 1 transmit; Output is to be connected with an output of said measuring unit, and being used to select from the signal y that measuring unit at the corresponding levels is imported is the signal that transmits through the first time delay unit N1 and the 5th time delay unit B 1 or the signal that transmits through the 3rd time delay unit A1 output y ' as measuring unit at the corresponding levels;
The 4th MUX M4; Input is the signal that the 4th time delay unit A2 and the 6th time delay unit B 2 transmit; Output is to be connected with another output of said measuring unit, and being used to select from measuring unit input signal x at the corresponding levels is the signal that transmits through the second time delay unit N2 and the 6th time delay unit B 2 or through the 4th time delay unit A2 output x ' as measuring unit at the corresponding levels;
Preferably, because metering circuit of the present invention can be used for measuring a large amount of different path time delays, therefore can be selected to the target path to different tested paths and send into and carry out latency measurement in the metering circuit through MUX or coding-decoding circuit.
A rising edge sensitive trigger device 2; Be used for delay inequality according to two skip signal that receive; Judge whether resolution greater than measuring unit at the corresponding levels; If two input skip signal are then respectively through the first time delay unit and the second time delay unit and the 5th time delay unit and the arrival output of the 6th time delay unit, the delay inequality between said two output hopping signals deducts the value of the Measurement Resolution of measuring unit at the corresponding levels; Otherwise, arriving output through the 3rd time delay unit and the 4th time delay unit, the delay inequality between said two output hopping signals remains unchanged;
Said rising edge sensitive trigger device; Saltus step delay inequality (signal on supposition y and the x is the rising skip signal earlier) according to input signal x that receives and input signal y; Judging that input y goes up time that saltus step than input x saltus step takes place takes place whether is worth the resolution greater than measuring unit at the corresponding levels in advance; If; Delay inequality between two output hopping signals will deduct the Measurement Resolution value of measuring unit at the corresponding levels; Simultaneously the rising edge sensitive trigger device in the measuring unit at the corresponding levels will keep a logic high, make two input skip signal y and the x first time delay unit N1 and the 5th time delay unit B 1 and the second time delay unit N2 and the 6th time delay unit B 2 through being connected separately respectively, pass through the 3rd MUX M3 and the 4th MUX M4 arrival more respectively and export; Simultaneously, the delay inequality between two skip signal of y ' and x ' deducts the value of the Measurement Resolution of measuring unit at the corresponding levels; Otherwise; Rising edge sensitive trigger device in the measuring unit at the corresponding levels will keep a logic low; Two input skip signal y will be via the 3rd time delay unit A1 that is connected separately and the 4th time delay unit A2 with x; And propagate into output through the 3rd MUX M3 and the 4th MUX M4 respectively, and the delay inequality between two output hopping signal y ' and the x ' remains unchanged.Obviously, the logic level value record of the rising edge sensitive trigger device in the measuring unit at the corresponding levels two output hopping signal time delay differences situations of change with respect to two input skip signal delay inequalities.If it has preserved a logic high, mean that the delay inequality between the output hopping signal is compared with the delay inequality between the input signal, reduced Measurement Resolution at the corresponding levels.Otherwise delay inequality does not change.
But as a kind of embodiment; The 5th time delay unit B 1 that in each grade measuring unit, designs has identical time delay value size with the 6th time delay unit B 2; And the size of its value need guarantee to import skip signal before propagating arrival MUX M3 and M4 respectively, and the rising edge sensitive trigger device in this grade measuring unit has had a stable save value.Equally; The 3rd time delay unit A1 also has identical time delay value size with the 4th time delay unit A2; And its time delay value also should design enough big; After guaranteeing that the output of rising edge sensitive trigger device is stable, input skip signal y and x just can arrive the input of MUX M3 and M4 after via the 3rd time delay unit A1 and the 4th time delay unit A2 respectively.Be used to guarantee that the rising edge sensitive trigger device output terminal at each grade can have a stable signal to select whether should deduct the input signal delay inequality of sending into the next stage measuring unit Measurement Resolution value of measuring unit at the corresponding levels.
The first time delay unit N1 is connected with an input of said measuring unit, and is connected to an output terminal of said measuring unit through the 3rd MUX M3;
The second time delay unit N2 is connected with another input of said measuring unit, and is connected to another output terminal of said measuring unit through the 4th MUX M4;
Wherein the delay inequality of the first time delay unit N1 and the second time delay unit N2 is represented the Measurement Resolution of every grade of measuring unit.
The 3rd time delay unit A1 and the 4th time delay unit A2 are connected with the 4th MUX M4 with two inputs and the 3rd MUX M3 respectively;
The 5th time delay unit B 1 and the 6th time delay unit B 2 are connected with the 4th MUX M4 with the second time delay unit N2 and the 3rd MUX M3 with the first time delay unit N1 respectively;
As shown in Figure 2, suppose that the time delay value of the first time delay unit N1 in each grade time-delay measuring unit is D
Up, suppose that equally the time delay value of the second time delay unit N2 is made as D
LowThe Measurement Resolution of each grade time-delay measuring unit is defined as the delay inequality of these two time delay unit.
When carrying out the metering circuit design, to first order time-delay measuring unit, the Measurement Resolution of each grade increases progressively with two multiple from afterbody.
Fig. 4 is the structural representation of an embodiment of a kind of on-chip access time delay measuring circuit of the present invention, and is as shown in Figure 4, and the input end of said metering circuit also comprises:
Because in the latency measurement of reality; The needed Time Created that can not ignore the rising edge sensitive trigger device storage data in each grade measuring unit; Thus; The present invention has designed a delay compensation module at the input end of metering circuit, has promptly designed the first delay compensation unit and the second delay compensation unit in the y of metering circuit input and x input end respectively.Obviously, utilize said two delay compensation unit delay inequalities can realize high-precision delay compensation.Preferably, if in the delay compensation module, also compensate half big or small time delay value of afterbody measuring unit resolution, the precision of so whole metering circuit also will double.
Preferably, adopt said delay compensation module among the present invention, can improve accuracy and precision that path time delay is measured, can also improve the resolution of whole metering circuit.
Fig. 5 is the structural representation of a kind of on-chip access time delay measuring circuit of the present invention on IC chip, and of Fig. 5, said metering circuit also comprises:
Two signal saltus step direction conversioning circuit module TR1 and TR2, the two ends of the tested path that is connected to through MUX respectively, and be connected with the input of metering circuit, be used for converting any direction skip signal of input to the rising skip signal.
Because when the path time delay of reality is measured, possibly compare serious situation etc. for time delay value on the activation pathway, the input and output of tested path all might not be the rising skip signal.Fig. 6 is Ming-ChienTsai; Ching-HwaCheng; And Chiou-Mao Yang, " An All-DigitalHigh-Precision Built-In Delay Time Measurement Circuit " Proceedingsof 26th IEEE VLSI Test Symposium, 2008; The signal saltus step direction conversioning circuit structural drawing that is proposed among the pp.249-254, it can convert any direction skip signal of input in output rising skip signal.Like the path time delay measurement structure synoptic diagram among Fig. 5, in test circuit of the present invention, also increased corresponding signal saltus step direction conversioning circuit TR module, signal saltus step direction conversioning circuit promptly shown in Figure 6.
But as a kind of embodiment, below through considering that first order measuring unit is the mode of operation that example is introduced each time-delay measuring unit in the metering circuit: at first ignore in each grade measuring unit storage data needed Times Created at this.Right through on tested path, applying the test vector that generates in advance, in the output of tested path, will generate the skip signal of expecting.We can be input to the skip signal in the tested path input measurement input end y1 of first order measuring unit, with the measurement input end x1 of the skip signal input first order measuring unit in the tested path output.Obviously; If the skip signal of measuring on the input y1 arrives than the skip signal on the x1 is early; And its delay inequality is greater than the Measurement Resolution value of first order measuring unit; Rising edge sensitive trigger device in the first order measuring unit will be preserved a logic high so, and two input skip signal will be passed through N1 and B1 and N2 and B2 respectively, arrive output terminal y2 and x2 through the 3rd MUX and the 4th MUX respectively again.Obviously, the delay inequality between two output hopping signals will reduce the Measurement Resolution value of measuring unit at the corresponding levels, the variation that the logic high of measuring in the measuring unit at the corresponding levels has simultaneously write down this delay inequality; Otherwise the delay inequality between two output hopping signals remains unchanged, and two skip signal that receive via the A1 and the A2 time delay unit that connect separately, are propagated into output terminal y2 and x2 through the 3rd MUX and the 4th MUX then.Fig. 7 (a) and Fig. 7 (b) are respectively when having different delay inequalities between measurement input signal y1 and the x1 of corresponding first order time-delay measuring unit, the variation relation synoptic diagram of the delay inequality between itself and measurement output signals y2 and the x2.Can find out that from Fig. 7 (a) when the signal time delay difference that is input to measuring unit during greater than Measurement Resolution at the corresponding levels, the delay inequality between the output signal will deduct the Measurement Resolution value of measuring unit at the corresponding levels.Otherwise, can find out that from Fig. 7 (b) delay inequality between the output signal will remain unchanged.
Corresponding to a kind of on-chip access time delay measuring circuit of the present invention, a kind of on-chip access time delay measuring method also is provided, Fig. 8 is the process flow diagram of a kind of on-chip access time delay measuring method of the present invention, and is as shown in Figure 8, said method comprises the following steps:
The method of the crucial path that the specific time delay threshold value of said selection is above is a prior art, gives unnecessary details no longer one by one at this.
Step 200. is from said crucial path, and selection need be carried out the destination path of latency measurement;
The crucial path of finding out in the said step 100 is a lot of bars, and metering circuit of the present invention need be measured it one by one, therefore in step 200 through MUX is set, the critical path that selection need be carried out latency measurement is as destination path.
Step 300 through the reset signal that resets, is initialized to logic low to all the rising edge sensitive trigger devices in the metering circuit; Through set mode signal, be arranged to the latency measurement pattern to metering circuit;
Said metering circuit has two kinds of patterns, is respectively latency measurement pattern and shift mode.
Step 500: metering circuit is configured to shift mode to metering circuit through the mode signal that resets after accomplishing latency measurement, reads through displacement scanning the Measurement Resolution of the said measuring unit of preserving at the corresponding levels at output terminal;
Step 600: return step 200, select other crucial path to proceed the path time delay measurement.
Fig. 9 is the process flow diagram of step 400 among the present invention, and is as shown in Figure 9, and said step 400 comprises the following steps:
The test vector that step 410. will generate for tested path in advance is to being input to said destination path; Make the input and output at said destination path produce a corresponding skip signal respectively; And the skip signal of said input is input to metering circuit first order measuring unit one measure input end, another of first order measuring unit that the skip signal of output is input to metering circuit measured input end;
It is right to be applied as the test vector that tested path generates in advance; Make the input and output at tested path produce a corresponding skip signal y and x respectively; The skip signal y of the input of said tested path is input to metering circuit first order measuring unit one measure input end, another of first order measuring unit that the skip signal x of tested path output is input to metering circuit measured input end;
The skip signal of the said input of step 420. arrives first MUX of measuring unit at the corresponding levels through the first time delay unit of measuring unit at the corresponding levels, arrives the data terminal of the rising edge sensitive trigger device of measuring unit at the corresponding levels again; The skip signal of said output arrives the clock end of the rising edge sensitive trigger device of measuring unit at the corresponding levels through the second time delay unit of measuring unit at the corresponding levels; The skip signal of said input and the skip signal of output also will be respectively through the 3rd time delay unit A1 and the 4th time delay unit A2 of measuring unit at the corresponding levels;
The rising edge sensitive trigger device of the said measuring unit at the corresponding levels of step 430. judges whether the resolution greater than measuring unit at the corresponding levels according to the delay inequality of two skip signal that receive, if, execution in step 440; Otherwise, execution in step 450;
The rising edge sensitive trigger device of step 440. measuring unit at the corresponding levels is preserved a logic high; Two input signals of measuring unit will be respectively through the first time delay unit N1 and the 5th time delay unit B 1 and the second time delay unit N2 and the 2 arrival outputs of the 6th time delay unit B of measuring unit at the corresponding levels, and the delay inequality of two output hopping signals of measuring unit at the corresponding levels will deduct the Measurement Resolution of measuring unit at the corresponding levels;
Obviously, the variation that the logic high that rising edge sensitive trigger device is preserved in the measuring unit at the corresponding levels has write down this delay inequality.
In this step; The rising edge sensitive trigger device of measuring unit at the corresponding levels is preserved a logic high; Two input signals of measuring unit will be respectively through the first time delay unit N1 and the 5th time delay unit B 1 and the second time delay unit N2 and the 2 arrival outputs of the 6th time delay unit B of measuring unit at the corresponding levels, and the Measurement Resolution that the delay inequality of two output hopping signals of measuring unit at the corresponding levels will deduct measuring unit at the corresponding levels arrives output through the 3rd MUX M3 and the 4th MUX M4 again;
In this step, the delay inequality between two skip signal remains unchanged, and two skip signal that receive are propagated into output via the 3rd time delay unit and the 4th time delay unit that connect separately through the 3rd MUX M3 and the 4th MUX M4.
Beneficial effect of the present invention is:
1. a kind of on-chip access time delay measuring circuit of the present invention and method can be used in the delay failure of IC products and hour prolong defective and effectively detect, thereby guarantee the Performance And Reliability of circuit.In addition, can also a large amount of effective informations relevant with the chip failure type be provided for the debugging of chip before volume production;
2. a kind of on-chip access time delay measuring circuit of the present invention and method can reach bigger measurement range with considerably less measuring unit progression, thereby this metering circuit needed time overhead when path time delay is measured are less;
3. a kind of on-chip access time delay measuring circuit of the present invention, the design hardware expense is very little, and can provide the good tolerance of process deviation;
4. the delay compensation unit among the present invention can improve the accuracy of time delay measures and the minimum Measurement Resolution that improves metering circuit.
In conjunction with the drawings to the description of the specific embodiment of the invention, others of the present invention and characteristic are conspicuous to those skilled in the art.
More than specific embodiment of the present invention is described and explains it is exemplary that these embodiment should be considered to it, and be not used in and limit the invention, the present invention should make an explanation according to appended claim.
Claims (11)
1. an on-chip access time delay measuring circuit is characterized in that, said metering circuit comprises: multistage measuring unit, and each grade measuring unit comprises: MUX, rising edge sensitive trigger device and time delay unit, wherein:
First MUX and second MUX, the data terminal with said rising edge sensitive trigger device is connected with clock end respectively, is used for two skip signal of input are transferred to the data terminal and the clock end of said rising edge sensitive trigger device;
The 3rd MUX; Input is the signal that transmits through the 3rd time delay unit and the 5th time delay unit respectively; Output is to be connected with an output of said measuring unit, and being used to select from the signal that measuring unit at the corresponding levels is imported is the output as measuring unit at the corresponding levels of the signal that transmits through the first time delay unit and the 5th time delay unit or the signal that transmits through the 3rd time delay unit;
The 4th MUX; Input is the signal that transmits through the 4th time delay unit and the 6th time delay unit respectively; Output is to be connected with another output of said measuring unit, and being used to select from another signal of measuring unit input at the corresponding levels is another output as measuring unit at the corresponding levels of the signal that transmits through the second time delay unit and the 6th time delay unit or through the 4th time delay unit;
Rising edge sensitive trigger device; Be used for delay inequality according to two skip signal that receive; Judge whether resolution greater than measuring unit at the corresponding levels; If two input skip signal then arrive output through the first time delay unit and the second time delay unit and the 5th time delay unit and the 6th time delay unit respectively, the delay inequality between two output hopping signals deducts the value of the Measurement Resolution of measuring unit at the corresponding levels; Otherwise, arriving output through the 3rd time delay unit and the 4th time delay unit, the delay inequality between two output hopping signals remains unchanged;
The first time delay unit and the second time delay unit are connected with two inputs of said measuring unit respectively, and are connected to two output terminals of said measuring unit through the 5th and the 6th time delay unit and the 3rd MUX and the 4th MUX respectively;
The 3rd time delay unit and the 4th time delay unit are connected with the 4th MUX with two inputs and the 3rd MUX respectively;
The 5th time delay unit and the 6th time delay unit are connected with the 4th MUX with the second time delay unit and the 3rd MUX with the first time delay unit respectively.
2. on-chip access time delay measuring circuit according to claim 1 is characterized in that, in the said multistage measuring unit, to first order measuring unit, the Measurement Resolution of every grade of measuring unit increases progressively with 2 multiple from the afterbody measuring unit.
3. on-chip access time delay measuring circuit according to claim 1; It is characterized in that; Said the 3rd time delay unit and the 4th time delay unit; In each grade measuring unit, have identical time delay value size, and this time delay value need guarantee that signal saltus step rising edge sensitive trigger device in this grade measuring unit before arriving third and fourth MUX has had a stable save value.
4. on-chip access time delay measuring circuit according to claim 1; It is characterized in that; Said the 5th time delay unit and the 6th time delay unit; In each grade measuring unit, have identical time delay value size, and the size of this time delay value need guarantee that signal saltus step rising edge sensitive trigger device in this grade measuring unit before arriving third and fourth MUX has had a stable save value.
5. on-chip access time delay measuring circuit according to claim 1 is characterized in that, said metering circuit also comprises:
The delay compensation module; Be arranged on the input end of said metering circuit; Comprise the first delay compensation unit and the second delay compensation unit, compensate each grade measuring unit storage data needed Times Created through utilizing time delay value between the said first delay compensation unit and the second delay compensation unit.
6. on-chip access time delay measuring circuit according to claim 1 is characterized in that, said metering circuit also comprises:
Two signal saltus step direction conversioning circuit modules, the two ends of the tested path that is connected to through two MUXs respectively, and be connected with two inputs of said metering circuit, be used for converting any direction skip signal of input to the rising skip signal.
7. an on-chip access time delay measuring method is characterized in that, said method comprises the following steps:
Step 100. adopts static or the statistical timing analysis method is selected the above crucial path of specific time delay threshold value;
Step 200. is from said crucial path, and selection need be carried out the destination path of latency measurement;
Step 300. is initialized to logic low to all the rising edge sensitive trigger devices in the metering circuit through reset signal; Through asserts signal, be arranged to the latency measurement pattern to metering circuit;
Step 400. utilizes said metering circuit to measure the time delay of tested path; Select whether should deduct Measurement Resolution at the corresponding levels to delay inequality between the input signal of sending into the next stage measuring unit with the comparative result of this grade measuring unit resolution according to the delay inequality between the measurement input signal of every grade of measuring unit, select simultaneously whether the rising edge sensitive trigger device in the measuring unit at the corresponding levels to be kept a logic high;
Step 500: metering circuit is configured to shift mode to metering circuit through reset signal after accomplishing latency measurement, reads through displacement scanning the Measurement Resolution of the said measuring unit of preserving at the corresponding levels at output terminal;
Step 600: return step 100, select other crucial path to proceed the path time delay measurement.
8. on-chip access time delay measuring method according to claim 7 is characterized in that said step 400 comprises the following steps:
The test vector that step 410. will generate for tested path in advance is to being applied to said destination path; Make the input and output at said destination path produce a corresponding skip signal; And the skip signal of said input is input to said metering circuit first order measuring unit one measure input end, another of first order measuring unit that the skip signal of said output is input to said metering circuit measured input end;
The skip signal of the said input of step 420. arrives first MUX of measuring unit at the corresponding levels through the first time delay unit of measuring unit at the corresponding levels; Arrive the data terminal of the rising edge sensitive trigger device of measuring unit at the corresponding levels again; The skip signal of said output arrives the clock end of the rising edge sensitive trigger device of measuring unit at the corresponding levels through the second time delay unit of measuring unit at the corresponding levels, the skip signal of said input and the skip signal of output also will be respectively through the 3rd time delay unit and the 4th time delay unit of measuring unit at the corresponding levels;
The rising edge sensitive trigger device of the said measuring unit at the corresponding levels of step 430. judges whether the Measurement Resolution greater than measuring unit at the corresponding levels according to the delay inequality of two skip signal that receive, if, execution in step 440; Otherwise, execution in step 450;
The rising edge sensitive trigger device of step 440. measuring unit at the corresponding levels is preserved a logic high; Two input signals of measuring unit will be respectively through the first time delay unit and the 5th time delay unit and the second time delay unit and the arrival output of the 6th time delay unit of measuring unit at the corresponding levels, and the delay inequality of two output hopping signals of measuring unit at the corresponding levels will deduct the Measurement Resolution of measuring unit at the corresponding levels;
The delay inequality that step 450. is exported between said two skip signal through the 3rd time delay unit and the 4th time delay unit of measuring unit at the corresponding levels remains unchanged;
Step 460. judges whether said measuring unit is the afterbody measuring unit, if then execution in step 500, otherwise two skip signal input next stage measuring units with output return step 420.
9. a measuring unit that is used for on-chip access time delay measuring circuit is characterized in that, said measuring unit comprises: MUX, rising edge sensitive trigger device and time delay unit, wherein:
First MUX and second MUX, the data terminal with said rising edge sensitive trigger device is connected with clock end respectively, is used for two skip signal of input are transferred to the data terminal and the clock end of said rising edge sensitive trigger device;
The 3rd MUX; Input is the signal that transmits through the 3rd time delay unit and the 5th time delay unit respectively; Output is to be connected with an output of said measuring unit, and being used to select from the signal that measuring unit at the corresponding levels is imported is the output as measuring unit at the corresponding levels of the signal that transmits through the first time delay unit and the 5th time delay unit or the signal that transmits through the 3rd time delay unit;
The 4th MUX; Input is the signal that transmits through the 4th time delay unit and the 6th time delay unit respectively; Output is to be connected with another output of said measuring unit, and being used to select from another signal of measuring unit input at the corresponding levels is another output as measuring unit at the corresponding levels of the signal that transmits through the second time delay unit and the 6th time delay unit or through the 4th time delay unit;
Rising edge sensitive trigger device; Be used for delay inequality according to two skip signal that receive; Judge whether resolution greater than measuring unit at the corresponding levels; If two input skip signal then arrive output through the first time delay unit and the second time delay unit and the 5th time delay unit and the 6th time delay unit respectively, the delay inequality between two output hopping signals deducts the value of the Measurement Resolution of measuring unit at the corresponding levels; Otherwise, arriving output through the 3rd time delay unit and the 4th time delay unit, the delay inequality between two output hopping signals remains unchanged;
The first time delay unit and the second time delay unit are connected with two inputs of said measuring unit respectively, and are connected to two output terminals of said measuring unit through the 5th and the 6th time delay unit and the 3rd MUX and the 4th MUX respectively;
The 3rd time delay unit and the 4th time delay unit are connected with the 4th MUX with two inputs and the 3rd MUX respectively;
The 5th time delay unit and the 6th time delay unit are connected with the 4th MUX with the second time delay unit and the 3rd MUX with the first time delay unit respectively.
10. the measuring unit that is used for on-chip access time delay measuring circuit according to claim 9; It is characterized in that; Said the 3rd time delay unit and the 4th time delay unit; In each grade measuring unit, have identical time delay value size, and this time delay value need guarantee that signal saltus step rising edge sensitive trigger device in this grade measuring unit before arriving third and fourth MUX has had a stable save value.
11. the measuring unit that is used for on-chip access time delay measuring circuit according to claim 9; It is characterized in that; Said the 5th time delay unit and the 6th time delay unit; In each grade measuring unit, have identical time delay value size, and the size of this time delay value need guarantee that signal saltus step rising edge sensitive trigger device in this grade measuring unit before arriving third and fourth MUX has had a stable save value.
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| CN102495349B (en) * | 2011-12-12 | 2014-07-02 | 中国科学院深圳先进技术研究院 | Path delay on-line measurement circuit |
| CN106407486A (en) * | 2015-07-27 | 2017-02-15 | 深圳市中兴微电子技术有限公司 | Process deviation detection circuit and method |
| CN105629159B (en) * | 2015-12-31 | 2018-08-21 | 上海华虹宏力半导体制造有限公司 | The measuring circuit of the data setup time of d type flip flop |
| CN106291324B (en) * | 2016-08-18 | 2018-10-02 | 北京航空航天大学 | A kind of on piece differential delay measuring system and recycling integrated circuit recognition methods |
| CN111208416B (en) * | 2020-01-15 | 2021-08-20 | 西安电子科技大学 | Integrated circuit process credibility detection method and circuit based on time-to-digital converter |
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Application publication date: 20100512 Assignee: Zhongke Jianxin (Beijing) Technology Co.,Ltd. Assignor: Institute of Computing Technology, Chinese Academy of Sciences Contract record no.: X2022990000752 Denomination of invention: A circuit and method for on-chip path delay measurement Granted publication date: 20120201 License type: Exclusive License Record date: 20221009 |