CN100575975C - Asynchronous chip simultaneous test method - Google Patents
Asynchronous chip simultaneous test method Download PDFInfo
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- CN100575975C CN100575975C CN200610117248A CN200610117248A CN100575975C CN 100575975 C CN100575975 C CN 100575975C CN 200610117248 A CN200610117248 A CN 200610117248A CN 200610117248 A CN200610117248 A CN 200610117248A CN 100575975 C CN100575975 C CN 100575975C
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Abstract
The invention discloses a kind of asynchronous chip simultaneous test method, at first, first output of chip under test asynchronous response signal is mated; Secondly, when matching first output of chip under test appearance, the clock signal that is about to this chip under test remains unchanged, and waiting for a period of time keeps synchronously a plurality of asynchronous chip under test; Afterwards, compare second of the asynchronous response signal more continuously, realize when a plurality of asynchronous chip under test are tested simultaneously coupling multidigit asynchronous response signal to the output of position, end.The present invention is based on external clock and control and realize asynchronous chip test simultaneous test method is shortened the test duration of chip, improve chip simultaneous test quantity and test frequency.
Description
Technical field
The invention belongs to integrated circuit (IC) testing method, be meant a kind of asynchronous chip simultaneous test method especially.
Background technology
In the semiconductor test industry, existing memory test instrument can only just can not carry out with surveying if will mate long numeric data to one digit number according to mating.
Logic tester is that a plurality of chips are all taken off in all data of certain time period, and then analyzes and handle at data.As shown in Figure 1, when realizing with survey to three asynchronous chips, at first, three chips are accepted instruction synchronously, because the response of asynchronous chip can not occur simultaneously, therefore, distribute a period of times such as back in instruction, allow all data in the time of occurrence section all to collect response, at last, it is whether qualified that the data of each chip of off-line analysis are judged, its shortcoming is that data processing time is long, and less relatively with quantitation.
Therefore, in this technical field, need a kind of asynchronous chip simultaneous test method, can shorten the test duration of chip, can also improve chip simultaneous test quantity and test frequency.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of asynchronous chip simultaneous test method, and it is controlled based on external clock and realizes asynchronous chip test simultaneous test method is shortened the test duration of chip, improves chip simultaneous test quantity and test frequency.
For solving the problems of the technologies described above, asynchronous chip simultaneous test method of the present invention at first, mates first output of chip under test asynchronous response signal; Secondly, when matching first output of chip under test appearance, the clock signal that is about to this chip under test remains unchanged, and waiting for a period of time keeps synchronously a plurality of asynchronous chip under test; Afterwards, compare second of the asynchronous response signal more continuously, realize when a plurality of asynchronous chip under test are tested simultaneously coupling multidigit asynchronous response signal to the output of position, end.
In described a period of time, have any chip do not occur first output promptly as defective.
Just can be implemented on the memory test instrument the test of asynchronous chip by the present invention, given full play to that the memory test instrument is many with quantitation, test frequency is than advantage such as higher, that test resource is many.The functional test of a lot of original card series products all must be tested on logic tester, now just can transfer to having improved chip simultaneous test quantity on the more storage tester of quantitation, obviously shorten the test duration of chip, test frequency also can improve, and has saved testing cost greatly.
Description of drawings
The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment.
Fig. 1 is that tester is realized the method to the asynchronous signal coupling;
Fig. 2 is the method that the present invention realizes the asynchronous signal coupling.
Embodiment
At first, first output to asynchronous signal is mated when the multicore sheet is tested simultaneously, as " 0 " of first clock output of first start bit of coupling earlier during 9000H of response in the IS7816 agreement, as shown in Figure 2, when chip 1 matches first bit data, just the state with test channel remains unchanged, and mainly is that clock signal is remained unchanged.
At this moment because the stopping of clock signal, chip under test 1 just can't be exported next data.When tester when all matching, continues first signal of all outputs such as chip 2, chip 3, chip 4 test vector is moved down in a certain period again.The chip that this time period is not matched is just as defective processing, and other chips that match have been kept synchronously this moment, as long as comparison is gone down and just can successively.
As need the product test of ISO7816 agreement communication, realized the synchro control of a plurality of asynchronous chips by control to clock signal, all tests of this series products all are placed on carry out 32 on the memory test instrument with surveying, saved the test duration greatly, carried out 16 in the logic testing with surveying and no longer need test procedure is placed on.
Claims (2)
1, a kind of asynchronous chip simultaneous test method is characterized in that: at first, first output of chip under test asynchronous response signal is mated; Secondly, when matching first output of chip under test appearance, the clock signal that is about to this chip under test remains unchanged, and waiting for a period of time keeps synchronously a plurality of asynchronous chip under test; Afterwards, compare second of the asynchronous response signal more continuously, realize when a plurality of asynchronous chip under test are tested simultaneously coupling multidigit asynchronous response signal to the output of position, end.
2, asynchronous chip simultaneous test method according to claim 1 is characterized in that: in described a period of time, have any chip do not occur first output promptly as defective.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200610117248A CN100575975C (en) | 2006-10-18 | 2006-10-18 | Asynchronous chip simultaneous test method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200610117248A CN100575975C (en) | 2006-10-18 | 2006-10-18 | Asynchronous chip simultaneous test method |
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| CN101165501A CN101165501A (en) | 2008-04-23 |
| CN100575975C true CN100575975C (en) | 2009-12-30 |
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Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106872874A (en) * | 2015-12-11 | 2017-06-20 | 华大半导体有限公司 | One kind concentrates CP method of testings for RFID label chip |
| CN110907803A (en) * | 2019-11-21 | 2020-03-24 | 北京中电华大电子设计有限责任公司 | Method for realizing 7816 interface communication synchronous test on ATE |
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| CN101165501A (en) | 2008-04-23 |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20140108 |
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Free format text: CORRECT: ADDRESS; FROM: 201206 PUDONG NEW AREA, SHANGHAI TO: 201203 PUDONG NEW AREA, SHANGHAI |
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Effective date of registration: 20140108 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Patentee before: Shanghai Huahong NEC Electronics Co., Ltd. |