CN104808134A

CN104808134A - Multi-channel chip test system

Info

Publication number: CN104808134A
Application number: CN201510183982.7A
Authority: CN
Inventors: 吴华; 刘建峰; 张小丹; 李承峰
Original assignee: NANTONG KINGTECH CO Ltd
Current assignee: NANTONG KINGTECH CO Ltd
Priority date: 2015-04-18
Filing date: 2015-04-18
Publication date: 2015-07-29

Abstract

The invention discloses a multi-channel chip test system, comprising a computer, an FPGA, a modulating and demodulating circuit and a probe, wherein the modulating and demodulating circuit is provided with 8-16 channels in parallel and generates signals with frequency of 13.56MHz, and the test chip is a RFID (Radio Frequency Identification) chip with frequency of 13.56MHz. The multi-channel chip test system achieves simultaneous parallel test of 8-16 channels and saves more time, and the test signals are very strong in anti-jamming capacity.

Description

Multi-channel chip test macro

Technical field

The present invention relates to performance test apparatus and the method for testing of microelectronic chip.

Background technology

High frequency chip multiple channel test technical discussion for a long time, mainly realize difficult point and be that logical signal via line is to probe, chip under test is applied to as test vector, test vector understands the interference between or signal asynchronous because of each channel signal in transmitting procedure, make a mistake when causing signal to arrive chip under test, chip can not be correctly decoded test vector, therefore can not produce effective test result data.

Existing technology is multi-channel serial test, is all single-chip computer control system substantially, adopts ping-pong operation, and a passage is when testing, and another passage is at setup test vector.One passage has been surveyed, two lane testings, triple channel setup test vector, by that analogy.This serial scheme, relative to single pass test, can shorten the test duration really.But because can not test by complete parallel, can holding time on the wait last lane testing time.

It is a kind of based on modular hyperchannel diode test system and method that number of patent application has been the disclosure of the invention of 2012103467083, native system comprises master system and lower computer system, wherein master system comprises industrial computer, data collecting card, digital I/O card and Phototube Coupling interface board, and lower computer system comprises four reusable test circuit modules and three function plates wherein.Native system carries out modular design according to test function, the parameter testing of forward voltage drop VF, disruptive voltage VB, reverse leakage current IR, forward voltage difference Δ VF, voltage difference delta VB1 and Δ VB2 can be carried out, hyperchannel, the high precision measurement of diode can be completed at test streamline.This invention can not be tested multiple chip synchronization, and efficiency is lower.

Number of patent application be 2003101135173 invention relate to a kind of multi-channel data method of testing, comprise following processing procedure: according to the performance parameter of tested digital device, computer parallel port or Serial Port Line are connected to correspondingly the controlled pin of the correlated digital device needing to carry out input control; The binary digital information sent computer parallel port under all possible for each passage digital state is needed to collect, the data file of formation control computer parallel port output information; The data file that input step 2 is formed, utilizes computer parallel port or serial ports, and the number that send that operation correlation computer send several software to carry out each state of digital device is arranged; And the response parameter numerical value to be measured of each state of each passage of line item.Method of testing of the present invention overcomes the infull defect of conventional sample testing data, and adopt all possible digital state of hyperchannel to utilize computer parallel port to complete setting, data record can walk abreast at any time simultaneously.This method of testing is tested while can only being applicable to less than 8 chips, not high enough on testing efficiency.

Summary of the invention

Goal of the invention: the invention provides the multi-channel chip test macro that a kind of 8-16 passage is tested simultaneously.

Technical scheme:

The invention discloses a kind of multi-channel chip test macro, for the performance (electrical performance data, physical dimension data or logical data) of test chip, there is the composition devices such as the computing machine (PC) by connecting successively, field programmable gate array, modulation-demodulation circuit, probe (or exploration card).Chip is placed in chip bonding pad, two of each probe probes respectively with two Electrode connection of a chip.

PC is communicated with FPGA by Serial Port Line, for transmitting test script, test command, passback test result; Field programmable gate array, is called for short FPGA, English full name Field-Programmable Gate Array, is responsible for the generation of test signal and the judgement of chip return signal, puts back to the result of test to computer disposal simultaneously.It is inner containing trigger, logic gate array etc., can realize multiple signal and synchronously produces output and return acceptance.

Modulation-demodulation circuit has 8-16 parallel passage (test circuit passage), each passage connects a probe or multiple expanding channels same probe (probe now has multiple serial connector) by a Serial Port Line, correspondingly has one or 8-16 probe.Chip is placed in chip bonding pad, and chip bonding pad rotates 8-16 chip position at every turn, each chip to be measured can be turned to the position of each detection below, can realize the synchronism output of 8-16 signal and return acceptance judgement.

FPGA passes through self-defining interface and each channel transmission data, comprising the signal with data sending to chip.

FPGA(field programmable gate array) according to the related command in test script, each passage independently can be operated, as in advance, synchronous or time delay, the test timing pattern that multiple chip is different can be realized.

Described Serial Port Line is preferably shielding line, and antijamming capability is improved.

The logical signal that FPGA produces, preferably through 100%ASK modulation-demodulation circuit, produces the signal of 13.56MHz frequency, to tat probe, and the RFID radio-frequency (RF) identification chip of test chip to be frequency be 13.56MHz.The signal stabilization of test is higher.

Beneficial effect:

Serial scheme of the present invention, relative to single pass test, can shorten the test duration really.This programme parallel channel achieves 8-16 passage concurrent testing simultaneously, relative to serial test, saves the more time.The selection of test frequency and the employing of shielding line, ensure that the stable and very strong antijamming capability of test signal.

Accompanying drawing explanation

Fig. 1 is a test system framework figure of the present invention;

In figure, 1-computing machine (PC); 2-Serial Port Line; 3-FPGA; 4-passage; 5-probe; 6-chip.

Embodiment

If Fig. 1 is test system framework figure.PC1 is communicated with FPGA3 by Serial Port Line 2, for transmitting test script, and test initiation command, and passback test result; FPGA3 is by self-defining interface and each passage 4 front end delivery data, comprising the 13.56MHz signal with data sending to chip 6, CHO-CH15 is the 100%ASK modulation circuit passage 4, CARD of 13.56MHz be probe 5, CHIP is the chip bonding pad (PAD) with multiple chip 6.This test macro can test synchronously and exactly the performance parameter of 16 chips.

Claims

1. a multi-channel chip test macro, for the performance of test chip, there is probe (5), two of probe (5) probes respectively with two Electrode connection of a chip (6), it is characterized in that: there is computing machine (1), FPGA(3 connected in series successively), these composition devices of modulation-demodulation circuit, probe (5);

Computing machine (1) is by the Serial Port Line (2) of shielding line and FPGA(3) communicate, for transmitting test script, test command, passback test result; FPGA(3) trigger is contained in inside, logic gate array, can be responsible for the generation of multiple test signal and the judgement of chip (6) return signal, put back to the result of test to computer disposal simultaneously.

2. multi-channel chip test macro as claimed in claim 1, is characterized in that: modulation-demodulation circuit has 8-16 parallel passage (4), and each passage (4) connects a probe (5) by a Serial Port Line, correspondingly has 8-16 probe (5).

3. multi-channel chip test macro as claimed in claim 1, is characterized in that: modulation-demodulation circuit has 8-16 parallel passage (4), multiple expanding channels same probe.

4. multi-channel chip test macro as claimed in claim 2 or claim 3, it is characterized in that: chip (6) is placed in chip bonding pad, chip bonding pad rotates 8-16 chip position at every turn, realizes the synchronism output of the detection of 8-16 chip (6) and test signal, returns acceptance judgement.

5. multi-channel chip test macro as claimed in claim 1, is characterized in that: described FPGA(3) according to the related command in test script, each passage (4) is independently shifted to an earlier date, the operation of synchronous or time delay.

6. the multi-channel chip test macro as described in claim 1 or 5, it is characterized in that: described FPGA(3) logical signal that produces, through 100%ASK modulation-demodulation circuit, produce the signal of 13.56MHz frequency to tat probe (5), the RFID radio-frequency (RF) identification chip of test chip (6) to be frequency be 13.56MHz.