CN112147482B - Parallel test system and test method thereof - Google Patents
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Abstract
The invention provides a high-precision high-test speed parallel test system for wafer-level parameter test and a test method thereof, in particular to a parallel test system, which comprises a main controller, a storage module, a public bus and at least one measurement module, wherein the main controller, the storage module and the measurement module are all connected to the public bus; the parallel test system is also provided with a dispatching module which is integrated in the main controller or is connected to the public bus by adopting an independent control device; the invention determines the execution scheme of the test plan by using the scheduling module, and the main controller controls the plurality of measuring modules to carry out parallel test according to the execution scheme, and the controller in each measuring module is interacted with the main controller independently, so that the test unit in each measuring module can carry out uninterrupted test, and the efficient and stable wafer test is realized.
Description
Technical Field
The present invention relates to the field of integrated circuit industry, and more particularly, to a parallel test system and a test method thereof.
Background
In the integrated circuit industry, integrated circuit testing is an important step throughout the entire process of integrated circuit production and application. Wafer testing is the first step in the subsequent packaging test of semiconductor devices, and aims to pick out bad chips in the wafer. For testing wafer-level integrated circuits, because the test interface of an external test instrument cannot directly realize the test of a test object (wafer or chip), the external test instrument is usually controlled by a computer, the test instrument is connected to the test object through a probe card as a bridge, a probe on the probe card contacts with a bonding pad in the test object to form a test signal path, and then the test signal path is matched with the test instrument to achieve the test purpose.
In conventional sequential parametric test methods, the testing of each Device Under Test (DUT) on a wafer must be performed one by one, and after one test is completed, the next test must be started. The total test time is approximately equal to the sum of the test time of all the devices to be tested and the task switching time between each test task and the next test task, so as the device size is reduced, the integration level of the devices is higher and higher, the fault randomness of the devices is increased, and the requirement on the wafer test speed cannot be met by the sequence parameter test.
Many manufacturers are beginning to explore the possibility of using parallel parametric testing to increase test speed. Parallel parametric testing is a test method that measures multiple test structures simultaneously on a wafer to increase wafer level parametric testing speed. Some manufacturers currently implement parallel parametric testing by controlling the operation of multiple SMUs with one clock signal, but this approach has drawbacks: 1) There may be a delay in the transfer of the clock signal to the plurality of SMUs; 2) Multiple SMUs must begin testing at the same time, even if a certain SMU completes testing earlier than other SMUs, it must wait until other SMUs complete testing before starting the next test; 3) The system only comprises one CPU, and compared with a system with multiple CPUs, the system has lower precision.
Disclosure of Invention
The invention mainly aims to overcome the defects in the prior art and provides a high-precision and high-test-speed parallel test system and a test method for wafer-level parameter test. In order to solve the technical problems, the invention adopts the following solutions:
the parallel test system comprises a main controller, a storage module, a public bus and at least one measurement module, wherein the main controller, the storage module and the measurement module are all connected to the public bus; the parallel test system is also provided with a dispatching module which is integrated in the main controller or is connected to the public bus by adopting an independent control device;
the main controller can create a test algorithm (Algo) and a test task, compile the test algorithm and the test task to generate a test plan (testplan) and perform test related parameter configuration; the main controller can generate a trigger signal and a control signal for controlling the measurement module to execute the test plan according to the execution scheme determined by the scheduling module, and send corresponding trigger signals or control signals to the measurement module;
the public buses comprise a data bus (data bus), a trigger signal bus (trigger bus) and a control signal bus (control bus), wherein the data bus is used for transmitting data information, the trigger signal bus is used for transmitting trigger signals, and the control signal bus is used for transmitting control signals;
the storage module is used for storing a test algorithm, a test task, a test plan and a test result returned by the measurement module;
the scheduling module is used for determining an execution scheme, namely a measurement module and a moment for executing each test plan;
the measurement module comprises a controller, a memory (RAM) and a test unit; the controller can extract a corresponding test plan in the storage module, control the test unit to execute the test plan according to the received trigger signal or control signal, and feed back the test result to the main controller; the memory is capable of storing test plans extracted from the memory module.
As a further improvement, the execution scheme determined by the scheduling module makes the time of executing all the test plans shortest, and the test rows at each moment are testable test rows; the test row: all test plans tested in parallel at a certain moment are designed into a test row; the measurable test row: there are no test rows sharing pads (pads) or test plans where parallel tests would interfere with each other's test results.
As a further refinement, the scheduling module determines the measurement module and the moment of execution of each test plan, in particular by: the scheduling module divides all the test meters into E trigger signal test groups and F control signal test groups, and then determines the measurement module and the time of specific execution of each test plan in the test groups; for the test plan in one trigger signal test group, the executed measurement modules share the trigger signals to execute the test plan, so that synchronous parallelism is realized; and the test plans are independently executed among different trigger signal test groups; for the test plans in the control signal test group, each executed measurement module executes the test plan according to the control signals received by each module, so that asynchronous parallelism is realized; wherein E is a natural number, F is 0 or 1, and E, F is not 0 at the same time.
As a further improvement, the scheduling module divides all the test meters into a plurality of test groups, and the specific method is as follows: if the same test algorithm is adopted and the number of test plans whose test time consumption differs within a time threshold exceeds a quantity threshold, the test plans are used as one trigger signal test group (for example, a preset time threshold is 1 second, and the quantity threshold is 50, if the number of test plans whose test time consumption differs within 1s is greater than 50, the test plans are used as one trigger signal test group), and the remaining test plans which cannot be divided into trigger signal test groups are used as control signal test groups, so that all test plans are divided into E trigger signal test groups and F control signal test groups.
As a further improvement, the measurable test row, the scheduling module is obtained by:
step A: there are M test plans to be executed, at most N test channels to execute the test, one test channel using at least one measuring module, then there are
Different test rows; wherein (1)>
Is a combined symbol, i test plans are taken from M test plans to form a subset, the order of the test plans in the subset is not considered, and the number of the subset is +.>
A representation;
and (B) step (B): taking each test row in turn, and judging whether a test plan of a shared Pad (Pad) exists in the test row: if so, deleting the test line; if not, reserving the test line; until the alignment is completed
Judging the number of test rows;
step C: and B, sequentially taking each test row for judgment on the test row reserved after the judgment in the step B, and judging whether a test plan which can mutually interfere a test result by parallel tests exists in the test row or not: if so, deleting the test line; if not, reserving the test line; and B, after the judgment of all the test rows reserved in the step B is completed, the finally reserved test rows are all testable test rows.
As a further improvement, the storage module is provided with a task unit, a storage unit, an allocation result unit and a test result unit; the task unit is used for storing a test algorithm and a test task; the storage unit is used for storing test plans, and each element in the storage unit has an own address, namely each test plan has an own address; the allocation result unit is used for storing the allocation result of each test plan, namely the address of the test plan to be executed by each measurement module in the storage unit; the test result unit is used for storing the test result fed back by the measurement module.
As a further improvement, the controller in the measurement module extracts the corresponding test plan in the storage module, specifically: the controller can obtain the address of the corresponding test plan from the allocation result unit of the storage module, and extract the corresponding test plan from the storage unit according to the address.
As a further improvement, the main controller is connected with an input/output device, and can input externally generated test tasks and test algorithms to the main controller through the input/output device, or directly input an externally compiled test plan to the main controller through the input/output device; the main controller can output the test result by using the input/output device.
As a further improvement, the parallel test system employs a General Purpose Interface Bus (GPIB) connection, i.e., the common bus is implemented using a GPIB bus, and each device connected to the common bus is provided with a GPIB interface.
The test method based on the parallel test system comprises the following steps:
step (1): the main controller receives the test plan or compiles the test plan and stores all the test plans into the storage module;
step (2): the scheduling module extracts test plans, divides all the test plans into E trigger signal test groups and F control signal test groups, and determines an execution scheme, namely, a measurement module and time for executing each test plan are determined, so that the time for executing all the test plans is shortest and the test row at each time is a testable test row; wherein E is a natural number, F is 0 or 1, and E, F is not 0 at the same time;
step (3): each measuring module extracts a corresponding test plan from the storage module; the main controller generates a trigger signal and a control signal for controlling the measurement module to execute the test plan according to the execution scheme determined by the scheduling module; the main controller sends corresponding trigger signals to the measurement modules executing the test plans in the trigger signal test group and sends corresponding control signals to the measurement modules executing the test plans in the control signal test group; the controller in the measurement module controls the test unit to execute the test plan according to the received trigger signal or control signal;
step (4): in each measuring module, after the test unit executes the test plan, the controller feeds back the test result to the main controller, and the main controller stores the fed-back test result into the storage module;
step (5): and after receiving the test results executed by all the test plans, the main controller ends the test task.
As a further improvement, the test unit in the measurement module is provided with a buffer, and in the step (4), after the test unit executes the test plan, the controller uniformly feeds all test results of the test unit back to the main controller.
Compared with the prior art, the invention has the beneficial effects that:
1. the invention determines the execution scheme of the test plan by using the scheduling module, and the main controller controls the plurality of measuring modules to carry out parallel test according to the execution scheme, and the controller in each measuring module is interacted with the main controller independently, so that the test unit in each measuring module can carry out uninterrupted test, and the efficient and stable wafer test is realized.
2. The invention reasonably divides all test plans into a plurality of trigger signal test groups and control signal test groups, determines the measurement module and time of specific execution of each test plan in the test groups, and divides wafer test tasks into two parts of synchronous parallel test controlled by the trigger signals and asynchronous parallel test controlled by the control signals; the trigger signal controls the test to adopt the test plans of the same Alog, and the test time of the single test plan is consistent, so that the method has the advantage of no delay; the control signal controls the test to adopt the test plans of different alogs, and the test time consumption of a single test plan is generally different; aiming at different test groups, the invention adopts different parallel modes, and reduces the execution time consumption of test tasks.
3. In the test task, some test plans have the condition of sharing the pad, so that parallel test cannot be performed, and some test plans influence test results if parallel test can mutually influence the test results, so that parallel test is avoided; the invention pre-determines all the measurable test lines when the test task is executed, ensures that the test lines at each moment of the execution scheme determined by the scheduling module are the measurable test lines, and avoids conflict.
Drawings
FIG. 1 is a schematic diagram of a system architecture of a parallel test system.
FIG. 2 is a schematic diagram of another system architecture of a parallel test system.
FIG. 3 is a schematic diagram of a measurement module in a parallel test system.
Fig. 4 is a schematic diagram showing control differences between the trigger signal test set and the control signal test set.
Fig. 5 is a functional schematic diagram of a memory module.
FIG. 6 is a flow chart of a test method based on a parallel test system.
FIG. 7 is a flow chart of a scheduling module determining a testable row.
FIG. 8 is a measurement I off The Algo schematic used.
FIG. 9 is a measurement I off The Algo used requires a schematic representation of the variables used.
FIG. 10 is a measurement I dsat The Algo schematic used.
FIG. 11 is a measurement I dsat The used Algo requires a schematic representation of the variables used.
FIG. 12 is a schematic view of a portion of a test plan.
Detailed Description
The invention is described in further detail below with reference to the attached drawings and detailed description:
the parallel test system shown in fig. 1 comprises a main controller, a scheduling module, a storage module, a public bus and at least one measurement module, wherein the main controller, the scheduling module, the storage module and the measurement module are all connected to the public bus, and the main controller is also connected with input and output equipment; in some embodiments, the scheduling module may be integrated directly into the host controller, see in particular fig. 2. The parallel test system is connected by a General Purpose Interface Bus (GPIB), namely, a common bus is realized by a GPIB bus, and each device connected to the common bus is provided with a GPIB interface.
The main controller has the following functions: 1) Creating a test algorithm (Algo), a test task. 2) Compiling and generating a test plan (testplan) by using Algo and a test task: the Algo contains multiple variables, the DUT pin variable and the SMU variable are two of the variables, each test item in the test task contains a specific attachment value of the DUT pin variable, the specific attachment value of each pin variable is substituted into the Algo to generate a test plan, and finally, the test plan is correspondingly generated according to the number of the test items in the test task. 3) Testing the relevant parameter configuration. 4) Controlling the execution of the test, including generating a trigger signal and a control signal for controlling the measurement module to execute the test plan according to the execution scheme determined by the scheduling module, and sending a corresponding trigger signal to the measurement module executing the test plan in the trigger signal test group and a corresponding control signal to the measurement module executing the test plan in the control signal test group.
In the parallel test system, the main controller is connected with the input/output equipment, and externally generated test tasks and test algorithms can be input to the main controller through the input/output equipment, and even externally compiled test plans can be input to the main controller directly through the input/output equipment.
The common bus includes a data bus (data bus) for transmitting data information, a trigger signal bus (trigger bus) for transmitting a trigger signal, and a control signal bus (control bus) for transmitting a control signal.
The memory module shown in fig. 5 is provided with a task unit, a memory unit, an allocation result unit, and a test result unit. The task unit is used for storing a test algorithm and a test task. The storage unit is used for storing the test plans, and each element in the storage unit has an own address, namely each test plan has an own address. The allocation result unit is used for storing the allocation result of each test plan, namely the address of the test plan to be executed by each measurement module in the storage unit. The test result unit is used for storing the test result fed back by the measurement module.
The scheduling module is used for determining an execution scheme, namely a measurement module and a time for executing each test plan, and the specific mode is as follows:
if the same Algo is adopted and the number of the test plans with the test time difference within the time threshold exceeds the quantity threshold, dividing the test plans into one trigger signal test group (for example, the preset time threshold is 1 second, the quantity threshold is 50, and if the number of the test plans with the test time difference within 1s is adopted and the same Algo is greater than 50, the test plans are used as one trigger signal test group), and the rest of the test plans which cannot be divided into the trigger signal test groups are used as control signal test groups, so that all the test plans are divided into E trigger signal test groups and F control signal test groups; wherein E is a natural number, F is 0 or 1, and E, F is not 0 at the same time.
The scheduling module determines an execution scheme of each test group, namely a measurement module and a time of specific execution of each test plan in the test group, so that the time for executing all the test plans is shortest. As shown in fig. 4, for the test plans in one trigger signal test group, the executed measurement modules share the trigger signals to execute the test plans, so as to realize synchronous parallelism; and the test plans are independently executed among different trigger signal test groups. For the test plans in the control signal test group, each executed measurement module executes the test plan according to the control signals received by each module, and asynchronous parallel is realized.
The execution scheme determined by the scheduling module also ensures that the test line at each moment is a measurable test line; all the test plans tested in parallel at a certain moment are designed into one test row, and the testable test row refers to a test row which does not have a test plan that the mutual shared bonding pads or the parallel tests can interfere with the test results. As shown in fig. 7, the scheduling module obtains all measurable test rows in advance through the following steps:
step A: there are M test plans to be executed, there are at most N test channels to execute the test (one test channel uses at least one measurement module), then there are
Different test rows; wherein (1)>
Is a combined symbol, i test plans are taken from M test plans to form a subset, the order of the test plans in the subset is not considered, and the number of the subset is +.>
A representation;
and (B) step (B): taking each test row in turn, and judging whether a test plan of a shared Pad (Pad) exists in the test row: if so, deleting the test line; if not, reserving the test line; until the alignment is completed
Judging the number of test rows;
step C: and B, sequentially taking each test row for judgment on the test row reserved after the judgment in the step B, and judging whether a test plan which can mutually interfere a test result by parallel tests exists in the test row or not: if so, deleting the test line; if not, reserving the test line; and B, after the judgment of all the test rows reserved in the step B is completed, the finally reserved test rows are all testable test rows.
As shown in fig. 3, the measurement module includes a controller, a memory (RAM), and a test unit, which may be implemented using a Source Measurement Unit (SMU). The controller has the following functions:
1) Extracting a test plan: the controller acquires the address of the corresponding test plan from the distribution result unit of the storage module, and extracts the corresponding test plan from the storage unit according to the address and stores the test plan into the memory.
2) Controlling the test unit to execute the test plan: the controller controls the test unit to execute the test plan according to the received trigger signal or control signal.
3) And (5) feeding back a test result: after the test unit executes the test plan, the controller feeds back the test result to the main controller.
As shown in fig. 6, the wafer test task is executed based on the parallel test system, and the test method specifically includes the following steps:
step (1): the main controller receives the test plans or compiles the test plans to generate the test plans, and stores all the test plans into a storage unit of the storage module, and each test plan obtains an address in the storage unit.
Step (2): the scheduling module extracts test plans, divides all the test plans into E trigger signal test groups and F control signal test groups, and determines an execution scheme, namely, a measurement module and time for executing each test plan are determined, so that the time for executing all the test plans is shortest and the test row at each time is a testable test row; wherein E is a natural number, F is 0 or 1, and E, F is not 0 at the same time.
Step (3): each measuring module obtains the address of the corresponding test plan from the distribution result unit of the storage module, and extracts the corresponding test plan from the storage unit according to the address. And the main controller generates a trigger signal and a control signal for controlling the measurement module to execute the test plan according to the execution scheme determined by the scheduling module. The main controller sends corresponding trigger signals to a measurement module executing a test plan in the trigger signal test group; for a trigger signal test group, the related measurement modules share at least one trigger signal and synchronously execute a test plan in parallel; and the test plans are independently executed among different trigger signal test groups. The main controller sends corresponding control signals to a measurement module executing a test plan in the control signal test group; the controller of the related measurement module controls the test unit to execute a test plan according to the respective received control signals; at this time, the relevant test units work independently at the same time, and the test plan in the control signal test group is executed asynchronously and parallelly.
Step (4): in each measuring module, after the test unit executes all the distributed test plans, the controller uniformly feeds back all the test results in the buffer of the test unit to the main controller, and the main controller stores the fed-back test results into the test result unit of the storage module.
Step (5): after receiving the test results executed by all the test plans, the main controller ends the test task; and extracting a test result in the test result unit of the storage module, and outputting the test result through input and output equipment.
The following examples will enable those skilled in the art to more fully understand the present invention and are not intended to limit the same in any way.
In 86 Dies/wafer, each Die/wafer includes 2003 transistors under test, each transistor to test I off and Idsat . The test algorithm comprises Algo1:I off And Algo2:I dsat . After compiling the test tasks, the main controller obtains 4006 test plans, wherein 2003 pieces adopt Algo1, and other 2003 pieces adopt Algo2. The parallel test system is provided with 18 measurement modules, which are used for executing the 4006 test plans, and test units in the measurement modules are realized by SMUs.
FIG. 8 and FIG. 10 are respectively measurement I off 、I dsat Algo used; fig. 9 and 11 are Alg respectivelyo1 and Algo2, wherein the values attached to smuVF and smuVM represent specific SMU used for measurement, the values attached to variable D, G, S, B represent pad names connected to specific transistor pins to be tested, and current-voltage signals flow into or out of the transistor pins through pad; fig. 12 is a small portion of testplan.
The scheduling module firstly divides all the test meters into 5 trigger signal test groups and 1 control signal test group:
150 test plans with Algo1, test time of about 20s and test time difference within 1s are adopted as a trigger signal test group;
500 test plans with Algo1, test time of about 15s and test time difference within 1s are adopted as a trigger signal test group;
wherein 553 adopts Algo1, a test plan with the test time of about 10s and the test time difference within 1s as a trigger signal test group;
550 test plans with Algo2, test time of about 20s and test time difference within 1s are adopted as a trigger signal test group;
wherein 553 adopts a test plan of Algo2 with test time of about 15s and test time difference within 1s as a trigger signal test group;
the remaining 800 test plans with Algo1 and 900 test plans with Algo2 were used as a control signal test set.
Then, the scheduling module determines an execution scheme, that is, determines a measurement module and a time of specific execution of each test plan, so that the time of executing all the test plans is shortest and the test row at each time is a testable test row.
Each trigger signal test group, and the executed measurement modules share the trigger signals to synchronously execute the test plan in parallel; and the tests are independently executed among different trigger signal test groups. And the controller of the related measurement module controls the test unit to execute a test plan according to the respective received control signals to realize asynchronous parallel test. At this time, each measuring module is connected toContinuously working until all test plans are completed, and obtaining the I of the transistor off and Idsat 。
By adopting the parallel test system of the embodiment, the test task can be completed only by 1.6 hours, and compared with the traditional serial test method, the test efficiency of the traditional test method is improved by more than 3.7 times.
Finally, it should be noted that the above list is only specific embodiments of the present invention. Obviously, the invention is not limited to the above embodiments, but many variations are possible. All modifications directly derived or suggested to one skilled in the art from the present disclosure should be considered as being within the scope of the present invention.
Claims (9)
1. The parallel test system comprises a main controller, a storage module, a public bus and at least one measurement module, wherein the main controller, the storage module and the measurement module are all connected to the public bus; the parallel test system is characterized in that the parallel test system is also provided with a dispatching module which is integrated in the main controller or is connected to the public bus by adopting an independent control device;
the main controller can create a test algorithm and a test task, compile and generate a test plan by using the test algorithm and the test task, and perform test related parameter configuration; the main controller can generate a trigger signal and a control signal for controlling the measurement module to execute the test plan according to the execution scheme determined by the scheduling module, and send corresponding trigger signals or control signals to the measurement module;
the public bus comprises a data bus, a trigger signal bus and a control signal bus, wherein the data bus is used for transmitting data information, the trigger signal bus is used for transmitting a trigger signal, and the control signal bus is used for transmitting a control signal;
the storage module is used for storing a test algorithm, a test task, a test plan and a test result returned by the measurement module;
the scheduling module is used for determining an execution scheme, namely a measurement module and a moment for executing each test plan;
the measuring module comprises a controller, a memory and a testing unit; the controller can extract a corresponding test plan in the storage module, control the test unit to execute the test plan according to the received trigger signal or control signal, and feed back the test result to the main controller; the memory is capable of storing the test plan extracted from the memory module;
the scheduling module determines a measurement module and a time to execute each test plan specifically by:
the scheduling module divides all the test meters into E trigger signal test groups and F control signal test groups, and then determines a measuring module and a time for each test plan in the test groups to be executed specifically; for the test plan in one trigger signal test group, the executed measurement modules share the trigger signal to execute the test plan, so that synchronous parallelism is realized; and executing the test plan independently among the different trigger signal test groups; for the test plans in the control signal test group, each executed measurement module executes the test plan according to the control signals received by each module to realize asynchronous parallel
Wherein E is a natural number, F is 0 or 1, and E, F is not 0 at the same time.
2. The parallel test system according to claim 1, wherein the execution scheme determined by the scheduling module minimizes the time to complete all test plans, and the test rows at each moment are testable test rows;
the test row: all test plans tested in parallel at a certain moment are designed into a test row;
the measurable test row: there are no test rows of the test plan that share pads or parallel tests would interfere with each other's test results.
3. A parallel test system according to claim 1, wherein the scheduling module divides all test meters into test groups by the following method:
if the same test algorithm is adopted and the number of test plans whose test time consumption differs within a time threshold exceeds a number threshold, the test plans are used as a trigger signal test group, and the remaining test plans which cannot be divided into the trigger signal test groups are used as control signal test groups, so that all the test plans are divided into E trigger signal test groups and F control signal test groups.
4. A parallel test system according to claim 2, wherein the measurable test row, the scheduling module is obtained by:
step A: there are M test plans to be executed, at most N test channels to execute the test, one test channel using at least one measuring module, then there are
Different test rows;
wherein ,
is a combined symbol, i test plans are taken from M test plans to form a subset, the order of the test plans in the subset is not considered, and the number of the subset is +.>
A representation;
and (B) step (B): taking each test row in turn, and judging whether a test plan of a shared pad exists in the test row: if present, then
Deleting the test line; if not, reserving the test line; until the alignment is completed
Judging the number of test rows;
step C: and B, sequentially taking each test row for judgment on the test row reserved after the judgment in the step B, and judging whether a test plan which can mutually interfere the test result of the parallel test exists in the test row or not: if so, deleting the test line; if not, reserving the test line;
and B, after the judgment of all the test rows reserved in the step B is completed, the finally reserved test rows are all testable test rows.
5. The parallel test system according to claim 1, wherein the memory module is provided with a task unit, a memory unit, an allocation result unit and a test result unit; the task unit is used for storing a test algorithm and a test task;
the storage unit is used for storing test plans, and each element in the storage unit has an own address, namely each test plan has an own address;
the allocation result unit is used for storing the allocation result of each test plan, namely the address of the test plan to be executed by each measurement module in the storage unit; the test result unit is used for storing the test result fed back by the measurement module.
6. The parallel test system according to claim 5, wherein the controller in the measurement module extracts the corresponding test plan in the storage module, specifically:
the controller can obtain the address of the corresponding test plan from the allocation result unit of the storage module, and extract the corresponding test plan from the storage unit according to the address.
7. The parallel test system according to claim 1, wherein the main controller is connected with an input/output device, and is capable of inputting externally generated test tasks and test algorithms to the main controller through the input/output device, or directly inputting externally compiled test plans to the main controller through the input/output device; the main controller can output the test result by using the input/output device.
8. A parallel test system according to claim 1, characterized in that the parallel test system employs a universal interface bus connection.
9. The testing method based on the parallel testing system according to claim 1, comprising the following steps:
step (1): the main controller receives the test plan or compiles the test plan and stores all the test plans into the storage module;
step (2): the scheduling module extracts test plans, divides all the test plans into E trigger signal test groups and F control signal test groups, and determines an execution scheme, namely, a measurement module and time for executing each test plan are determined, so that the time for executing all the test plans is shortest and the test row at each time is a testable test row; wherein E is a natural number, F is 0 or 1, and E, F is not 0 at the same time;
step (3): each measuring module extracts a corresponding test plan from the storage module;
the main controller generates a trigger signal and a control signal for controlling the measurement module to execute the test plan according to the execution scheme determined by the scheduling module; the main controller sends corresponding trigger signals to the measurement modules executing the test plans in the trigger signal test group and sends corresponding control signals to the measurement modules executing the test plans in the control signal test group;
the controller in the measurement module controls the test unit to execute the test plan according to the received trigger signal or control signal;
step (4): in each measuring module, after the test unit executes the test plan, the controller feeds back the test result to the main controller, and the main controller stores the fed-back test result into the storage module;
step (5): and after receiving the test results executed by all the test plans, the main controller ends the test task.
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