CN115201529A - Novel parallel semiconductor parameter testing system - Google Patents
Novel parallel semiconductor parameter testing system Download PDFInfo
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- CN115201529A CN115201529A CN202210909347.2A CN202210909347A CN115201529A CN 115201529 A CN115201529 A CN 115201529A CN 202210909347 A CN202210909347 A CN 202210909347A CN 115201529 A CN115201529 A CN 115201529A
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- 238000012360 testing method Methods 0.000 title claims abstract description 231
- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 239000011159 matrix material Substances 0.000 claims abstract description 55
- 238000005259 measurement Methods 0.000 claims abstract description 53
- 239000000523 sample Substances 0.000 claims abstract description 39
- 238000003860 storage Methods 0.000 claims abstract description 31
- 238000009826 distribution Methods 0.000 claims description 8
- 238000012545 processing Methods 0.000 claims description 8
- 238000000034 method Methods 0.000 claims description 7
- 238000012937 correction Methods 0.000 claims description 4
- 230000001360 synchronised effect Effects 0.000 claims description 4
- 238000013461 design Methods 0.000 claims 4
- 230000004044 response Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/04—Housings; Supporting members; Arrangements of terminals
- G01R1/0408—Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
- G01R1/0416—Connectors, terminals
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2601—Apparatus or methods therefor
Abstract
The invention discloses a new parallel semiconductor parameter testing system, comprising: a scheduling module; a storage module; the device comprises a test module, a controller, a memory and a measurement unit, wherein the measurement unit comprises a Source Measurement Unit (SMU), a digital multimeter, a capacitance measurement unit and a pulse generator unit (the measurement unit comprises but is not limited to the test unit). The invention enables each source measuring unit to be directly connected with each probe card pin under the condition of using a small-scale switch matrix, and simultaneously enables the digital multimeter, the capacitance measuring unit and the pulse generator unit to be connected with each probe card pin through the switch matrix. The parallel test of current and voltage is realized, the test speed can be greatly improved, the test units required by the test system are greatly reduced, and the cost of the test system is obviously reduced.
Description
Technical Field
The invention relates to the technical field of semiconductor and integrated circuit testing, in particular to a novel parallel semiconductor parameter testing system.
Background
With the development of semiconductor manufacturing technology, the integration level of semiconductor devices is continuously increasing. In the field of wafer level semiconductor parameter testing, the number of components required to be tested for each wafer is increased continuously, so that the requirement of the wafer level semiconductor parameter testing on the testing speed of a testing system is increased continuously, and the testing speed can be increased greatly by adopting a parallel semiconductor testing system.
One existing solution is to have all test resources connected to each pin of the probe card (probe card) through a very large scale switch matrix to achieve parallel testing. The disadvantage of this solution is the need for an ultra-large scale switch matrix. Meanwhile, the SMU (source measurement unit) is connected to the device under test through the switch matrix, and parasitic resistance is introduced into the test loop, which affects the test accuracy and test speed, as shown in fig. 4;
another solution is that different test resources are directly connected to each pin of the probe card through multiple check switches, which requires a large number of test units, resulting in a significant increase in the cost of the test system, as shown in fig. 5.
The wafer-level parallel semiconductor parameter testing system adopted by the scheme enables each SMU to be directly connected with each probe card pin, and simultaneously enables a DVM (digital multimeter), a CMU (capacitance measuring unit) and a PGU (pulse generator unit) to be connected with the probe card pins through a switch matrix, thereby avoiding the defects that the two schemes use a super-large scale switch matrix or need a large number of testing units.
Disclosure of Invention
The present invention is directed to a novel parallel semiconductor parametric test system, in which each SMU is directly connected to each probe card pin while the DVM, CMU and PGU are connected to each probe card pin through a switch matrix, in the case of using a small-scale switch matrix, so as to solve the problems of the background art.
In order to achieve the purpose, the invention provides the following technical scheme:
a new parallel semiconductor parametric test system comprising:
the test module comprises a Source Measurement Unit (SMU), a digital multimeter, a capacitance measurement unit and a pulse generator unit (the test module comprises but is not limited to the test units), wherein the Source Measurement Unit (SMU) is directly connected with each probe card pin in a one-to-one correspondence manner; and connecting the digital multimeter, the capacitance measuring unit and the pulse generator unit with any probe card pin through the switch matrix module.
The switch matrix module comprises two schemes, namely: the small-scale switch matrix consists of high-frequency matrix superposed leakage isolating switches; in the second scheme, a small-scale switch matrix consists of a low-leakage switch matrix;
the testing bus module consists of a plurality of groups of cables, each group of testing cables directly connects the Source Measuring Unit (SMU) with each probe card pin in a one-to-one correspondence manner, and each group of testing cables also directly connects the output port of the switch matrix with each probe card pin in a one-to-one correspondence manner, so that the digital multimeter, the capacitance measuring unit and the pulse generator unit can be connected with any probe card pin through the switch matrix module;
the capacitance correction processing module removes system errors of the semiconductor parameter test through a system level capacitance compensation algorithm;
the judging and processing module judges whether the tested semiconductor wafer is qualified or not according to the measurement data of the testing module;
the scheduling module is integrated in the main controller or connected to a common bus by adopting an independent control device;
the device comprises a storage module, a task unit, a storage unit, an allocation result unit and a test result unit, wherein the storage module is provided with the task unit, the storage unit, the allocation result unit and the test result unit;
the task unit is used for storing a test algorithm and a test task;
the storage unit is used for storing test plans, and each element in the storage unit has an address of the element, namely each test plan has an address of the element;
the distribution result unit is used for storing the distribution result of each test plan, namely the address of the test plan to be executed by each measurement module in the storage unit;
and the test result unit is used for storing the test result fed back by the measurement module.
Preferably, the test module includes:
a controller, a memory and a test unit; the controller can extract the corresponding test plan in the storage module, control the test unit to execute the test plan according to the received trigger signal or control signal, and feed back the test result to the main controller; the memory can store the test plan retrieved from the storage module.
Preferably, the parallel semiconductor parametric test system further includes:
the main control module can create a test algorithm and a test task, can compile and generate a test plan by using the test algorithm and the test task, and performs test related parameter configuration; the main controller can generate a trigger signal and a control signal for controlling the measurement module to execute the test plan according to the execution scheme determined by the scheduling module, and sends the corresponding trigger signal or control signal to the measurement module;
the scheduling module is integrated in a host computer or connected to a common bus by adopting an independent control device and is used for determining an execution scheme, namely a measuring module and time for executing each test plan, and the scheduling module specifically determines the measuring module and the time for executing each test plan by the following method: the scheduling module divides all test plans into E trigger signal test groups and F control signal test groups, and then determines the specific execution measurement module and time of each test plan in the test groups; for a test plan in a trigger signal test group, an executed measurement module shares a trigger signal execution test plan to realize synchronous parallelism; and the test plan is independently executed among different trigger signal test groups; for the test plans in the control signal test group, each executed measurement module executes the test plans according to the received control signals, so as to realize asynchronous parallel;
in summary, due to the adoption of the technology, the invention has the beneficial effects that:
in the invention, under the condition of using a small-scale switch matrix, each source measuring unit is directly connected with each probe card pin through a test bus, and simultaneously, the digital multimeter, the capacitance measuring unit and the pulse generator unit are connected with each probe card pin through the test bus and then the switch matrix. The parallel test of current and voltage is realized, the test speed can be greatly improved, the test units required by the test system are greatly reduced, and the cost of the test system is obviously reduced.
Drawings
FIG. 1 is a schematic diagram showing the connection of test modules in an embodiment of the novel parallel semiconductor parametric test system of the present invention;
FIG. 2 is a 6 x 24 switch matrix schematic diagram required by the parametric test system in the new parallel semiconductor parametric test system embodiment of the present invention;
fig. 3 is a 6 x 24 switch matrix schematic diagram required by the parametric test system in the embodiment of the novel parallel semiconductor parametric test system of the present invention.
FIG. 4 is a circuit diagram of a parallel semiconductor parametric test system according to the background of the invention.
FIG. 5 is a circuit diagram of a parallel semiconductor parametric test system according to the background of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings of the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
The present invention provides a new parallel semiconductor parametric test system as shown in fig. 1-3, comprising:
the test module comprises a Source Measurement Unit (SMU), a digital multimeter, a capacitance measurement unit and a pulse generator unit (the test module comprises but is not limited to the test units), wherein the Source Measurement Unit (SMU) is directly connected with each probe card pin in a one-to-one correspondence manner; and connecting the digital multimeter, the capacitance measuring unit and the pulse generator unit with any probe card pin through the switch matrix module.
The switch matrix module comprises two schemes, namely: the small-scale switch matrix consists of high-frequency matrix superposed leakage isolating switches; in the second scheme, a small-scale switch matrix consists of a low-leakage switch matrix;
the testing bus module consists of a plurality of groups of cables, each group of testing cables directly connects the Source Measuring Unit (SMU) with each probe card pin in a one-to-one correspondence manner, and each group of testing cables also directly connects the output port of the switch matrix with each probe card pin in a one-to-one correspondence manner, so that the digital multimeter, the capacitance measuring unit and the pulse generator unit can be connected with any probe card pin through the switch matrix module;
the capacitance correction processing module removes system errors of the semiconductor parameter test through a system level capacitance compensation algorithm;
the judging and processing module judges whether the tested semiconductor wafer is qualified or not according to the measurement data of the testing module;
the scheduling module is integrated in the main controller or is connected to the common bus by adopting an independent control device;
the storage module is provided with a task unit, a storage unit, an allocation result unit and a test result unit;
the task unit is used for storing a test algorithm and a test task;
the storage unit is used for storing test plans, and each element in the storage unit has an address of the element, namely each test plan has an address of the element;
the distribution result unit is used for storing the distribution result of each test plan, namely the address of the test plan to be executed by each measurement module in the storage unit;
and the test result unit is used for storing the test result fed back by the measuring module.
The test module comprises a Source Measurement Unit (SMU), a digital multimeter, a capacitance measurement unit and a pulse generator unit (the test module comprises but is not limited to the test units), wherein the Source Measurement Unit (SMU) is directly connected with each probe card pin in a one-to-one correspondence manner; and connecting the digital multimeter, the capacitance measuring unit and the pulse generator unit with any probe card pin through the switch matrix module.
The switch matrix module comprises two schemes, namely: the small-scale switch matrix consists of high-frequency matrix superposed leakage isolating switches; in the second scheme, a small-scale switch matrix consists of a low-leakage switch matrix;
the testing bus module consists of a plurality of groups of cables, each group of testing cables directly connects the Source Measuring Unit (SMU) with each probe card pin in a one-to-one correspondence manner, and each group of testing cables also directly connects the output port of the switch matrix with each probe card pin in a one-to-one correspondence manner, so that the digital multimeter, the capacitance measuring unit and the pulse generator unit can be connected with any probe card pin through the switch matrix module;
the capacitance correction processing module removes system errors of the semiconductor parameter test through a system level capacitance compensation algorithm;
the judging and processing module judges whether the tested semiconductor wafer is qualified or not according to the measurement data of the testing module;
the scheduling module is integrated in the main controller or is connected to the common bus by adopting an independent control device;
the device comprises a storage module, a task unit, a storage unit, an allocation result unit and a test result unit, wherein the storage module is provided with the task unit, the storage unit, the allocation result unit and the test result unit;
the task unit is used for storing a test algorithm and a test task;
the storage unit is used for storing test plans, and each element in the storage unit has an own address, namely each test plan has an own address;
the distribution result unit is used for storing the distribution result of each test plan, namely the address of the test plan to be executed by each measurement module in the storage unit;
and the test result unit is used for storing the test result fed back by the measuring module.
The main control module can create a test algorithm and a test task, can compile and generate a test plan by using the test algorithm and the test task, and performs test related parameter configuration; the main controller can generate a trigger signal and a control signal for controlling the measurement module to execute the test plan according to the execution scheme determined by the scheduling module, and sends the corresponding trigger signal or control signal to the measurement module;
the scheduling module is integrated in the host computer or connected to the common bus by an independent control device, and is used for determining an execution scheme, namely a measurement module and time for executing each test plan, and the scheduling module is used for determining the measurement module and time for executing each test plan by the following method: the scheduling module divides all the test plans into E trigger signal test groups and F control signal test groups, and then determines the measurement module and the time of each test plan in the test groups; for a test plan in a trigger signal test group, an executed measurement module shares a trigger signal execution test plan to realize synchronous parallelism; and the test plans are independently executed among different trigger signal test groups; for the test plans in the control signal test group, each executed measurement module executes the test plans according to the received control signals, so that asynchronous parallelism is realized;
the scheduling module determines a measurement module and a time for executing each test plan in the following manner: the scheduling module divides all test plans into E trigger signal test groups and F control signal test groups, and then determines the specific execution measurement module and time of each test plan in the test groups; for a test plan in a trigger signal test group, an executed measurement module shares a trigger signal to execute the test plan, so that synchronous parallelism is realized; and the test plans are independently executed among different trigger signal test groups; for the test plans in the control signal test group, each executed measurement module executes the test plan according to the respective received control signal, thereby realizing asynchronous parallel test
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art should be considered to be within the technical scope of the present invention, and the technical solutions and the inventive concepts thereof according to the present invention should be equivalent or changed within the scope of the present invention.
It should be noted that, in this document, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
Claims (4)
1. A novel parallel semiconductor parametric test system, comprising:
the test module comprises a Source Measurement Unit (SMU), a digital multimeter, a capacitance measurement unit and a pulse generator unit (the test module comprises but is not limited to the test units), wherein the Source Measurement Unit (SMU) is directly connected with each probe card pin in a one-to-one correspondence manner; and connecting the digital multimeter, the capacitance measuring unit and the pulse generator unit with any probe card pin through the switch matrix module.
The switch matrix module comprises two schemes, namely: the small-scale switch matrix consists of high-frequency matrix superposed leakage isolating switches; in the second scheme, a small-scale switch matrix consists of a low-leakage switch matrix;
the testing bus module consists of a plurality of groups of cables, each group of testing cables directly connects the Source Measuring Unit (SMU) with each probe card pin in a one-to-one correspondence manner, and each group of testing cables also directly connects the output port of the switch matrix with each probe card pin in a one-to-one correspondence manner, so that the digital multimeter, the capacitance measuring unit and the pulse generator unit can be connected with any probe card pin through the switch matrix module;
the capacitance correction processing module is used for removing the system error of the semiconductor parameter test through a system level capacitance compensation algorithm;
the judging and processing module judges whether the tested semiconductor wafer is qualified or not according to the measurement data of the testing module;
the scheduling module is integrated in the main controller or connected to a common bus by adopting an independent control device;
the device comprises a storage module, a task unit, a storage unit, an allocation result unit and a test result unit, wherein the storage module is provided with the task unit, the storage unit, the allocation result unit and the test result unit;
the task unit is used for storing a test algorithm and a test task;
the storage unit is used for storing test plans, and each element in the storage unit has an own address, namely each test plan has an own address;
the distribution result unit is used for storing the distribution result of each test plan, namely the address of the test plan to be executed by each measurement module in the storage unit;
and the test result unit is used for storing the test result fed back by the measurement module.
2. A new parallel semiconductor parametric test system according to claim 1, characterized in that:
the unique design of the test bus module ensures that the SMU can be directly connected with each probe card pin in a one-to-one correspondence manner through the test bus; meanwhile, the digital multimeter, the capacitance measuring unit and the pulse generator unit can be connected with any probe card pin through the switch matrix module.
The test bus module consists of a plurality of groups of cables with two joints, one side of each group of cables is provided with two joints, one joint is connected with a Source Measurement Unit (SMU), and the other joint is connected with an output port of the switch matrix module; the other side is connected with the spring pins and is connected to the pins of the probe card through the spring pins. The testing cable connects the Source Measuring Unit (SMU) with each probe card pin one-to-one directly, and simultaneously connects the output port of the switch matrix with each probe card pin one-to-one directly, so that the digital multimeter, the capacitance measuring unit and the pulse generator unit can be connected with any probe card pin through the switch matrix module.
Unique switch matrix design:
the unique switch matrix design ensures that different measuring units in the testing module can share the same testing bus module, and meanwhile, the tests among different measuring units cannot influence each other.
The first scheme comprises the following steps: the switch matrix is formed by superposing high-frequency matrixes and leakage isolating switches; in the second scheme, a small-scale switch matrix consists of a low-leakage switch matrix;
unique electrical signal channel design:
the direct current voltage signal output or measured by the Source Measurement Unit (SMU) is directly connected to the corresponding probe card pins through the test bus module. The digital multimeter, the capacitance measuring unit and the pulse generator unit can be connected with any probe card pin through the switch matrix module and the test bus module.
3. A new parallel semiconductor parametric test system according to claim 1, characterized in that: the test module includes:
a controller, a memory and a test unit; the controller can extract the corresponding test plan in the storage module, control the test unit to execute the test plan according to the received trigger signal or control signal, and feed back the test result to the main controller; the memory can store the test plan retrieved from the storage module.
4. The new parallel semiconductor parametric test system of claim 1, wherein: the parallel semiconductor parameter testing system further comprises:
the main control module can create a test algorithm and a test task, can compile and generate a test plan by using the test algorithm and the test task, and performs test related parameter configuration; the main controller can generate a trigger signal and a control signal for controlling the measurement module to execute the test plan according to the execution scheme determined by the scheduling module, and sends the corresponding trigger signal or control signal to the measurement module;
the scheduling module is integrated in the host computer or connected to the common bus by using an independent control device, and is used for determining an execution scheme, namely a measurement module and a time for executing each test plan, and the scheduling module is used for determining the measurement module and the time for executing each test plan by the following method: the scheduling module divides all the test plans into E trigger signal test groups and F control signal test groups, and then determines the measurement module and the time of each test plan in the test groups; for a test plan in a trigger signal test group, an executed measurement module shares a trigger signal execution test plan to realize synchronous parallelism; and the test plan is independently executed among different trigger signal test groups; for the test plans in the control signal test group, each executed measurement module executes the test plans according to the received control signals, so that asynchronous parallelism is realized;
a plurality of pin cells, each cell having means for generating a test pattern of a test pin of the semiconductor test system assigned to a pin of a semiconductor device to be measured and evaluating the resulting response of the semiconductor device to be measured.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115629299A (en) * | 2022-12-19 | 2023-01-20 | 柯泰光芯(常州)测试技术有限公司 | Semiconductor chip testing method for realizing isolation Kelvin test |
| CN116794470A (en) * | 2022-12-06 | 2023-09-22 | 海宁理万集成电路有限公司 | New semiconductor parameter test hardware architecture system |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101196554A (en) * | 2006-12-04 | 2008-06-11 | 上海华虹Nec电子有限公司 | Wafer multi-test object parallel test system |
| KR20100024678A (en) * | 2008-08-26 | 2010-03-08 | 주식회사 루셈 | Probe card for testing semiconductor devices, tester and chip inspection method using the same |
| CN101680914A (en) * | 2007-04-03 | 2010-03-24 | 斯卡尼梅特里科斯有限公司 | Use the test of the electronic circuit of active probe integrated circuit |
| CN202256409U (en) * | 2011-08-17 | 2012-05-30 | 东莞利扬微电子有限公司 | Probe card and multi-chip test system using the same |
| CN208432669U (en) * | 2018-06-25 | 2019-01-25 | 青岛天盈华智科技有限公司 | A kind of test macro |
| CN112147482A (en) * | 2019-06-26 | 2020-12-29 | 杭州广立微电子有限公司 | Parallel test system and test method thereof |
-
2022
- 2022-07-29 CN CN202210909347.2A patent/CN115201529A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101196554A (en) * | 2006-12-04 | 2008-06-11 | 上海华虹Nec电子有限公司 | Wafer multi-test object parallel test system |
| CN101680914A (en) * | 2007-04-03 | 2010-03-24 | 斯卡尼梅特里科斯有限公司 | Use the test of the electronic circuit of active probe integrated circuit |
| KR20100024678A (en) * | 2008-08-26 | 2010-03-08 | 주식회사 루셈 | Probe card for testing semiconductor devices, tester and chip inspection method using the same |
| CN202256409U (en) * | 2011-08-17 | 2012-05-30 | 东莞利扬微电子有限公司 | Probe card and multi-chip test system using the same |
| CN208432669U (en) * | 2018-06-25 | 2019-01-25 | 青岛天盈华智科技有限公司 | A kind of test macro |
| CN112147482A (en) * | 2019-06-26 | 2020-12-29 | 杭州广立微电子有限公司 | Parallel test system and test method thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116794470A (en) * | 2022-12-06 | 2023-09-22 | 海宁理万集成电路有限公司 | New semiconductor parameter test hardware architecture system |
| CN115629299A (en) * | 2022-12-19 | 2023-01-20 | 柯泰光芯(常州)测试技术有限公司 | Semiconductor chip testing method for realizing isolation Kelvin test |
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