CN101196554A - Wafer multi-test object parallel test system - Google Patents
Wafer multi-test object parallel test system Download PDFInfo
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- CN101196554A CN101196554A CN 200610119039 CN200610119039A CN101196554A CN 101196554 A CN101196554 A CN 101196554A CN 200610119039 CN200610119039 CN 200610119039 CN 200610119039 A CN200610119039 A CN 200610119039A CN 101196554 A CN101196554 A CN 101196554A
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Abstract
The invention discloses a parallel test system of the wafer multiple test objects, which comprises a probe group of the multiple test objects that the parallel test requires, and the additional probes corresponding to the close chip of the test objects. The additional probes correspond to the ground terminal or other terminals of the close chip of the test objects, and contact with them when under test. The invention effectively solves the problem of crosstalk due to the leakage of charge pattern of the ground potential in the process of parallel test.
Description
Technical field
The present invention relates to a kind of test macro of SIC (semiconductor integrated circuit), particularly relate to a kind of wafer multi-test object parallel test macro.
Background technology
In the test of SIC (semiconductor integrated circuit), for improving testing efficiency, in wafer ATE test, adopt the method for many tested objects concurrent testing usually, promptly on probe, dispose the pairing probe of a plurality of tested objects, in test, realize the concurrent testing of many tested objects of ATE (ATE (automatic test equipment)) by the control of test procedure.
In the middle of test process, many tested objects concurrent testing brings earthy fluctuating disturbance of wafer easily, for the wafer device of some signal sensitivities, and test result instability or distortion when such disturbance will cause concurrent testing.
In the prior art, reduce the problem that many tested objects concurrent testing is crosstalked from improving probe to the signal shielding on this path of ATE test channel usually, but this and the unresolved signal interference problem that occurs on the wafer.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of wafer multi-test object parallel test macro, when using ATE that wafer is carried out many tested objects concurrent testing, overcomes the tested object signal phase mutual interference on wafer.
For solving the problems of the technologies described above, wafer multi-test object parallel test macro of the present invention comprises the probe groups of a plurality of tested objects that concurrent testing is required, tested object closes on the additional probe of chip correspondence, described additional probe is corresponding with earth terminal (GND) or other terminals of the chip that the concurrent testing object closes on, and is in contact with it when test.
Adopt test macro of the present invention, the test probe group of a plurality of tested objects that on probe, need except the configuration concurrent testing, the probe of the chip correspondence that the additional configurations tested object closes on.Be set to ground level in when test by the current potential that the test procedure programming adds probe, simultaneously the concurrent testing object applied test signal and implement concurrent testing, the earth potential of concurrent testing object is disturbed reduce and obtain good stable testing.
Description of drawings
The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment:
Accompanying drawing is the application synoptic diagram of wafer multi-test object parallel test macro of the present invention.
Embodiment
The present invention connects by the ground connection that strengthens tested object near zone on the wafer, thereby earth potential rises and falls and the stable testing problem of the concurrent testing object that causes when reducing concurrent testing.
As shown in the figure, the probe groups of a plurality of tested objects that need except the configuration concurrent testing on the probe, the additional configurations tested object closes on the additional probe of chip correspondence, and additional probe configuration number is determined by the complexity of being disturbed.
The additional pairing chip pin terminal types of probe at first, is considered the GND terminal (hold) of chip, does not have enough GND ends as fruit chip, also can be corresponding with common signal end.On probe, additional probe can be directly connected to the earth terminal of tester, also can be connected to the test channel of tester.If be connected to test channel, it is set to ground level then need to control ATE by test procedure in test.
During test, the probe of corresponding tested object and additional probe contact with the pad of wafer simultaneously.In test process, no matter be which kind of above-mentioned mode, all need the current potential of additional probe to be set to ground level, and with this understanding tested object is applied test signal enforcement concurrent testing.Because additional probe makes near the wafer area the tested object all be set to level doughtily.Therefore, the earth potential fluctuating of concurrent testing object is obviously reduced, thereby obtain good stable testing.
In actual applications, certain radio frequency products is carried out parallel test system exploitation, found that when concurrent testing object number more than or equal to 2 the time, the stable testing variation can't be finished the steady testing of wafer, can only carry out single tested object and test.Adopt technical scheme of the present invention, the concurrent testing number of objects brings up to 4 with surveying, and additional 4 groups are used to stablize earthy probe groups simultaneously, have realized stable concurrent testing, and testing efficiency rises to 4 times that do not adopt when of the present invention.
The present invention can solve the cross-interference issue that rises and falls and cause owing to earth potential in the concurrent testing process effectively, obtains good stable testing, improves the concurrent testing number of objects greatly, thereby improves testing efficiency, reduces testing cost.
Claims (3)
1. wafer multi-test object parallel test macro, the probe groups that comprises a plurality of tested objects that concurrent testing is required, it is characterized in that: comprise that also tested object closes on the additional probe of chip correspondence, described additional probe is corresponding with earth terminal or other terminals of the chip that the concurrent testing object closes on, and is in contact with it when test.
2. wafer multi-test object parallel test macro as claimed in claim 1, it is characterized in that: described additional probe is received the earth terminal of tester in succession, or be connected to the test channel of tester, if be connected to test channel, it is set to ground level then need to control ATE (automatic test equipment) by test procedure in test.
3. wafer multi-test object parallel test macro as claimed in claim 1 or 2 is characterized in that: when test, the current potential of all additional probes is set to ground level, and with this understanding tested object is tested.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200610119039 CN101196554B (en) | 2006-12-04 | 2006-12-04 | Wafer multi-test object parallel test system |
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| Application Number | Priority Date | Filing Date | Title |
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| CN 200610119039 CN101196554B (en) | 2006-12-04 | 2006-12-04 | Wafer multi-test object parallel test system |
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| CN101196554A true CN101196554A (en) | 2008-06-11 |
| CN101196554B CN101196554B (en) | 2010-05-12 |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101510520B (en) * | 2009-03-18 | 2011-05-11 | 上海华岭集成电路技术有限责任公司 | Test method for asynchronously repairing and adjusting silicon wafer with anti-interference |
| CN103267940A (en) * | 2013-05-06 | 2013-08-28 | 上海华岭集成电路技术股份有限公司 | Multi-module parallel test system and multi-module parallel test method |
| CN106409707A (en) * | 2015-07-28 | 2017-02-15 | 中芯国际集成电路制造(上海)有限公司 | Non-contact RF chip wafer testing method and apparatus |
| CN106841980A (en) * | 2017-01-10 | 2017-06-13 | 芯原微电子(上海)有限公司 | A kind of Bluetooth integrated circuit test system and method for testing |
| CN108828382A (en) * | 2018-07-26 | 2018-11-16 | 上海华虹宏力半导体制造有限公司 | Multi-chip integration test method |
| CN114152858A (en) * | 2022-02-08 | 2022-03-08 | 广州粤芯半导体技术有限公司 | Electrical test device and test method for cutting channel device |
| CN115201529A (en) * | 2022-07-29 | 2022-10-18 | 海宁理万集成电路有限公司 | Novel parallel semiconductor parameter testing system |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102542320B (en) * | 2010-12-10 | 2014-12-10 | 上海华虹宏力半导体制造有限公司 | Radio frequency identification (RFID) chip structure and test method for reducing test crosstalk |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0462706A1 (en) * | 1990-06-11 | 1991-12-27 | ITT INDUSTRIES, INC. (a Delaware corporation) | Contact assembly |
| DE19907727A1 (en) * | 1999-02-23 | 2000-08-24 | Test Plus Electronic Gmbh | Test adapter for contacting assembled printed circuit boards |
| CN100395879C (en) * | 2005-12-05 | 2008-06-18 | 深圳市矽电半导体设备有限公司 | Multiplex test method for semiconductor wafer and multiplex test probe station therefor |
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2006
- 2006-12-04 CN CN 200610119039 patent/CN101196554B/en active Active
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101510520B (en) * | 2009-03-18 | 2011-05-11 | 上海华岭集成电路技术有限责任公司 | Test method for asynchronously repairing and adjusting silicon wafer with anti-interference |
| CN103267940A (en) * | 2013-05-06 | 2013-08-28 | 上海华岭集成电路技术股份有限公司 | Multi-module parallel test system and multi-module parallel test method |
| CN103267940B (en) * | 2013-05-06 | 2016-08-10 | 上海华岭集成电路技术股份有限公司 | Multimode parallel test system |
| CN106409707A (en) * | 2015-07-28 | 2017-02-15 | 中芯国际集成电路制造(上海)有限公司 | Non-contact RF chip wafer testing method and apparatus |
| CN106841980A (en) * | 2017-01-10 | 2017-06-13 | 芯原微电子(上海)有限公司 | A kind of Bluetooth integrated circuit test system and method for testing |
| CN108828382A (en) * | 2018-07-26 | 2018-11-16 | 上海华虹宏力半导体制造有限公司 | Multi-chip integration test method |
| CN114152858A (en) * | 2022-02-08 | 2022-03-08 | 广州粤芯半导体技术有限公司 | Electrical test device and test method for cutting channel device |
| CN115201529A (en) * | 2022-07-29 | 2022-10-18 | 海宁理万集成电路有限公司 | Novel parallel semiconductor parameter testing system |
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| Publication number | Publication date |
|---|---|
| CN101196554B (en) | 2010-05-12 |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20140108 |
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Free format text: CORRECT: ADDRESS; FROM: 201206 PUDONG NEW AREA, SHANGHAI TO: 201203 PUDONG NEW AREA, SHANGHAI |
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Effective date of registration: 20140108 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Patentee before: Shanghai Huahong NEC Electronics Co., Ltd. |