CN115856588B

CN115856588B - Chip test board and test method

Info

Publication number: CN115856588B
Application number: CN202310147575.5A
Authority: CN
Inventors: 顾勋; 刘凡; 葛蕤馨; 李垣杰
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2023-02-22
Filing date: 2023-02-22
Publication date: 2023-08-04
Anticipated expiration: 2043-02-22
Also published as: CN115856588A

Abstract

The disclosure provides a chip test board and a test method, and relates to the technical field of semiconductors. Comprising the following steps: a plurality of chip test branches, each corresponding to a chip to be tested; each chip testing branch circuit comprises a switching element and a chip connecting element which are connected in series, and the chip connecting element is used for connecting a chip to be tested corresponding to the chip testing branch circuit; the switch control device is used for sending a switch conduction signal to the switching element of the target chip test branch, wherein the switch conduction signal is used for controlling the switching element of the target chip test branch to be conducted, and the target chip test branch comprises at least one chip test branch; the chip management device is used for acquiring the electrical performance parameters of the chip to be tested corresponding to the target chip testing branch through one end of the chip connecting element in the target chip testing branch when the switching element of the target chip testing branch is conducted. According to the embodiment of the disclosure, the chip testing efficiency can be improved.

Description

Chip test board and test method

Technical Field

The disclosure relates to the field of semiconductor technology, and in particular, to a chip test board and a test method.

Background

In the process of producing the packaged chip, the chip may be malfunctioning due to electrostatic Discharge (ESD) in the production environment, and defects in the manufacturing process itself. If the malfunction cannot be monitored in time, irreversible damage to the chip may be caused, thereby reducing the yield of the chip. In view of the fact that such functional defects can be obtained through analysis of electrical performance parameters such as current, in the production test process, in order to improve the yield of chips, the electrical performance parameters of the chips to be tested can be monitored by using the chip test board.

In one related art, a multimeter can be attached to a chip test board to test electrical performance parameters of each chip under test with the multimeter. However, this test mode has a low test efficiency.

Therefore, a solution capable of improving the chip test efficiency is required.

It should be noted that the information disclosed in the above background section is only for enhancing understanding of the background of the present disclosure and thus may include information that does not constitute prior art known to those of ordinary skill in the art.

Disclosure of Invention

The present disclosure provides a chip test board and a test method, which overcome the problem of low chip test efficiency in the related art at least to some extent.

Other features and advantages of the present disclosure will be apparent from the following detailed description, or may be learned in part by the practice of the disclosure.

According to one aspect of the present disclosure, there is provided a chip test board including:

a plurality of chip test branches, each corresponding to a chip to be tested; one end of each chip testing branch is connected with the positive electrode of the voltage source, and the other end of each chip testing branch is connected with the negative electrode of the voltage source; each chip testing branch circuit comprises a switching element and a chip connecting element which are connected in series, and the chip connecting element is used for connecting a chip to be tested corresponding to the chip testing branch circuit;

the switch control device is connected with the control end of the switching element in each chip test branch and is used for sending a switch conduction signal to the control end of the switching element of the target chip test branch, and the switch conduction signal is used for controlling the switching element of the target chip test branch to be conducted, wherein the target chip test branch comprises at least one chip test branch;

the chip management device is connected with one end of the chip connecting element in each chip testing branch and is used for acquiring the electrical performance parameters of the chip to be tested corresponding to the target chip testing branch through one end of the chip connecting element in the target chip testing branch when the switching element of the target chip testing branch is conducted so as to perform chip testing on the chip to be tested corresponding to the target chip testing branch by utilizing the acquired electrical performance parameters.

In one embodiment, a chip management apparatus includes:

the electrical performance parameter monitor is used for monitoring electrical performance parameters of chips to be tested of the plurality of chip testing branches;

the first power supply is used for providing voltage signals for the chips to be tested corresponding to each chip test branch.

In one embodiment, the voltage source is a first power supply; or the chip test board is connected to the test machine, and the voltage source is a second power supply in the test machine;

the switch element comprises a fixed contact end, a first movable contact end and a second movable contact end, wherein the fixed contact end of the switch element is used for being connected with a chip connecting element connected with the fixed contact end in series, the first movable contact end is used for being connected with a first power supply device, the second movable contact end is used for being connected with a second power supply device,

the switch control device is specifically used for controlling the conduction between the fixed contact end of the switch element of the target chip test branch and the first movable contact end or the second movable contact end,

when the fixed contact end of the switching element of the target chip testing branch circuit is conducted with the first movable contact end, the first power supply is used as a voltage source; when the fixed contact end of the switching element of the target chip testing branch circuit is conducted with the second movable contact end, the second power supply is used as a voltage source.

In one embodiment, the electrical performance parameter monitor includes a current monitoring element,

The current monitoring element is connected with the other end of the chip connecting element of each chip testing branch and is used for collecting current parameters of the chip to be tested connected with the chip connecting element from the other end of the chip connecting element, wherein one end of the chip connecting element is used for receiving voltage signals of the voltage source.

In one embodiment, the electrical performance parameter monitor includes a plurality of signal receiving pins, each corresponding to a chip under test,

each signal receiving pin is used for acquiring the electrical performance parameters of the corresponding chip to be tested.

In one embodiment, the chip test board further comprises:

the analog-to-digital conversion device is used for receiving the electrical performance parameters of the analog signal format sent by the chip management device and converting the electrical performance parameters of the analog signal format into the electrical performance parameters of the digital signal format;

the processing device is also used for processing the electrical performance parameters of the digital signal format.

In one embodiment, the chip test board further comprises:

and the storage device is used for storing the data to be stored of the chip test board.

In one embodiment, a serial data bus is connected between the analog-to-digital conversion device and the chip management device,

The chip management apparatus is further configured to: and transmitting the electrical performance parameters of the analog signal format obtained through monitoring to the analog-to-digital conversion device through a serial data bus.

In one embodiment, the processing device is further configured to: and sending the electrical performance parameters of the digital signal format to the test machine so that the test machine generates a test log based on the electrical performance parameters of the digital signal format and outputs the test log.

In one embodiment, the processing device is further configured to:

receiving a chip test command sent by a test machine station, wherein the chip test command is used for indicating to test a chip to be tested corresponding to a target chip test branch, and the chip test command is also used for controlling the chip to be tested to be in a preset working mode;

and responding to the chip test command, and controlling the chip to be tested corresponding to the target chip test branch to be in a preset working mode so as to test the chip to be tested in the preset working mode.

In one embodiment, a first command bus is connected between the processing device and the test machine, the first command bus is used for transmitting a chip test command, the chip test command is used for indicating to test a chip to be tested corresponding to the target chip test branch, and the chip test command is also used for controlling the chip to be tested to be in a preset working mode;

And/or the number of the groups of groups,

a first input/output bus is connected between the processing device and the test machine, and the first input/output bus is used for transmitting the electrical performance parameters of the digital signal format.

In one embodiment, a second command bus is connected between each chip to be tested and the test machine, and the second command bus is used for transmitting commands between the chip to be tested and the test machine;

and/or the number of the groups of groups,

and a second input/output bus is connected between each chip to be tested and the test machine, and the second input/output bus is used for carrying out data transmission between each chip to be tested and the test machine.

In one embodiment, each chip test branch further includes a resistive element,

in each chip test branch, a first connection end of a switching element of the chip test branch is used for being connected with an anode of a voltage source, a second connection end of the switching element of the chip test branch is used for being connected with one end of a chip connection element, the other end of the chip connection element of the chip test branch is used for being connected with one end of a resistance element, and the other end of the resistance element is used for being connected with a cathode of the voltage source.

In one embodiment, the chip connection element includes a chip socket.

According to another aspect of the present disclosure, there is provided a chip testing method applied to the above chip testing board, the method including:

A switch conduction signal is sent to the control end of the switching element of the target chip test branch circuit, and the switch conduction signal is used for controlling the switching element of the target chip test branch circuit to be conducted;

when the switching element of the target chip testing branch is conducted, the electrical performance parameters of the chip to be tested corresponding to the target chip testing branch are obtained, and the obtained electrical performance parameters are utilized to conduct chip testing on the chip to be tested corresponding to the target chip testing branch.

According to the chip test board and the test method provided by the embodiment of the disclosure, the switch control device can control the switch element of the target chip test branch to be conducted through the switch conducting signal, can provide the voltage signal provided by the voltage source to the chip to be tested corresponding to the target chip test branch, and can acquire the electrical performance parameter of the chip to be tested corresponding to the target chip test branch through the chip management device to conduct chip test. Because in the chip test board provided by the embodiment of the disclosure, the switch control device and the chip management device can be shared by a plurality of chip test branches, and then enough usable areas can be reserved for the chip test branches on the chip test board, so that a sufficient number of chip test branches can be arranged on the chip test board, and a sufficient number of chips to be tested can be tested by using the chip test board, thereby improving the test efficiency of the chips to be tested.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure. It will be apparent to those of ordinary skill in the art that the drawings in the following description are merely examples of the disclosure and that other drawings may be derived from them without undue effort.

FIG. 1 is a schematic diagram showing a test structure of a chip test scheme in the related art;

FIG. 2 illustrates a schematic diagram of an exemplary chip test board provided by embodiments of the present disclosure;

FIG. 3 is a schematic diagram of a chip test board according to an embodiment of the disclosure;

fig. 4 shows a schematic structural diagram of a switching element provided in an embodiment of the present disclosure;

FIG. 5 is a schematic diagram of another chip test board according to an embodiment of the disclosure;

FIG. 6 illustrates a schematic diagram of an exemplary chip test board provided by an embodiment of the present disclosure;

FIG. 7 shows a schematic structural diagram of yet another chip test board in an embodiment of the disclosure;

FIG. 8 is a schematic diagram of a chip test board according to an embodiment of the disclosure;

FIG. 9 is a schematic diagram of a chip test board according to another embodiment of the disclosure; and

fig. 10 is a flow chart illustrating a method for testing a chip according to an embodiment of the disclosure.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments may be embodied in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus a repetitive description thereof will be omitted. Some of the block diagrams shown in the figures are functional entities and do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in software or in one or more hardware modules or integrated circuits or in different networks and/or processor devices and/or microcontroller devices.

It should be understood that the various steps recited in the method embodiments of the present disclosure may be performed in a different order and/or performed in parallel. Furthermore, method embodiments may include additional steps and/or omit performing the illustrated steps. The scope of the present disclosure is not limited in this respect.

It should be noted that the terms "first," "second," and the like in this disclosure are merely used to distinguish between different devices, modules, or units and are not used to define an order or interdependence of functions performed by the devices, modules, or units.

It should be noted that references to "one", "a plurality" and "a plurality" in this disclosure are intended to be illustrative rather than limiting, and those of ordinary skill in the art will appreciate that "one or more" is intended to be understood as "one or more" unless the context clearly indicates otherwise.

In the process of producing the packaged chip, the packaged chip may be poorly functioning due to factors such as electrostatic Discharge (ESD) in the production environment, and defects in the manufacturing process itself. If the malfunction cannot be monitored in time, irreversible damage to the chip may be caused, thereby reducing the yield of the chip.

Therefore, in order to improve the chip yield, the chip test board may be used to monitor the electrical performance parameters such as voltage and/or current of the packaged chip.

In a related art, fig. 1 shows a schematic diagram of a test structure of a chip test scheme in the related art. As shown in fig. 1, in this related art, a plurality of multimeters 20 can be attached to a substrate 10 of a chip test board. Wherein each multimeter 20 is correspondingly connected to one device under test (Device Under Test, DUT), i.e. to one of DUTs 1 to 6, and each multimeter is adapted to test a connected device under test (i.e. chip under test).

Then, the related art has one or more of the following disadvantages.

The disadvantage 1 is that the related technology cannot be applied to large-scale test of a test chip due to the fact that the number of the multimeter arranged is limited due to the limited area of the test board, and therefore the test efficiency of the chip is low.

Disadvantage 2, multimeters do not guarantee time-domain accuracy of measured electrical performance parameters. And, the test accuracy of multimeters tends to be low, affecting the chip test accuracy.

Disadvantage 3 this solution requires reserving circuitry on the test board for stringing the DUT into the test structure, making automated testing difficult.

In another related art, the test machine itself may monitor the Power Supply module (Power Supply), however, the related art tests the total current of all the chips under test, and it is difficult to recognize the current of a single chip under test.

In order to solve at least one of the above technical problems, the embodiments of the present disclosure provide a chip test scheme, which can be applied to a chip test scenario, for example, a test scenario of a packaged chip. Through the chip test board that this disclosed embodiment provided, a plurality of chip test branch circuits can share switch control device and chip management device, and then can leave sufficient usable floor area for the chip test branch circuit on the chip test board for can set up the chip test branch circuit of sufficient quantity on the chip test board, with utilize the chip test board can test the chip that awaits measuring of sufficient quantity, thereby improved the test efficiency of the chip that awaits measuring.

In order to facilitate understanding of the technical solutions provided by the embodiments of the present disclosure, before describing in detail the technical solutions provided by the embodiments of the present disclosure, a specific example is used to describe the technical solutions provided by the embodiments of the present disclosure in its entirety.

Fig. 2 shows a schematic structural diagram of an exemplary chip test board provided by an embodiment of the disclosure. Wherein the dashed arrow in fig. 2 is used to represent the communication connection between the chip management device 330 and the switch control device 320. Illustratively, the two may be connected by a serial bus. As shown in fig. 2, a chip test board provided by an embodiment of the present disclosure may include a switch control device 320 and a chip management device 330. The chip management apparatus 330 and the switch control apparatus 320 may be integrated on the substrate 10 of the chip test board. The substrate 10 may be a circuit board for testing a chip. Illustratively, the substrate 10 may be a printed circuit board (Printed Circuit Boards, PCB) or the like.

As shown in fig. 2, the chip management apparatus 330 may monitor electrical performance parameters of any one or more chip ICs under the control of the switch control apparatus 320, so as to implement chip testing of any one or more chip ICs under test.

Next, the chip test board and the chip test method according to the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings and examples.

First, a chip test board is provided in an embodiment of the present disclosure.

Fig. 3 shows a schematic structural diagram of a chip test board in an embodiment of the disclosure. As shown in fig. 3, the chip test board provided in the embodiments of the present disclosure may include n chip test branches 310, a switch control device 320, and a chip management device 330. Wherein n may be any positive integer greater than or equal to 2, and n may be set according to a specific test scenario and a specific test requirement, which is not particularly limited.

Next, each constituent structure of the chip test board will be described in order.

For the chip test branches 310, each chip test branch corresponds to a chip under test. One end of each chip testing branch 310 is connected to the positive electrode of the voltage source 340, and the other end of each chip testing branch 310 is connected to the negative electrode of the voltage source 340. Illustratively, by this connection, the voltage source 340 may provide a voltage signal for each chip test branch.

To facilitate understanding of the chip test branch 310, the technical terms involved, and the specific arrangement of the n chip test circuits 310, will be described.

The chip to be tested may refer to a chip to be tested. In some embodiments of the present disclosure, the chip to be tested may refer to a packaged chip, i.e., a packaged chip, obtained after performing a packaging process. The packaged chips can be tested through the electrical performance parameters of the packaged chips, so that the chip defects possibly caused by reasons such as ESD, self-processing defects and the like in the chip packaging process are avoided, and the yield of the packaged chips is improved.

For the voltage source 340, it may be a structure, a circuit module, etc. capable of providing a test voltage signal to the chip under test. In some embodiments, the voltage source 340 may be a voltage source internal to the chip test board, such as may be the first power supply in a chip management device. For example, to improve stability of the test, the first power supply may be a constant voltage power supply. In other embodiments, the voltage source 340 may be a voltage source external to the chip test board, such as a second power supply in the test station 40 connected to the chip test board. It should be noted that, the voltage source 340 may also be implemented as other structures, circuits or functional modules capable of providing a voltage signal, which is not limited in particular. And, for the connection between the chip test board and the test machine 40, the chip test board may be mounted on the test machine 40, or the chip test board and the test machine 40 may be separately disposed, and the two may be connected by a connection cable, which is not particularly limited.

The specific arrangement of the n chip test circuits 310 is as follows. In one embodiment, n chip test branches 310 may be disposed inside a chip test board. Optionally, to improve signal monitoring quality, the n chip test branches 310 may have different depths compared to the chip test board surface. For example, they may be arranged in different hierarchies. By setting the n chip test branches 310 to different depths, the influence of data crosstalk, data loss, signal reflection and the like between the chip test branches 310 on the monitored electrical performance parameters can be reduced, and the signal monitoring quality is improved.

Having described the above, a description of the specific structural elements of the chip test branch 310 follows.

As shown in fig. 3, each chip test branch 310 includes a switching element 311 and a chip connecting element 312 connected in series.

As for the switching element 311, it can be used to control the on or off of the chip test branch 310 where it is located. For any one of the chip test branches 310, when the switching element 311 in that branch is turned on, the positive voltage of the voltage source may be applied to one end of the chip under test to which the chip connection element 312 in that branch is connected. The switching element 311 may be implemented as a device having a switching function, such as a relay, a transistor, or a circuit or a device having a switching function, for example, without being particularly limited.

In some embodiments, the switching element 311 may include a fixed contact and m movable contacts, where the fixed contact may be connected to the chip connecting element 312 connected in series therewith, the m movable contacts may be respectively connected to different available voltage sources, and when the fixed contact is conducted with one of the movable contacts, the available voltage source to which the one movable contact is connected may be used as the voltage source 340 in the embodiments of the present disclosure. Where m may be any integer greater than or equal to 2, which is not particularly limited. The switching element 311 may be implemented as a switching chip or a MOS series-parallel structure, for example, without particular limitation.

In one embodiment, fig. 4 shows a schematic structural diagram of a switching element according to an embodiment of the present disclosure. As shown in fig. 4, in the case that the voltage source may be the first power supply 332 in the chip management device 330 or the second power supply 41 in the test machine 40, the switching element 311 may include a fixed contact 311A, a first movable contact 311B, and a second movable contact 311C.

The fixed contact 311A of the switching element 311 is used for connecting to a chip connecting element 312 connected in series therewith, the first movable contact 311B of the switching element 311 is used for connecting to a first power supply 332, and the second movable contact 311C of the switching element 311 is used for connecting to a second power supply 41.

At this time, the switch control device 320 is specifically configured to control the conduction between the fixed contact terminal 311A of the switching element 311 of the target chip testing branch and the first movable contact terminal 311B of the switching element 311 of the target chip testing branch. When the fixed contact 311A of the switching element 311 of the target chip testing branch is connected to the first movable contact 311B, the first power supply 332 is used as the voltage source 340.

Alternatively, the switch control device 320 is specifically configured to control the conduction between the fixed contact terminal 311A of the switching element 311 of the target chip testing branch and the second movable contact terminal 311C of the switching element 311 of the target chip testing branch. When the fixed contact 311A of the switching element 311 of the target chip testing branch is connected to the second movable contact 311C, the second power supply 41 is used as the voltage source 340.

Through the embodiment, the second power supply or the first power supply in the test machine can be flexibly selected as the voltage source according to the test requirement by controlling the conduction between the fixed contact end and the two movable contact ends (namely the first movable contact end and the second movable contact end) of the switch element 311, so that the reasonable setting of the voltage source is realized, and the test flexibility and the reasonable utilization of the energy are improved.

After the switching element 311 is described, the description of the chip connection element 312 is continued.

For the chip connecting element 312, it is used to connect the chip to be tested corresponding to the chip test branch. For example, for any one of the chip test legs 310, the chip connecting element 312 in that leg may connect the connected chip under test to that leg. In a specific example, when the chip to be tested is connected to the branch, the Input end (Input) of the chip to be tested is connected to the other end of the switching element, and the Output end (Output) of the chip to be tested is used for being directly connected to the negative electrode of the voltage source, or is connected to the negative electrode of the voltage source through the resistor element. For example, the input terminal of the chip under test may be a Power supply (Power) terminal of the chip under test.

In one embodiment, the chip connection element may be implemented as a Socket structure (Socket). The slot structure can be used for fixing the chip to be tested and connecting the chip to be tested into the chip test circuit. In one example, the chip connection element may include a power pin and a signal pin. The power pin of the chip connecting element is connected with the power pin of the chip to be tested, so that when the switch element is turned on, the voltage signal provided by the voltage source 340 is provided to the chip to be tested through the power pin of the chip connecting element. And the signal pins of the chip connecting element are connected with the signal pins of the chip to be tested, so that when the switch element is conducted, the electrical performance parameters of the chip to be tested are provided to the chip management device through the signal pins of the chip connecting element.

In the example, the chip to be tested can be quickly plugged and unplugged through the slot structure, the chip to be tested can be quickly connected into the chip test branch circuit when the test is started, and the chip to be tested can be quickly disconnected from the chip test branch circuit when the test is ended, so that the chip test efficiency is further improved. And the slot structure can realize the mass and automatic test of the chips to be tested.

It should be noted that, the chip connecting element 312 may be other structures capable of connecting the chip to be tested, or a substrate area for placing the test chip in the substrate of the chip test board, and the like, which is not particularly limited.

In some embodiments, fig. 5 shows a schematic structural diagram of another chip test board in an embodiment of the disclosure. As shown in fig. 5, each chip test branch 310 further includes a resistive element 313.

In each chip test branch 310, a first connection end of the switching element 311 of the branch is used for being connected with the positive electrode of the voltage source 340, a second connection end of the switching element 311 of the branch is used for being connected with one end of the chip connecting element 312, the other end of the chip connecting element 312 of the branch is used for being connected with one end of the resistance element 313, and the other end of the resistance element 313 is used for being connected with the negative electrode of the voltage source 340.

In a specific example, fig. 6 shows a schematic structural diagram of an exemplary chip test board provided by an embodiment of the disclosure. As shown in fig. 6, the resistive elements in the n chip test branches may include variable resistors R1 to Rn. The flexible control of the chip test branch can be realized through the variable resistor, so that the voltage applied to the test chip can be flexibly adjusted in a mode of adjusting the variable resistor according to the chip type or the chip working mode and the like, and the test flexibility is improved.

It should be noted that the resistive element 313 may include one or more resistors connected in series, parallel, or series-parallel connection. Or may be implemented as a device, circuit or functional module having a resistive function, without particular limitation.

Through the embodiment, the excessive current in the chip test branch can be avoided through the resistor element 313, so that the damage of the large current to the chip management device, such as the damage to the electrical performance parameter monitor or the voltage unit in the chip management device, can be avoided, and the safety of the chip test board is improved.

It should be noted that other functional modules, devices or circuit units may be disposed in the chip test branch according to the actual test requirements and test scenarios, which is not particularly limited.

After the chip test branch 310 is introduced through the above, the description of the switch control device 320 is continued.

The switch control device 320 is connected to the control end of the switching element in each chip testing branch, and is used for sending a control end switch on signal to the switching element of the target chip testing branch, where the switch on signal is used for controlling the switching element 311 of the target chip testing branch to be turned on. In one example, the switch on signal may be a high level signal or a low level signal, etc. Illustratively, the switch on signal may control the on and off of devices such as relays, transistors, etc. in the switching element.

Alternatively, the switch control device 320 may also control the on/off of the switching elements 311 of the other chip test branches of the n chip test branches except for the target chip test branch, while controlling the on/off of the switching elements 311 of the target chip test branch. In one example, the switch control device 320 may be referred to as a master chip module, which may include one or more master chips (or referred to as control chips) to implement control functions.

The target chip test branch circuit comprises at least one chip test branch circuit of n chip test branch circuits. The target chip test branch may be a particular chip test branch, for example. In one example, a target chip test leg may be selected among n chip test legs according to preset test logic. For example, if n chips to be tested are arranged in an array, the n chip test branches may be used as target chip test branches to obtain electrical performance parameters of the n chips to be tested for chip testing. Then, the problem can be corresponding to a certain column, and the chip testing branch corresponding to the chip to be tested in the same column is taken as the target chip testing branch, so as to obtain the electrical performance parameters of the chip to be tested in the column. Then, the test chips in the column can be removed one by one for testing until the problem is positioned to a certain chip to be tested. It should be noted that, the target chip test branch may be selected by other preset test logic, for example, n chip test branches may be sequentially selected as the target chip test branch, so as to monitor electrical performance parameters and test chips of n chips to be tested one by one.

After the description of the target chip test branch, the specific structure of the switch control device 320 will be described next.

The switch control device 320 is configured to control the on state of the switching element 311 of the test branch of the target chip, wherein the content of this portion may be referred to the related description of the above portion in the embodiments of the present disclosure, and will not be described herein. Illustratively, the switch control device 320 may be a switch control circuit in a main control chip. The main control chip can be a semiconductor chip with a control function.

And, in order to facilitate understanding of the switching control device, other constituent devices of the chip test board will be described next. In some embodiments, fig. 7 shows a schematic structural diagram of yet another chip test board in an embodiment of the disclosure. As shown in fig. 7, the chip test board may further include an analog-to-digital conversion means 350 and a processing means 360.

The analog-to-digital conversion device 350 is configured to receive the electrical performance parameter in the analog signal format sent by the chip management device 330, and convert the electrical performance parameter in the analog signal format into the electrical performance parameter in the digital signal format. For example, the analog-to-digital conversion device 350 may receive the electrical performance parameter of the chip to be tested corresponding to the test branch of the target chip and convert the electrical performance parameter from the analog signal format to the digital signal format.

The analog-to-digital conversion apparatus 350 may be implemented as a device, a circuit structure, or a functional module having a function of converting between an analog signal and a digital signal, for example, without being particularly limited thereto.

In one embodiment, a serial data bus 370 is connected between the analog-to-digital conversion device 350 and the chip management device 330. Accordingly, the chip management apparatus 330 is further configured to transmit the electrical performance parameters in the analog signal format obtained by monitoring to the analog-to-digital conversion apparatus 350 through the serial data bus 370. The serial data bus 370 may be a bus capable of data transmission between devices, and is not particularly limited.

Through this embodiment, through serial data bus 370, the fast transmission of the electrical performance parameters can be realized, and the transmission rate of the electrical performance parameters is ensured, thereby further improving the chip testing efficiency.

After the analog-to-digital conversion means 350 are described, the description of the processing means 360 is continued. The processing device 360 may be a processing circuit or a processing functional module in the main control chip, which is not limited in particular. Illustratively, the processing device 360 and the switch control device 320 may be different functional modules or different circuit units in the same main control chip, which is not particularly limited.

And the processing device 360 is used for processing the electrical performance parameters of the digital signal format. Illustratively, the processing device 360 may send the electrical performance parameters in digital signal format to the test station 40. Alternatively, the processing device 360 may further determine whether the chip to be tested passes the chip test by determining whether the electrical performance parameter based on the digital signal format meets the preset chip test requirement.

It should be noted that, the processing device 360 may also perform other processing on the electrical performance parameters of the digital signal format according to the written parameter processing logic, which is not limited in particular.

In one embodiment, with continued reference to fig. 6, the processing device 360 is further configured to send the electrical performance parameters in the digital signal format to the test station 40, so that the test station 40 generates a test Log (Log) based on the electrical performance parameters in the digital signal format, and outputs the test Log. Illustratively, the processing device 360 may send the electrical performance parameters acquired during the period of time to the test machine 40 at intervals of time, and the test machine 40 generates a test log based on the electrical performance parameters acquired during the period of time, thereby implementing serial output of the test log. The serial output of the test log can facilitate the device with the chip test function to test the chip based on the test log in time, so that the test efficiency is improved.

Through the embodiment, the electrical performance parameters monitored by the chip test board can be timely sent to subsequent equipment to process the performance parameters through the test log generated by the test machine, so that the rationality and the order of chip test are realized.

In one embodiment, the processing device 360 is further configured to:

and receives the chip test command sent by the test machine 40. The chip test command is used for indicating to test the chip to be tested corresponding to the target chip test branch, and the chip test command is also used for controlling the chip to be tested to be in a preset working mode.

And responding to the chip test command, and controlling the chip to be tested corresponding to the target chip test branch to be in a preset working mode so as to test the chip to be tested in the preset working mode. The preset operation mode may be a mode in which the electrical performance of the chip to be tested needs to be tested in the mode. The preset operation mode may be, for example, a write mode, a read mode, an idle mode, a precharge mode, etc., which is not particularly limited.

In one example, the processing device 360 may receive a chip test command sent by the test bench 40, and the processing device 360 may control the chip under test to enter the write mode in response to the chip test command, and then the chip management device 330 may obtain a current parameter of the chip under test in the write mode, and then determine whether the chip under test is normal in the write mode according to the current parameter. In a specific example, after the current parameter of the chip to be tested is obtained, it may be determined whether the current parameter of the chip to be tested is in a preset current value range, and if the current parameter is smaller than a lower limit value of the preset current value range or larger than an upper limit value of the preset current value range, it is determined that the chip to be tested is abnormal in the write mode. The preset current value range is the current change range of the chip to be tested in the write mode.

According to the embodiment, the chip to be tested on the designated one or more target chip test branches can be accurately tested through the chip test command, and the definability and the test flexibility of the chip test are improved. And the chip to be tested corresponding to the target chip test branch can be controlled to be in a preset working mode through the chip test command, so that the chip characteristics of the chip to be tested in a specific working mode can be tested, and the accuracy and the flexibility of chip test are improved.

It should be noted that, other command control may be performed on the main control module or the chip to be tested through the chip test command, which is not particularly limited.

In one embodiment, fig. 8 shows a schematic structural diagram of yet another chip test board in an embodiment of the disclosure. As shown in fig. 8, the processing device 360 may be communicatively coupled to the test station 40.

In one example, a first command bus is coupled between processing device 360 and test station 40. The first command bus is used for transmitting a chip test command. The chip test command may be referred to the related description of the above portion of the embodiments of the disclosure, which is not described in detail herein.

Wherein the first command bus may be a bus capable of command transfer. Illustratively, the first command bus may include a CMD bus. The first command bus may be any other bus capable of transmitting commands, and is not particularly limited.

By setting the first command bus, communication between the processing device 360 and the test machine 40 can be realized, the processing device 360 can capture a chip test command sent by the test machine 40, and further flexible control of a switching element in a chip test branch and flexible control of a working mode and the like of a chip to be tested can be realized through the chip test command based on the test machine 40 and the processing device 360, so that the chip test precision and the flexibility of chip test are improved.

In another example, a first input/output bus is connected between the processing device 360 and the test station 40. For example, the test machine 40 may perform a chip test based on the acquired electrical performance parameters, and the first input/output bus is used for transmitting the electrical performance parameters in the digital signal format. Still another example, the first input-output bus is used to transmit the chip test results when the processing device 360 performs the chip test. Illustratively, when the processing device 360 performs a chip test, the processing device may include a comparison circuit, where the comparison circuit includes a first input terminal and a second input terminal, the first input terminal is used for acquiring an electrical performance parameter, the second input terminal is used for acquiring a reference electrical performance parameter, the comparison circuit is used for generating a chip test result according to the acquired electrical performance parameter and the reference electrical performance parameter, and the output terminal is used for outputting the chip test structure. The chip test result may be a high level signal or a low level signal.

The first Input/Output (I/O) bus may be a bus capable of data transmission. By way of example, it should be noted that other buses capable of data transfer may be employed, without specific limitation.

Through setting up first input/output bus, can realize the data transmission between processing apparatus 360 and the test board 40 to in time send the electrical property parameter that the chip test board monitored to follow-up equipment through test board 40 and handle the performance parameter, thereby realized rationality and the orderly nature of chip test.

And through the above-mentioned analog-to-digital conversion device 350 and the processing device 360, the electrical performance parameters of the analog signal format obtained by monitoring can be converted into the data signal format for transmission in a data conversion mode, so that the signal transmission quality of the electrical performance parameters is improved, the monitoring precision of the electrical performance parameters is further improved, the testing progress of the chip is further improved, and the yield of the chip is improved.

In other embodiments, with continued reference to fig. 7, the switch control device 320 further includes a storage device 380.

The storage device 380 may be used to store data to be stored of the chip test board. In one example, the storage 380 may include one or more memory chips. For data to be stored, it may be data that needs to be stored. The specific content of the data to be stored can be defined according to the specific test scene and the test requirement, and is not particularly limited. For example, the data to be stored may include electrical performance parameters in a digital signal format. As yet another example, the data to be stored may include control logic of a switching element or the like, which is not particularly limited.

By arranging the storage device 380, necessary data can be stored, and the reliability of the monitoring process of the electrical performance parameters and the reliability of the chip testing process are improved.

It should be noted that, according to the actual test requirements and the test scenario, the chip test board may further include other functional modules, such as devices or circuit units of the chip, which is not limited in particular.

After the switch control device 320 is described through the above, the description of the chip management device 330 is continued.

The chip management device 330 is connected to one end of the chip connection element in each chip testing branch 310, and is configured to obtain, when the switching element 311 of the target chip testing branch is turned on, an electrical performance parameter of the chip to be tested corresponding to the target chip testing branch through one end of the chip connection element in the target chip testing branch, so as to perform a chip test on the chip to be tested corresponding to the target chip testing branch by using the obtained electrical performance parameter. Optionally, the chip management apparatus 330 is further configured to monitor electrical performance parameters of the chips under test of the plurality of chip test branches 310. In some embodiments, the chip management apparatus 330 may dynamically monitor the electrical performance parameters of the chips under test of the plurality of chip test branches.

As for the electrical performance parameter, it may be a parameter capable of characterizing the electrical performance of the chip to be tested. Illustratively, the electrical performance parameter may include a current parameter and/or a voltage parameter, etc. It should be noted that the electrical performance parameter may be other parameters that are measured by the chip test board provided by the embodiment of the present disclosure and can represent the electrical performance of the chip to be tested, which is not particularly limited.

For chip testing, the chip testing result can be generated according to whether the electrical performance parameters of the chip to be tested meet the preset chip testing requirements. The preset chip test requirements may be, for example, numerical requirements for electrical performance parameters, requirements for fluctuation ranges, and the like, and are not particularly limited.

In some embodiments, fig. 9 shows a schematic structural diagram of yet another chip test board in an embodiment of the disclosure. As shown in fig. 9, the chip management apparatus 330 may include an electrical performance parameter monitor 331 and a first power supply 332.

The electrical performance parameter monitor 331 is used for monitoring electrical performance parameters of the chips to be tested of the plurality of chip testing branches. Illustratively, the electrical performance parameter monitor 331 may dynamically monitor the electrical performance parameters of the chips under test of the plurality of chip test branches.

In one embodiment, the electrical performance parameter monitor 331 includes a plurality of signal receiving pins, each corresponding to a chip to be tested, wherein each signal receiving Pin is used for obtaining an electrical performance parameter of the corresponding chip to be tested. Illustratively, the electrical performance parameter monitor 331 includes n signal receiving pins, where n signal testing pins are in one-to-one correspondence with the chips to be tested of n chip testing branches.

Through this example, the chip that awaits measuring of each chip test branch road corresponds different signal test pins to the electric property parameter that obtains through the monitoring of different signal test pins can carry out quick and accurate location to each chip that awaits measuring in parameter monitoring process and follow-up chip test process, has improved test accuracy and test reliability.

In another embodiment, the electrical performance parameters of the chips to be tested of the n chip test branches can be transmitted to the same signal bus, and then the signal bus is connected to one signal receiving pin of the electrical performance parameter monitor 331.

In one embodiment, with continued reference to FIG. 6, the electrical performance parameter monitor 331 includes a current monitoring element 3311.

The current monitoring element 3311 is connected to the other end of the chip connecting element of each chip testing branch, and is used for collecting current parameters of the chip IC to be tested connected to the chip connecting element from the other end of the chip connecting element. One end of the chip connecting element is used for receiving a voltage signal of the voltage source.

Illustratively, the current monitoring element 3311 may be implemented as a device, a functional module, and a circuit having a current monitoring function, which are not particularly limited. Illustratively, the current monitoring element 3311 may be a hall current sensor, an electromagnetic current transformer, or the like, or the current monitoring element 3311 may be a current detection circuit, a current detection chip, or the like, which is not particularly limited.

Through this embodiment, through the current monitoring component, can realize effectively monitoring the electric current of the chip that awaits measuring, realized test board level current monitoring function.

And, compared with the universal meter, the universal meter can only observe data with naked eyes, and therefore the data observation precision is lower. According to the embodiment of the disclosure, through the current monitoring element, the current monitoring precision can reach the millisecond level by selecting the current monitoring element with a proper model, and the current monitoring precision is improved. And the current signal can be monitored to change in the time domain through the current monitoring element, so that the monitoring precision of the electrical performance parameters such as current in the time domain is improved.

In another embodiment, the electrical performance parameter monitor 331 includes a voltage monitoring element. The voltage monitoring element can collect the pressure difference between two ends of the chip to be tested.

By way of example, the voltage monitoring element may be implemented as a device, a functional module, and a circuit having a voltage monitoring function, which are not particularly limited. Illustratively, the voltage monitoring element may be a voltage sensor such as a resistive voltage sensor, a capacitive voltage sensor, an electromagnetic voltage sensor, a capacitive voltage sensor, a hall voltage sensor, or the like, or the voltage monitoring element may be a voltage detection circuit, a voltage detection chip, or the like, which is not particularly limited.

It should be noted that, according to the actual test requirement and the test scenario, other functional modules, such as a device of a chip or a circuit unit, may also be included in the electrical performance parameter monitor 331, which is not limited in particular.

After the electrical performance parameter monitor 331 is described, the first power supply 332 is described next.

The first power supply 332 is configured to provide a voltage signal for a chip to be tested corresponding to each chip testing branch. Illustratively, the first power supply 332 may include a constant voltage power supply. The first power supply may be implemented as a power supply device, a circuit having a power supply function, a functional module, or the like, which is not particularly limited.

Through the embodiment, the chip management device 330 can monitor the electrical performance parameters through the electrical performance parameter monitor 331, and simultaneously can provide voltage signals for the chip test branch by using the first power supply 332, so that the monitoring of the electrical performance parameters of the chip to be tested can be realized by using the chip test board provided by the embodiment of the disclosure, and the monitoring precision is improved.

In other embodiments, the chip management apparatus 330 may include an electrical performance parameter monitor 331. The electrical performance parameter monitor 331 is referred to the related description of the above portions of the embodiments of the disclosure, and will not be repeated here.

It should be noted that, according to the actual test requirement and the test scenario, the chip management apparatus 330 may further include other functional modules, such as devices or circuit units of the chip, which is not limited in particular.

According to the chip test board provided by the embodiment of the disclosure, the switch control device can control the switch element of the target chip test branch to be conducted, can provide the voltage signal provided by the voltage source to the chip to be tested corresponding to the target chip test branch, and can acquire the electrical performance parameters of the chip to be tested corresponding to the target chip test branch through the chip management device to conduct chip test. Because in the embodiment of the disclosure, a plurality of chip test branches can share the test module and the chip management device, and then enough usable areas can be reserved on the chip test board for the chip test branches, a sufficient number of chip test branches can be arranged on the chip test board so as to test a sufficient number of chips to be tested by using the chip test board, and thus the test efficiency of the chips to be tested is improved. Illustratively, the embodiments of the present disclosure may improve chip testing efficiency when large-scale testing of a chip under test is required.

And the chip test board provided by the embodiment of the disclosure can control the on-off mode of the switching element on any chip test branch by the switch control device to realize the chip test of the chip to be tested corresponding to any chip test branch, thereby realizing the chip test of the specific chip position, enhancing the definability of the chip test and improving the chip test efficiency and the flexibility of the chip test. And compared with a multimeter test scheme, the automatic test of the chip to be tested can be realized, the test efficiency is improved, and the test difficulty is reduced.

In addition, the chip test board provided by the embodiment of the disclosure can fully utilize the characteristics of multiple layers and large area of the chip test board, integrate the switch control device and the chip management device into the chip test board, improve the integration level of the chip test board and realize the full utilization of the chip test board.

In addition, the chip test board provided by the embodiment of the disclosure can share the switch control device and the chip management device by a plurality of chip test branches, and compared with the related technical scheme of adopting a universal meter for testing, a plurality of universal test meters are not required to be arranged, so that the chip test cost is reduced.

In addition, the chip test board provided by the embodiment of the disclosure can timely diagnose faults such as short circuit and short circuit of the chip to be tested based on the electrical performance parameters obtained by monitoring after the electrical performance parameters of the chip to be tested of the target chip test branch are monitored, so that real-time early warning can be realized, and the automatic test of the chip is improved.

In some embodiments, with continued reference to FIG. 6, a second command bus is connected between the chip under test and the test station 40. The second command bus is used for transmitting commands between the chip to be tested and the test machine 40.

For example, the second command bus may be used to transmit a chip test command, which may be used to control the chip under test to be tested in a preset operating mode. It should be noted that, the chip test command may refer to the related description of the above portion of the embodiments of the disclosure, which is not repeated.

Wherein the second command bus may be a bus capable of command transfer. Illustratively, the second command bus may include a CMD bus. The second command bus may be any other bus capable of transmitting commands, and is not particularly limited.

By setting the second command bus, communication between the chip to be tested and the test machine 40 can be realized, so that flexible control of the chip to be tested can be realized based on the test machine 40, and the chip test precision and the flexibility of chip test are improved.

In other embodiments, with continued reference to fig. 6, a second input/output bus is connected between each chip under test and the test station 40, and the second input/output bus performs data transmission between each chip under test and the test station 40.

The second input/output bus may be a bus capable of data transmission. By way of example, it should be noted that other buses capable of data transfer may be employed, without specific limitation.

By providing the second input-output bus, data transmission between the chip to be tested and the test machine 40 can be realized, thereby realizing rationality and order of chip testing.

Based on the same inventive concept, the embodiments of the present disclosure also provide a chip testing method, such as the following embodiments.

Fig. 10 is a flowchart illustrating a chip testing method according to an embodiment of the disclosure, and as shown in fig. 10, the chip testing method includes S1010 and S1020.

S1010, a switch conduction signal is sent to the control end of the switching element of the target chip testing branch. The switch conduction signal is used for controlling the switch element of the target chip test branch to be conducted. Wherein the target chip test branch comprises at least one of a plurality of chip test branches.

S1020, when the switching element of the target chip testing branch is conducted, acquiring the electrical performance parameters of the chip to be tested corresponding to the target chip testing branch, so as to perform chip testing on the chip to be tested corresponding to the target chip testing branch by utilizing the acquired electrical performance parameters.

In one embodiment, S1020 includes step A1 and step A2.

Step A1, monitoring the electrical performance parameters of the chips to be tested of the plurality of chip testing branches.

And step A2, providing voltage signals for the chips to be tested corresponding to the chip test branches.

In one embodiment, the voltage source is a first power supply in the chip management apparatus or a second power supply in the test station.

The switch element comprises a fixed contact end, a first movable contact end and a second movable contact end, wherein the fixed contact end of the switch element is used for being connected with a chip connecting element connected with the fixed contact end in series, the first movable contact end is used for being connected with a first power supply device, and the second movable contact end is used for being connected with a second power supply device.

Accordingly, S1010 specifically includes: the fixed contact end of the switching element of the control target chip testing branch circuit is conducted with the first movable contact end or the second movable contact end.

In one embodiment, the electrical performance parameter monitor includes a current monitoring element connected to the other end of the die attach element of each die test branch.

Accordingly, step A1 may include: and collecting current parameters of the chip to be tested connected with the chip connecting element from the other end of the chip connecting element, wherein one end of the chip connecting element is used for receiving a voltage signal of a voltage source.

In one embodiment, S1010 includes step B1 and step B2.

And step B2, controlling the switching element of the test branch of the target chip to be conducted.

And step B1, receiving the electrical performance parameters of the analog signal format sent by the chip management device, and converting the electrical performance parameters of the analog signal format into the electrical performance parameters of the digital signal format.

And step B3, processing the electrical performance parameters of the digital signal format.

In one embodiment, the chip test method may further include step C1.

And step C1, storing data to be stored of the chip test board.

In one embodiment, a serial data bus is connected between the analog-to-digital conversion device and the chip management device. The chip test method may further include step C2.

And step C2, transmitting the electrical performance parameters of the analog signal format obtained through monitoring to the analog-to-digital conversion device through a serial data bus.

In one embodiment, the chip test method may further include step C3.

And step C3, the electrical performance parameters of the digital signal format are sent to the test machine, so that the test machine generates a test log based on the electrical performance parameters of the digital signal format, and the test log is output.

In one embodiment, the chip test method may further include step C4 and step C5.

And step C4, receiving a chip test command sent by the test machine. The chip test command is used for indicating to test the chip to be tested corresponding to the target chip test branch and controlling the chip to be tested to be in a preset working mode.

And step C5, responding to the chip test command, and controlling the chip to be tested corresponding to the target chip test branch to be in a preset working mode so as to test the chip to be tested in the preset working mode.

In one embodiment, a first command bus is connected between the switch control device and the test machine, the first command bus is used for transmitting a chip test command, and the chip test command is used for indicating to test a chip to be tested corresponding to the target chip test branch and controlling the chip to be tested to be in a preset working mode;

and/or the number of the groups of groups,

a first input/output bus is connected between the switch control device and the test machine, and the first input/output bus is used for transmitting the electrical performance parameters of the digital signal format.

and/or the number of the groups of groups,

In one embodiment, each chip test branch further includes a resistive element,

in each chip testing branch, a first connecting end of a switching element of the branch is used for being connected with an anode of a voltage source, a second connecting end of the switching element of the branch is used for being connected with one end of a chip connecting element, the other end of the chip connecting element of the branch is used for being connected with one end of a resistance element, and the other end of the resistance element is used for being connected with a cathode of the voltage source.

In one embodiment, the chip connection element includes a chip socket.

According to the chip testing method provided by the embodiment of the disclosure, the switch control device can control the switch element of the target chip testing branch to be conducted, can provide the voltage signal provided by the voltage source to the chip to be tested corresponding to the target chip testing branch, and can acquire the electrical performance parameters of the chip to be tested corresponding to the target chip testing branch through the chip management device to conduct chip testing. Because the chip test board provided by the embodiment of the disclosure, the plurality of chip test branches can share the test module and the chip management device, and then the chip test branches on the chip test board leave enough usable areas, so that the chip test branches with enough numbers can be arranged on the chip test board to test the chips to be tested with the chip test board, and the test efficiency of the chips to be tested is improved.

It should be noted that the chip testing method shown in fig. 10 may be applied to the device embodiments shown in fig. 3 to 8, and the respective processes and effects in the device embodiments shown in fig. 3 to 8 are implemented, which are not described herein.

Those skilled in the art will appreciate that the various aspects of the present disclosure may be implemented as a system, method, or program product. Accordingly, various aspects of the disclosure may be embodied in the following forms, namely: an entirely hardware embodiment, an entirely software embodiment (including firmware, micro-code, etc.) or an embodiment combining hardware and software aspects may be referred to herein as a "circuit," module "or" system.

It should be understood that, in the present specification, each embodiment is described in an incremental manner, and the same or similar parts between the embodiments are all referred to each other, and each embodiment is mainly described in a different point from other embodiments. The method embodiments are described in a relatively simple manner, and reference is made to the description of the system embodiments for relevant points. The disclosure is not limited to the specific steps and structures described above and shown in the drawings. Those skilled in the art may, after appreciating the spirit of the present disclosure, make various changes, modifications and additions, or change the order between steps. Also, a detailed description of known method techniques is omitted here for the sake of brevity.

In the several embodiments provided in the present disclosure, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some ports, devices or units, and may be in electrical, mechanical or other forms.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present disclosure may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.

The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it is intended to cover the scope of the disclosure.

Therefore, the scope of the present disclosure should be determined based on the scope of the claims, and this disclosure is intended to cover any modification, use, or adaptations of the disclosure that follows, in general, the principles of the disclosure and includes common general knowledge or practice in the art, not disclosed by the disclosure. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims

1. A chip test board, the test board comprising:

a plurality of chip test branches, each corresponding to a chip to be tested; one end of each chip testing branch is connected with the positive electrode of the voltage source, and the other end of each chip testing branch is connected with the negative electrode of the voltage source; each chip testing branch circuit comprises a switching element and a chip connecting element which are connected in series, wherein the chip connecting element is used for connecting a chip to be tested corresponding to the chip testing branch circuit;

the chip management device is connected with one end of the chip connecting element in each chip testing branch and is used for acquiring the electrical performance parameters of the chip to be tested corresponding to the target chip testing branch through one end of the chip connecting element in the target chip testing branch when the switching element of the target chip testing branch is conducted so as to perform chip testing on the chip to be tested corresponding to the target chip testing branch by utilizing the acquired electrical performance parameters;

The test board also comprises a processing device, wherein the processing device is used for responding to a chip test command and controlling the chip to be tested corresponding to the target chip test branch to be in a preset working mode so as to test the chip to be tested in the preset working mode;

each chip testing branch circuit further comprises a variable resistor, so that the voltage applied to the chip to be tested is adjusted in a mode of adjusting the variable resistor according to the working mode of the chip;

the chip test board comprises a plurality of chip test branches, a chip test board and a control unit, wherein the chip test branches are arranged inside the chip test board, and the depths of the chip test branches are different from those of the surface of the chip test board;

under the condition that chips to be tested corresponding to the chip test branches are arranged in an array, the chip test branches are used as target chip test branches, so that chip tests are performed based on electrical performance parameters of the chips to be tested corresponding to the chip test branches, and chip problems are positioned to any row of chips to be tested; and under the condition that the chip problem is positioned to any row of chips to be tested, taking the chip test branch corresponding to any row of chips to be tested as a target chip test branch, and removing the chip test branches corresponding to any row of chips to be tested from the target chip test branch one by one so as to position the problem to the target chips to be tested.

2. The chip test board of claim 1, wherein the chip management apparatus comprises:

the electrical performance parameter monitor is used for monitoring the electrical performance parameters of the chips to be tested of the plurality of chip testing branches;

3. The chip test board of claim 2, wherein the voltage source is the first power supply; or the chip test board is connected with a test machine, and the voltage source is a second power supply in the test machine;

the switch element comprises a fixed contact end, a first movable contact end and a second movable contact end, wherein the fixed contact end of the switch element is used for being connected with a chip connecting element connected with the fixed contact end in series, the first movable contact end is used for being connected with the first power supply device, the second movable contact end is used for being connected with the second power supply device,

when the fixed contact end of the switching element of the target chip testing branch circuit is conducted with the first movable contact end, the first power supply is used as the voltage source; and when the fixed contact end of the switching element of the target chip testing branch circuit is conducted with the second movable contact end, the second power supply is used as the voltage source.

4. The chip test board of claim 2, wherein said electrical performance parameter monitor comprises a current monitoring element,

the current monitoring element is connected with the other end of the chip connecting element of each chip testing branch and is used for collecting current parameters of the chip to be tested connected with the chip connecting element from the other end of the chip connecting element, wherein one end of the chip connecting element is used for receiving a voltage signal of the voltage source.

5. The chip test board of claim 2, wherein the electrical performance parameter monitor comprises a plurality of signal receiving pins, each signal receiving pin corresponding to a chip under test,

6. The chip test board of claim 1, wherein the chip test board further comprises:

and the processing device is also used for processing the electrical performance parameters of the digital signal format.

7. The chip test board of claim 1, wherein the chip test board further comprises:

8. The chip test board of claim 6, wherein a serial data bus is connected between said analog-to-digital conversion means and said chip management means,

the chip management device is also used for: and transmitting the electrical performance parameters of the analog signal format obtained through monitoring to the analog-to-digital conversion device through the serial data bus.

9. The chip test board of claim 6, wherein the chip test board comprises a plurality of chips,

the processing device is also used for: and sending the electrical performance parameters of the digital signal format to a test machine so that the test machine generates a test log based on the electrical performance parameters of the digital signal format and outputs the test log.

10. The chip test board of claim 6, wherein the chip test board comprises a plurality of chips,

the processing device is further configured to:

and receiving a chip test command sent by the test machine station, wherein the chip test command is used for indicating to test the chip to be tested corresponding to the target chip test branch, and the chip test command is also used for controlling the chip to be tested to be in a preset working mode.

11. The chip test board according to claim 9 or 10, wherein,

a first command bus is connected between the processing device and the test machine, the first command bus is used for transmitting a chip test command, the chip test command is used for indicating to test a chip to be tested corresponding to a target chip test branch, and the chip test command is also used for controlling the chip to be tested to be in a preset working mode;

and/or the number of the groups of groups,

a first input/output bus is connected between the processing device and the test machine, and the first input/output bus is used for transmitting electrical performance parameters of a digital signal format.

12. The chip test board of claim 1, wherein the chip test board comprises a plurality of chips,

a second command bus is connected between each chip to be tested and the test machine, and the second command bus is used for transmitting commands between the chip to be tested and the test machine;

and/or the number of the groups of groups,

and a second input/output bus is connected between each chip to be tested and the test machine, and the second input/output bus performs data transmission between each chip to be tested and the test machine.

13. The chip test board of claim 1, wherein each of said chip test branches further comprises a resistive element,

in each chip test branch, a first connection end of a switching element of the chip test branch is used for being connected with an anode of the voltage source, a second connection end of the switching element of the chip test branch is used for being connected with one end of the chip connection element, the other end of the chip connection element of the chip test branch is used for being connected with one end of the resistance element, and the other end of the resistance element is used for being connected with a cathode of the voltage source.

14. The chip test board of claim 1, wherein the chip connection element comprises a chip socket.

15. A chip testing method applied to the chip testing board according to any one of claims 1 to 14, the method comprising:

a switch conduction signal is sent to a control end of a switching element of a target chip test branch, wherein the switch conduction signal is used for controlling the switching element of the target chip test branch to be conducted, and the target chip test branch comprises at least one of a plurality of chip test branches;

When the switching element of the target chip testing branch is conducted, acquiring the electrical performance parameters of the chip to be tested corresponding to the target chip testing branch, and performing chip testing on the chip to be tested corresponding to the target chip testing branch by utilizing the acquired electrical performance parameters;

and, the method further comprises:

responding to a chip test command, and controlling a chip to be tested corresponding to the target chip test branch to be in the preset working mode so as to test the chip to be tested in the preset working mode;

adjusting the voltage applied to the chip to be tested by adjusting the variable resistor according to the chip working mode;

under the condition that chips to be tested corresponding to the chip test branches are arranged in an array, the chip test branches are used as target chip test branches, so that chip tests are performed based on electrical performance parameters of the chips to be tested corresponding to the chip test branches, and chip problems are positioned to any row of chips to be tested; and under the condition that the chip problem is positioned to any row of chips to be tested, taking a chip test branch corresponding to any row of chips to be tested as a target chip test branch so as to perform chip test based on the electrical performance parameters of any row of chips to be tested; and removing the chip test branches corresponding to any row of chips to be tested from the target chip test branches one by one so as to locate the problem to the target chips to be tested.