CN209979755U - Addressable test chip capable of improving resistance measurement precision and test system thereof - Google Patents
Addressable test chip capable of improving resistance measurement precision and test system thereof Download PDFInfo
- Publication number
- CN209979755U CN209979755U CN201920376170.8U CN201920376170U CN209979755U CN 209979755 U CN209979755 U CN 209979755U CN 201920376170 U CN201920376170 U CN 201920376170U CN 209979755 U CN209979755 U CN 209979755U
- Authority
- CN
- China
- Prior art keywords
- circuit
- tested
- addressing
- switch
- switch circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
- G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
- G01R27/08—Measuring resistance by measuring both voltage and current
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
Abstract
The utility model relates to an addressable test chip and a test system thereof, which can improve the resistance measurement precision, wherein the addressable test chip comprises an excitation circuit, an induction circuit, a plurality of devices to be tested and a plurality of bonding pads; the device to be tested forms DUT arrays, and a drive circuit and a sensing circuit are respectively arranged on the periphery of each DUT array. The utility model discloses still relate to a test system who has above-mentioned addressable chip. The utility model discloses can eliminate the influence of pressure drop, accurate measurement resistance value.
Description
Technical Field
The utility model relates to a semiconductor design and production field, in particular to addressable test chip and test system that can improve resistance measurement accuracy.
Background
The defect rate and yield of the production process are tested and obtained by a conventional semiconductor manufacturing through a short-range test chip, and the defect rate and yield can be divided into two types according to different positions in a wafer: a stand-alone test chip and a test chip placed in the scribe line. The area of the individual test chip is large, and the chip needs to occupy one chip position, which corresponds to the manufacturing cost of the mask for the part of the area, which is paid by the semiconductor manufacturer. The scribing groove is a space reserved for cutting chips on a wafer, and the test chip is placed in the scribing groove and does not occupy the chip, so that a semiconductor manufacturer does not need to bear expensive mask cost, and a large amount of cost is saved.
However, the short-range test chip requires a separate connection of the test unit to PADs (PADs), and two or more PADs are required for each test structure, which results in a low area utilization of the short-range test chip. Based on the consideration, the common addressable test chip greatly reduces the number of PADs and relatively improves the area utilization rate of the test chip by introducing an address decoding circuit similar to a static memory chip.
The common addressable Test Chip (Test Chip) is a universal Test Chip with an addressable circuit and consists of four basic structures, namely an addressing circuit, a switching circuit, a device to be tested (DUT) and a pin (pad), wherein the addressing circuit is connected with the switching circuit and outputs an address signal to control the on-off state of a switch in the switching circuit; the switch circuit is connected with the device to be tested so as to select a specific DUT to measure through the on-off state of the switch.
As shown in FIG. 1, for a test chip with more DUTs, the whole DUT area can be divided into several small DUT areas, i.e. the DUT area is divided into several arrays, and then the switch circuit and the addressing circuit are respectively arranged between the different arrays. However, in actual chip testing, a better design is to use only one DUT array for testing, all DUTs are in the same DUT area, and there is no redundant circuit or device in the DUT area, which is more similar to the actual usage scenario of the chip.
However, as manufacturing companies demand for integration, more and more DUTs will have more switching circuits, and the increase in switching circuits will tend to result in increased resistance in the test circuit. From experimental data, it can be seen that the resistance of the DUT is mainly affected by the switching circuitry, not the resistance of the metal in the DUT array. For some current test chips with higher density, if more switching circuits are used to realize more DUT selections, the resistance of the DUT may reach 1.5k ohm to 3k ohm, which causes a voltage drop during ldsat measurement, which may cause inaccurate measurement values and a small resistance that cannot be measured. Therefore, how to eliminate the influence of the pressure drop and improve the accuracy is a problem to be solved in the field.
SUMMERY OF THE UTILITY MODEL
The utility model discloses a main aim at overcomes not enough among the prior art, provides one kind and can eliminate the influence of pressure drop, the addressable test chip of accurate measurement resistance value and test system thereof.
The utility model also aims to provide an addressable test chip which can improve the resistance measurement precision, comprising an excitation circuit, an induction circuit, a plurality of devices to be tested and a plurality of bonding pads; the device to be tested forms DUT arrays, and the periphery of each DUT array is respectively provided with a drive circuit and a sensing circuit;
the excitation circuit comprises a switch circuit A and an addressing circuit A, the addressing circuit A is connected with the switch circuit A, the addressing circuit A outputs an address signal to control the on-off state of a switch in the switch circuit A, the switch circuit A is connected with a device to be tested, and the switch circuit A selects a specified device to be tested through the on-off state of the switch; the excitation circuit is used for applying a test voltage to the selected device to be tested;
the induction circuit comprises a switch circuit B and an addressing circuit B, the addressing circuit B is connected with the switch circuit B, the addressing circuit B outputs an address signal to control the on-off state of a switch in the switch circuit B, the switch circuit B is connected with a device to be tested, and the switch circuit B selects a specified device to be tested through the on-off state of the switch; the induction circuit is used for introducing low current to the selected device to be measured so as to measure the voltage at two ends of the device to be measured;
for the same DUT array, because the excitation circuit and the induction circuit at the periphery of the DUT array select the same device to be tested, in the excitation circuit and the induction circuit at the periphery of the same DUT array, the addressing circuit A and the addressing circuit B can share one addressing circuit to realize the operation, or the addressing circuit A and the addressing circuit B are respectively provided with one addressing circuit to realize the operation; that is, the addressing circuit a and the addressing circuit B may be implemented by using the same circuit structure, or two independent circuit structures may be configured to implement the addressing circuit a and the addressing circuit B separately.
As a further improvement, in the addressable test chip capable of improving the resistance measurement accuracy, all devices to be tested are not subjected to array division, that is, all devices to be tested form a DUT array, and the excitation circuit and the sensing circuit are respectively arranged on the periphery of the DUT array.
According to the addressable test chip capable of improving the resistance measurement accuracy, the voltage at two ends of a device to be tested is measured by using the induction circuit to calculate the resistance of the device to be tested, so that the influence of voltage drop caused by the increase of the switching circuits is eliminated, the DUT arrays are not divided, namely all DUTs are in the same DUT area, redundant circuits or equipment are not arranged in the DUT area, only one DUT array is used for testing, and the addressable test chip is more similar to the real use scene of the chip. Of course, the addressable test chip capable of improving the resistance measurement accuracy can realize that the device to be tested does not carry out array segmentation, and can also be applicable to the condition that the array to be tested is segmented, and only the addressing circuit of the whole test chip needs to be provided with an array selection decoder for DUT array selection.
As a further improvement, the switch circuit a and/or the switch circuit B respectively include a row switch circuit and a column switch circuit, and the address circuit a and/or the address circuit B respectively include a row address decoder and a column address decoder; the row address decoder is connected with the row switch circuit and controls the row switch circuit to select the row of the device to be tested; the column address decoder is connected with the column switch circuit, and the column address decoder controls the column switch circuit to select the column of the device to be tested.
As a further improvement, the addressing circuit a comprises a plurality of decoders, the switching circuit a comprises a plurality of transmission gates, wherein the plurality of transmission gates form a group, and the input ends of the transmission gates in the same group are connected to the same decoder in the addressing circuit a; the transmission gates are connected into a multi-stage transmission gate structure according to the signal transmission direction, wherein the output end of the transmission gate of the higher stage is connected to the input end of the transmission gate of the lower stage connected with the transmission gate of the higher stage, and the output end of the transmission gate of the lowest stage is connected with the test port of the device to be tested. A switch circuit A in the excitation circuit adopts a multi-stage transmission gate circuit, so that the leakage interference of the unselected DUT to the tested DUT during the circuit measurement can be effectively reduced. The model of each decoder in the addressing circuit a is determined according to the group of transmission gates to which it is connected: the number of the digital signal output bits of the decoder is not less than the number of the transmission gates in the group of transmission gates connected with the decoder.
In the addressable test chip capable of improving the resistance measurement accuracy, the switch circuit A in the excitation circuit is realized by adopting a multi-stage transmission gate structure, and the configuration of each decoder in the addressing circuit A is determined according to the multi-stage transmission gate structure of the switch circuit A. For the excitation circuit and the induction circuit on the periphery of the same DUT array, if the addressing circuit A and the addressing circuit B are respectively configured with one addressing circuit for realization, the switch circuit B in the induction circuit can be realized by a conventional switch circuit or a multi-stage transmission gate structure the same as the switch circuit A; if the addressing circuit A and the addressing circuit B share the same addressing circuit, the switch circuit B in the sensing circuit is also realized by adopting the same multi-stage transmission gate structure as the switch circuit A due to the limitation of the addressing circuit.
As a further improvement, the number of the lower transmission gates connected with each transmission gate in the same group of transmission gates is the same, so that the leakage current of each device to be measured is the same during measurement, and the numerical value precision measured by each device to be measured is the same.
The utility model also provides a can improve resistance measurement accuracy's addressable test system, including test instrument, probe card and the above-mentioned addressable test chip that can improve resistance measurement accuracy, test instrument passes through the probe card with the addressable test chip that can improve resistance measurement accuracy and links to each other and constitute the test access.
The addressable test system capable of improving the resistance measurement precision further comprises a multi-purpose address register, wherein the multi-purpose address register is connected with the test instrument and is also connected with the input end of an addressing circuit in the addressable test chip, and the function of a counter or a shifter can be realized according to the change of an external signal. According to the characteristics of the multipurpose register, when the multipurpose address register has the function of a shift register, the device to be tested can be selectively tested; when the multi-purpose address register has the function of a counter, continuous address signals are generated, and the devices to be tested which need to be tested can be sequentially tested without reading and setting a test algorithm after one device to be tested is tested and before another device to be tested is tested. The multi-purpose address register is a prior art, the multi-purpose address register can realize the function of a counter or a shifter according to the change of an external signal, and the specific structure and the function realization thereof can refer to the content disclosed in the patent document with the publication number of CN 207742296U.
Compared with the prior art, the beneficial effects of the utility model are that:
1. the utility model discloses can improve resistance measurement accuracy's addressable test chip: 1) an induction circuit is added in the test chip and is used as a low-current path for measuring the voltage at two ends of the selected DUT in the low-current induction circuit, so that the voltage drop caused by large current in the excitation circuit is avoided, and the resistance of the DUT is accurately measured; 2) a complete DUT area is adopted on a test chip for testing, a DUT array is not divided, and the purpose of accommodating a complete product for testing is achieved; 3) the switch circuit in the test chip adopts a multi-stage transmission gate, so that the influence of leakage current generated by a branch where the unselected DUT is positioned on the DUT to be tested can be effectively reduced; 4) the method is compatible with the test flow of a common addressable test chip; 5) the method can be used for measuring the test object in the real hot spot product.
2. The utility model discloses can improve resistance measurement accuracy's addressable test system, use the above-mentioned addressable test chip that can improve resistance measurement accuracy, realize the advantage on the same.
Drawings
FIG. 1 is a layout diagram of a conventional high-density test chip.
Fig. 2 is a schematic layout diagram of the test chip of the present invention.
Fig. 3 is a schematic diagram of the structure of the excitation circuit.
Fig. 4 is a schematic structural diagram of the sensing circuit.
Fig. 5 is a schematic diagram of an embodiment of testing a peripheral circuit in a chip according to the present invention.
Fig. 6 is a schematic diagram of an embodiment of a peripheral circuit in the test chip of the present invention.
Detailed Description
The invention will be described in further detail with reference to the following detailed description and accompanying drawings:
as shown in fig. 2, the addressable test chip capable of improving the resistance measurement accuracy includes an excitation circuit, an induction circuit, a plurality of devices to be tested, and a plurality of pads; the device to be tested forms DUT arrays, and a drive circuit and a sensing circuit are respectively arranged on the periphery of each DUT array.
The excitation circuit comprises a switch circuit and an addressing circuit, the addressing circuit is connected with the switch circuit and used for outputting an address signal to control the on-off state of a switch in the switch circuit, and the switch circuit is connected with the device to be tested and used for selecting the specified device to be tested according to the on-off state of the switch; the excitation circuit is used for applying a test voltage to the selected device to be tested.
The induction circuit comprises a switch circuit and an addressing circuit, the addressing circuit is connected with the switch circuit and used for outputting an address signal to control the on-off state of a switch in the switch circuit, and the switch circuit is connected with the device to be tested and used for selecting the appointed device to be tested according to the on-off state of the switch; the induction circuit is used for introducing low current to the selected device to be tested so as to calculate the voltage at two ends of the device to be tested.
As with the excitation circuit shown in fig. 3, the switching circuit is connected to a voltage source via a pad, the voltage source provides the required voltage, and then there will be a voltage on the force line (excitation circuit) as well, but because of the voltage drop, the voltage on the force line and the voltage provided by the voltage source are different.
As shown in the sensing circuit of fig. 4, the switch circuit is connected to the current source through the pad, and the current source provides the smallest possible current, for example, less than 1pA, so that the Source Measurement Unit (SMU) can sense the voltage, and since the current on the sense line is very small, the voltage of the current source is very close to the voltage of the sense line, so that the DUT resistance can be accurately calculated.
The addressable test chip capable of improving the resistance measurement precision is additionally provided with the sensing circuit serving as a low current path, and is used for measuring the voltage at two ends of the selected DUT in the low current sensing circuit so as to accurately measure the resistance of the DUT. In addition, the addressable test chip capable of improving the resistance measurement precision is compatible with a general addressable test chip test flow.
On the addressable test chip capable of improving the resistance measurement precision, all devices to be tested are not subjected to array segmentation, namely all the devices to be tested form a DUT array, and the excitation circuit and the induction circuit are respectively arranged on the periphery of the DUT array. The DUT array is not divided on the test chip, namely no redundant circuit or device exists in the DUT area, and only one DUT array is used for testing, so that the real use scene of the chip is more similar.
The switch circuit comprises a row switch circuit and a column switch circuit, and the addressing circuit comprises a row address decoder and a column address decoder; the row address decoder is connected with the row switch circuit and is used for controlling the row switch circuit to select the row of the device to be tested; the column address decoder is connected with the column switch circuit and is used for controlling the column switch circuit to select the column of the device to be tested. During testing, the row address decoder outputs address signals to control the on-off state of the switches in the row switch circuit, the row where the tested structure is located is selected, the column address decoder outputs address signals to control the on-off state of the switches in the column switch circuit, the column where the tested structure is located is selected, the tested structure is uniquely determined to be conducted, and the test signals can smoothly enter the test structure to be detected.
The switch circuit in the excitation circuit adopts a multi-stage transmission gate circuit, each stage of the multi-stage transmission gate circuit comprises a plurality of transmission gate structures, the input end of a lower stage transmission gate structure is connected to the output end of a higher stage transmission gate structure, and the output end of a lowest stage transmission gate structure is respectively connected with a test signal line of a device to be tested; the input end of each transmission gate structure is also connected with a decoder of an addressing circuit in the excitation circuit, and the input end of the transmission gate structure at the same level is connected with the same decoder.
When the number of DUTs in the DUT array is larger, the configured peripheral circuit has more switching circuits, and according to the principle of addressable testing, only one DUT is selected at each time by each group of testing ports for testing, and the rest unselected switching circuits generate leakage current. In the excitation circuit, the multistage transmission gate circuit is used as the switch circuit, so that the influence of leakage current generated by the branch where the unselected DUT is positioned on the DUT to be tested can be effectively reduced, and the test chip can be ensured to carry out accurate measurement.
In the multi-stage transmission gate circuit, each transmission gate structure of the same stage has the same number of transmission gate structures of the lower stage connected through the decoder. Therefore, the leakage current of each device to be measured is the same during measurement, and the numerical value precision obtained by measurement of each device to be measured is the same.
The addressing circuit in the exciting circuit comprises a plurality of types of decoders, and the type of each decoder is selected according to a multi-level transmission gate circuit: the digital signal output digit number of the decoder is N, the input ends of the K-th transmission gate mechanisms in the multi-stage transmission gate circuits are all connected with the output end of the decoder, and the value of N is not less than the number of the K-th transmission gate structures.
In a specific application, for the same DUT array, because the same device to be tested is selected by the excitation circuit and the sensing circuit, the addressing circuit in the excitation circuit and the addressing circuit in the sensing circuit can be implemented by using the same addressing circuit, that is, the same group of decoders are used to output address signals to the switching circuits in the excitation circuit and the sensing circuit, respectively. Meanwhile, the sharing of the addressing circuit requires that the structures of the switch circuit in the excitation circuit and the switch circuit in the sensing circuit are the same, for example, when the switch circuit in the excitation circuit is implemented by using a multi-stage transmission gate circuit, the switch circuit in the sensing circuit is also implemented by using the same multi-stage transmission gate circuit.
The addressable test system comprises a test instrument, a probe card and the addressable test chip capable of improving the resistance measurement precision, wherein the test instrument and the addressable test chip capable of improving the resistance measurement precision are connected through the probe card to form a test path. According to the addressable test system capable of improving the resistance measurement precision, the sensing circuit is additionally arranged in the test chip, the resistance of a DUT (device under test) can be measured, and the problem of inaccuracy caused by voltage drop in the original test system is solved.
The addressable test system capable of improving the resistance measurement precision further comprises a multi-purpose address register, wherein the multi-purpose address register is connected with the test instrument and is also connected with the input end of an addressing circuit in the addressable test chip, and the function of a counter or a shifter can be realized according to the change of an external signal. According to the characteristics of the multipurpose register, when the multipurpose address register has the function of a shift register, the device to be tested can be selectively tested; when the multi-purpose address register has the function of a counter, continuous address signals are generated, and the devices to be tested which need to be tested can be sequentially tested without reading and setting a test algorithm after one device to be tested is tested and before another device to be tested is tested.
The following examples are presented to enable those skilled in the art to more fully understand the present invention, but are not intended to limit the invention in any way.
Example 1
For a switch circuit currently connecting hundreds of Devices Under Test (DUTs), in order not to divide the DUT array, when the number of DUTs in the DUT array increases to a very large number, for example, 1024 × 1024, i.e., 1 array includes millions of DUTs, the number of DUTs connected by the row switch circuit increases to 1024, and the number of DUTs connected by the column switch circuit increases to 1024, refer to fig. 5.
When 1 complete DUT array was used for testing, the test experiments demonstrated: the voltage drop during the test is mainly affected by the switch circuit, and the embodiment can solve the problem of non-negligible voltage drop under the high voltage test by adding the sensing circuit. Applying a high voltage in the excitation circuit, and measuring the current value flowing through the DUT to be measured; applying a small current in the sensing circuit, and sensing the voltage value at two ends of the DUT to be tested; the resistance value of the DUT to be tested with high precision is further calculated according to the voltage value and the current value.
Example 2
As shown in fig. 6, the switch circuit of the excitation circuit in the addressable test circuit adopts a multi-stage transmission gate circuit (except for the multi-stage transmission gate, the other peripheral circuit structure of the addressable test circuit is similar to that in fig. 5 and is therefore omitted), the circuit structure of the multi-stage transmission gate can effectively reduce the influence of the leakage current on the measurement accuracy during measurement, but when the DUT is tested, compared with the case that only one switch is arranged in the test path in the one-stage switch circuit, the path in which the multi-stage transmission gate structure is arranged contains a plurality of switches connected in series, and the more the stages of the multi-stage transmission gate structure, the greater the influence of the voltage drop on the switches during measurement is, so the addressable test circuit needs to be further configured with a sensing circuit to eliminate the voltage drop caused by the. In FIG. 6, the switching circuits on the left and bottom of the DUT array belong to the drive circuits, and the switching circuits on the right and top of the DUT array belong to the sense circuits. It should be noted that, in this embodiment, the switch circuit in the sensing circuit is also implemented by using a multi-level transmission gate circuit, but the switch circuit in the sensing circuit may use a multi-level transmission gate circuit or a one-level switch circuit according to requirements, and different selections have almost no influence on the sensing precision, and there is no obvious performance and precision improvement.
Next, taking the DUT in the first row and the second column (L1H2) as an example, when a high voltage VH is applied to the bottom switching circuit terminal and a low voltage VL is applied to the left switching circuit terminal, a current from bottom to left is generated; when a low current is applied to the top and right switching circuits, the voltage on the side of the DUT to which a high voltage is applied is sensed to be (VH-IR), wherein IR is the voltage drop on the side to which the high voltage is applied, and similarly, the voltage on the side of the DUT to which a low voltage is applied is sensed to be (VL + IR) by the sensing circuit. In addition, the value of the current flowing through the DUT to be tested is measured by the testing end of the testing chip, namely the value of the current flowing through the DUT to be tested on the excitation circuit, so that the resistance value of the DUT to be tested can be calculated.
Finally, it should be noted that the above-mentioned embodiments illustrate only specific embodiments of the invention. Obviously, the present invention is not limited to the above embodiments, and many variations are possible. All modifications which can be derived or suggested by a person skilled in the art from the disclosure of the invention should be considered as within the scope of the invention.
Claims (7)
1. An addressable test chip capable of improving resistance measurement accuracy is characterized by comprising an excitation circuit, an induction circuit, a plurality of devices to be tested and a plurality of bonding pads; the device to be tested forms DUT arrays, and the periphery of each DUT array is respectively provided with a drive circuit and a sensing circuit;
the excitation circuit comprises a switch circuit A and an addressing circuit A, the addressing circuit A is connected with the switch circuit A, the addressing circuit A outputs an address signal to control the on-off state of a switch in the switch circuit A, the switch circuit A is connected with a device to be tested, and the switch circuit A selects a specified device to be tested through the on-off state of the switch; the excitation circuit is used for applying a test voltage to the selected device to be tested;
the induction circuit comprises a switch circuit B and an addressing circuit B, the addressing circuit B is connected with the switch circuit B, the addressing circuit B outputs an address signal to control the on-off state of a switch in the switch circuit B, the switch circuit B is connected with a device to be tested, and the switch circuit B selects a specified device to be tested through the on-off state of the switch; the induction circuit is used for introducing low current to the selected device to be measured so as to measure the voltage at two ends of the device to be measured; in the excitation circuit and the induction circuit on the periphery of the same DUT array, the addressing circuit A and the addressing circuit B are realized by sharing one addressing circuit, or one addressing circuit is respectively configured for the addressing circuit A and the addressing circuit B.
2. The addressable test chip for improving the accuracy of resistance measurements according to claim 1, wherein all devices under test are distributed in the same DUT array, and the switching circuit and the addressing circuit are disposed at the periphery of the DUT array.
3. The addressable test chip capable of improving the resistance measurement accuracy according to claim 1, wherein the switch circuit a and/or the switch circuit B respectively comprise a row switch circuit and a column switch circuit, and the addressing circuit a and/or the addressing circuit B comprise a row address decoder and a column address decoder; the row address decoder is connected with the row switch circuit and controls the row switch circuit to select the row of the device to be tested; the column address decoder is connected with the column switch circuit, and the column address decoder controls the column switch circuit to select the column of the device to be tested.
4. The addressable test chip capable of improving the resistance measurement accuracy according to claim 1, wherein the addressing circuit a comprises a plurality of decoders, the switching circuit a comprises a plurality of transmission gates, wherein the plurality of transmission gates form a group, and the input ends of the transmission gates in the same group are connected to the same decoder in the addressing circuit a; the transmission gates are connected into a multi-stage transmission gate structure according to the signal transmission direction, wherein the output end of the transmission gate of the higher stage is connected to the input end of the transmission gate of the lower stage connected with the transmission gate of the higher stage, and the output end of the transmission gate of the lowest stage is connected with the test port of the device to be tested.
5. The addressable test chip capable of improving the resistance measurement accuracy according to claim 4, wherein the number of the transmission gates one stage lower connected to each transmission gate in the same group of transmission gates is the same.
6. The addressable test chip capable of improving the resistance measurement accuracy according to claim 4, wherein the model of each decoder in the addressing circuit A is determined according to the connected group of transmission gates: the number of the digital signal output bits of the decoder is not less than the number of the transmission gates in the group of transmission gates connected with the decoder.
7. An addressable test system capable of improving the resistance measurement accuracy, which is characterized by comprising a test instrument, a probe card and the addressable test chip capable of improving the resistance measurement accuracy of any one of claims 1 to 6, wherein the test instrument and the addressable test chip capable of improving the resistance measurement accuracy are connected through the probe card to form a test path.
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US16/377,422 US10725101B2 (en) | 2016-12-30 | 2019-04-08 | Addressable test chip with multiple-stage transmission gates |
| US16/377,471 US10725102B2 (en) | 2016-12-30 | 2019-04-08 | Addressable test chip with sensing circuit |
| PCT/CN2019/126995 WO2020135258A1 (en) | 2018-12-29 | 2019-12-20 | Addressable test chip capable of improving resistance measurement accuracy and test system thereof |
| US16/940,372 US11243251B2 (en) | 2016-12-30 | 2020-07-27 | Addressable test system with address register |
| US17/648,935 US11668748B2 (en) | 2016-12-30 | 2022-01-25 | Addressable test chip |
| US18/328,715 US11959964B2 (en) | 2016-12-30 | 2023-06-02 | Addressable test chip test system |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2018222504536 | 2018-12-29 | ||
| CN201822250453 | 2018-12-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN209979755U true CN209979755U (en) | 2020-01-21 |
Family
ID=69255251
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201920376170.8U Active CN209979755U (en) | 2016-12-30 | 2019-03-22 | Addressable test chip capable of improving resistance measurement precision and test system thereof |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN209979755U (en) |
| WO (1) | WO2020135258A1 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115856588A (en) * | 2023-02-22 | 2023-03-28 | 长鑫存储技术有限公司 | Chip test board and test method |
| CN117686889A (en) * | 2024-01-25 | 2024-03-12 | 杭州广立微电子股份有限公司 | Addressable parallel test circuit, method, chip and system |
| CN117686889B (en) * | 2024-01-25 | 2024-05-14 | 杭州广立微电子股份有限公司 | Addressable parallel test circuit, method, chip and system |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8581610B2 (en) * | 2004-04-21 | 2013-11-12 | Charles A Miller | Method of designing an application specific probe card test system |
| CN101640180B (en) * | 2009-08-31 | 2011-05-04 | 浙江大学 | Test chip for testing defects of production process of semiconductor and manufacturing method thereof |
| US9275187B2 (en) * | 2011-03-21 | 2016-03-01 | Ridgetop Group, Inc. | Programmable test chip, system and method for characterization of integrated circuit fabrication processes |
| US9207278B2 (en) * | 2013-03-22 | 2015-12-08 | Texas Instruments Incorporated | Testing integrated circuit packaging for shorts |
| CN103811468A (en) * | 2013-12-10 | 2014-05-21 | 杭州广立微电子有限公司 | Addressable test chip and test method thereof |
| CN104502830A (en) * | 2014-12-18 | 2015-04-08 | 重庆智锐德科技有限公司 | Chip testing device |
| CN105606948A (en) * | 2016-02-01 | 2016-05-25 | 北京集创北方科技股份有限公司 | Circuit detection method and system |
| CN108267682B (en) * | 2016-12-30 | 2020-07-28 | 杭州广立微电子有限公司 | High-density test chip, test system and test method thereof |
| CN207742296U (en) * | 2017-12-30 | 2018-08-17 | 杭州广立微电子有限公司 | A kind of addressable test chip test system |
-
2019
- 2019-03-22 CN CN201920376170.8U patent/CN209979755U/en active Active
- 2019-12-20 WO PCT/CN2019/126995 patent/WO2020135258A1/en active Application Filing
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115856588A (en) * | 2023-02-22 | 2023-03-28 | 长鑫存储技术有限公司 | Chip test board and test method |
| CN117686889A (en) * | 2024-01-25 | 2024-03-12 | 杭州广立微电子股份有限公司 | Addressable parallel test circuit, method, chip and system |
| CN117686889B (en) * | 2024-01-25 | 2024-05-14 | 杭州广立微电子股份有限公司 | Addressable parallel test circuit, method, chip and system |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2020135258A1 (en) | 2020-07-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10725102B2 (en) | Addressable test chip with sensing circuit | |
| US5418470A (en) | Analog multi-channel probe system | |
| US9053780B2 (en) | Measuring electrical resistance | |
| US6873173B2 (en) | Test circuit arrangement and method for testing a multiplicity of transistors | |
| US7317324B2 (en) | Semiconductor integrated circuit testing device and method | |
| KR100261392B1 (en) | Semiconductor integrated circuit | |
| US6947307B2 (en) | Package map data outputting circuit of semiconductor memory device and method for outputting package map data | |
| CN209979755U (en) | Addressable test chip capable of improving resistance measurement precision and test system thereof | |
| WO2020135257A1 (en) | Addressable test chip and system capable of reducing leakage current | |
| CN107340466B (en) | Analog signal detection system and analog signal detection method | |
| US11243251B2 (en) | Addressable test system with address register | |
| CN113791334A (en) | Switch circuit for addressable test chip and high-density addressable test chip | |
| US7660175B2 (en) | Integrated circuit, method for acquiring data and measurement system | |
| JPH06223596A (en) | Parallel testing circuit | |
| US7126326B2 (en) | Semiconductor device testing apparatus, semiconductor device testing system, and semiconductor device testing method for measuring and trimming the output impedance of driver devices | |
| CN116978810B (en) | On-chip test circuit | |
| US11959964B2 (en) | Addressable test chip test system | |
| CN216718594U (en) | Switch circuit for addressable test chip and high-density addressable test chip | |
| KR20050060902A (en) | Circuit for monitoring of internal voltage drop in chip | |
| KR100437834B1 (en) | Circuit for testing of semiconductor device | |
| CN118033356A (en) | Control circuit module, test circuit and test method | |
| WO2006041598A1 (en) | Direct memory access interface in integrated circuits | |
| JPH0214500A (en) | Semiconductor non-volatile memory device | |
| KR20240052470A (en) | Teg circuit, semiconductor device, and test method of the teg circuit | |
| US7012443B2 (en) | System used to test plurality of DUTs in parallel and method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP01 | Change in the name or title of a patent holder | ||
| CP01 | Change in the name or title of a patent holder |
Address after: Room A407, Neusoft venture building, 99 Huaxing Road, Xihu District, Hangzhou City, Zhejiang Province, 310012 Patentee after: Hangzhou Guangli Microelectronics Co.,Ltd. Address before: Room A407, Neusoft venture building, 99 Huaxing Road, Xihu District, Hangzhou City, Zhejiang Province, 310012 Patentee before: Semitronix Corp. |