CN104502830A - Chip testing device - Google Patents
Chip testing device Download PDFInfo
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- CN104502830A CN104502830A CN201410788096.2A CN201410788096A CN104502830A CN 104502830 A CN104502830 A CN 104502830A CN 201410788096 A CN201410788096 A CN 201410788096A CN 104502830 A CN104502830 A CN 104502830A
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Abstract
The invention discloses a chip testing device, and belongs to the field of electric energy testing devices. The chip testing device specifically comprises a first probe pin, a second probe pin, a row addressing module, a line addressing module, a switch module and a testing module, wherein the first probe pin, the row addressing module and the switch module are sequentially connected, the second probe pin, the line addressing module and the switch module are sequentially connected, the switch module is connected with the testing module, and the switch circuit consists of a single field effect tube. The chip testing device overcomes the defect of risk caused by the additional arrangement of a circuit because of too complicated switch circuit in the existing testing chip.
Description
Technical field
The invention belongs to the proving installation field of electrical property, be specifically related to a kind of apparatus for testing chip.
Background technology
Along with the continuous progress of semiconductor fabrication, device feature size constantly reduces, and integrated level constantly rises.Traditional test chip is connected in probe pins by independent for each test structure.Due to the complicacy of nanometer era IC manufacturing, in manufacturing process, any systematicness, error that is parametric and randomness all likely cause defect, the defect coverage rate that thousands of test structure just can reach certain must be comprised in test chip, the area utilization of traditional test chip design method is quite low, cannot meet this requirement.
The method for designing of conventional addressable test chip at present, all test structures share one group of probe pins by addressing circuit and on-off circuit, solve the problem of area utilization.But the on-off circuit design of this class methods complexity adds the danger that defect occurs circuit itself, disturbs the accurate location of defect.
Summary of the invention
The technical problem to be solved in the present invention is the too complicated defect adding the danger of this province of circuit generation defect of on-off circuit for current test chip, provides a kind of apparatus for testing chip for this reason.
In order to solve the problems of the technologies described above, the present invention adopts following technical scheme:
A kind of apparatus for testing chip, comprise the first probe pins, the second probe pins, row addressed module, row addressed module, switch module and test module, first probe pins, row addressed module are connected successively with switch module, second probe pins, row addressed module are connected successively with switch module, switch module is connected with test module, and described on-off circuit is made up of single field effect transistor, described test module comprises resistance measuring module and electric leakage measurement module, described electric leakage measurement module comprises the first comparer, second comparer, 3rd comparer, photoelectrical coupler and field effect transistor, the negative-phase input of the first comparer is connected with sensing lead, the output terminal of the first comparer is connected with the normal phase input end of the second comparer, the output terminal of the second comparer is connected with the normal phase input end of the 3rd comparer, the positive terminal of photoelectrical coupler is connected with oscillographic output terminal, the emitter terminal of photoelectrical coupler is connected with the grid of field effect transistor, the drain electrode of field effect transistor is connected with the positive terminal of the 3rd comparer, the output terminal of the 3rd comparer is connected with oscillograph.
A kind of apparatus for testing chip of the present invention is adopted to have following technique effect:
Described on-off circuit is made up of single field effect transistor, instead of the logic gate in classic method, simplifies on-off circuit, thus reduces the chance of circuit malfunctions; Electric test signal is provided by the first probe pins; Second probe pins is used for defect location; Row addressing circuit and row addressing circuit are used for the duty of gauge tap circuit; Row addressing circuit is used for opening row selecting switch, row addressing circuit is used for opening column select switch, measured load can be located accurately by row selecting switch and column select switch, simultaneously all test circuits share first probe pins, simplify addressing circuit, optimize area utilization further.After on-off circuit is opened, test module tests corresponding sensing lead.Described test module comprises resistance measuring module and electric leakage measurement module.Resistance measuring module test chip internal driving, the line electrical leakage situation of electric leakage measurement module analysis chip, the measured value of resistance measuring module and electric leakage measurement module has reacted the failure analysis of chip.
Further, also comprise display module, test module is connected with display module.Measured resistance value and electrical leakage are demonstrated by display module by display module, are convenient to staff and observe.
Further, described test module comprises and is located at current transformer and voltage transformer (VT) in each circuit.
Further, described display module is LCD display.
Type selecting for test module and display module is only that concrete practicality is selected, and is convenient to reality and uses.
Accompanying drawing explanation
Fig. 1 is the module map of the embodiment of a kind of apparatus for testing chip of the present invention.
Fig. 2 is the circuit theory diagrams of the electric leakage measurement module of Fig. 1.
Embodiment
Below in conjunction with accompanying drawing, the present invention will be further described:
As shown in Figure 1, apparatus for testing chip of the present invention, specifically comprise: the first probe pins, the second probe pins, row addressed module, row addressed module, switch module and test module, first probe pins, row addressed module are connected successively with switch module, second probe pins, row addressed module are connected successively with switch module, switch module is connected with test module, and described on-off circuit is made up of single field effect transistor.
In specific implementation process, by the first probe pins for test module provides electric test signal, and provide required address interrogation signal for row addressed module and row addressed module.Suppose that selected row address is the third line, column address is the 4th row, and row addressed module produces row selection signal, opens the third line in multiple row selection circuit, and row addressed module produces array selecting signal, opens the 4th row and the 5th row in multiple row on-off circuit.
When selecting resistance measuring module, electric current is flowed into by the first probe pins of the 4th row, and flowed out by first probe pins of voltage table through the 5th row after measuring resistance, the value of read-out voltage table can measure resistance value.
In addition, as shown in Figure 2, electric leakage measurement module comprises the first comparer IC1, second comparer IC2, 3rd comparer IC3, photoelectrical coupler OC and field effect transistor VT, the negative-phase input of the first comparer IC1 is connected with sensing lead, the output terminal of the first comparer IC1 is connected with the normal phase input end of the second comparer IC2, the output terminal of the second comparer IC2 is connected with the normal phase input end of the 3rd comparer IC3, the positive terminal of photoelectrical coupler OC is connected with the output terminal of oscillograph A, the emitter terminal of photoelectrical coupler OC is connected with the grid of field effect transistor VT, the drain electrode of field effect transistor VT is connected with the positive terminal of the 3rd comparer IC3, the output terminal of the 3rd comparer IC3 is connected with oscillograph A.The electric current flowing through test load enters the negative-phase input of the first comparer IC1, export after the amplification of the first comparer IC1, after being kept by the second amplifier IC2 and the 3rd amplifier IC3 peak value again, by the second electric capacity C2 filtering, then oscillograph A is inputted, demonstrate electrical leakage, oscillographic output valve is input to the positive terminal of photoelectrical coupler OC, make the lumination of light emitting diode of its inside, thus make the phototriode conducting of its inside, field effect transistor VT conducting, electric current flows into ground, and electric leakage measurement module numerical value resets.
Moreover, chip testing protective device of the present invention comprises: Dynamic Signal Generator, Dynamic Signal comparer, test press welding block, metal wire, control circuit and warning circuit, Dynamic Signal Generator, Dynamic Signal comparer, control circuit and warning circuit are positioned at chip, chip side is provided with scribe line, metal wire is positioned at scribe line Inner, Dynamic Signal Generator branch road is connected with Dynamic Signal comparer, another branch road is connected with Dynamic Signal comparer by metal wire, test press welding block branch road is connected with control circuit by metal wire, another branch road is connected with warning circuit by metal wire, Dynamic Signal comparer branch road is connected with control circuit, another branch road is connected with warning circuit.Dynamic Signal Generator produces the first identical Dynamic Signal of characteristics of signals and the second Dynamic Signal, first Dynamic Signal is input in Dynamic Signal comparer by the metal wire in scribe line, second Dynamic Signal is directly inputted in Dynamic Signal comparer, Dynamic Signal comparer compares to the received signal, if identical just by the flat input control circuit of electric for height SS, if not identical, send alerting signal with regard to trigger alarm circuit; Meanwhile, test press welding block produces external test mode enable signal, be input in control circuit by metal wire, if control circuit does not receive external test mode enable signal, then control warning circuit and send alerting signal, if control circuit receives external test mode enable signal and Dynamic Signal comparer exports high level to control circuit, then control circuit exports internal test mode enable signal, and chip enters test pattern.When chip is separated from wafer, scribe line is separated with chip, make the Dynamic Signal Generator in metal wire and chip, Dynamic Signal comparer and control circuit disconnect, make Dynamic Signal comparer cannot export high level in control circuit, thus control circuit cannot export internal test mode enable signal, chip cannot enter test pattern, more in the quantity of the metal wire of chip edge, spacing simultaneously between metal wire can be very little, this considerably increases difficulty and the complexity of FIB reconstruction metal wire, substantially increase the difficulty that assailant enters the test pattern of chip, thus greatly improve the security of chip.
Described test module comprises is located at current transformer and voltage transformer (VT) in each circuit.Described display module is LCD display.
For a person skilled in the art, under the prerequisite not departing from structure of the present invention, can also make some distortion and improvement, these also should be considered as protection scope of the present invention, and these all can not affect effect of the invention process and practical applicability.
Claims (4)
1. an apparatus for testing chip, it is characterized in that: comprise the first probe pins, the second probe pins, row addressed module, row addressed module, switch module and test module, first probe pins, row addressed module are connected successively with switch module, second probe pins, row addressed module are connected successively with switch module, switch module is connected with test module, and described on-off circuit is made up of single field effect transistor, described test module comprises resistance measuring module and electric leakage measurement module, described electric leakage measurement module comprises the first comparer, second comparer, 3rd comparer, photoelectrical coupler and field effect transistor, the negative-phase input of the first comparer is connected with sensing lead, the output terminal of the first comparer is connected with the normal phase input end of the second comparer, the output terminal of the second comparer is connected with the normal phase input end of the 3rd comparer, the positive terminal of photoelectrical coupler is connected with oscillographic output terminal, the emitter terminal of photoelectrical coupler is connected with the grid of field effect transistor, the drain electrode of field effect transistor is connected with the positive terminal of the 3rd comparer, the output terminal of the 3rd comparer is connected with oscillograph.
2. apparatus for testing chip as claimed in claim 1, it is characterized in that: also comprise display module, test module is connected with display module.
3. apparatus for testing chip as claimed in claim 2, is characterized in that: described test module comprises is located at current transformer and voltage transformer (VT) in each circuit.
4. apparatus for testing chip as claimed in claim 2 or claim 3, is characterized in that: described display module is LCD display.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410788096.2A CN104502830A (en) | 2014-12-18 | 2014-12-18 | Chip testing device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410788096.2A CN104502830A (en) | 2014-12-18 | 2014-12-18 | Chip testing device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104502830A true CN104502830A (en) | 2015-04-08 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410788096.2A Pending CN104502830A (en) | 2014-12-18 | 2014-12-18 | Chip testing device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107861047A (en) * | 2017-11-01 | 2018-03-30 | 北京智芯微电子科技有限公司 | The detecting system and detection method of safety test pattern |
| WO2020135258A1 (en) * | 2018-12-29 | 2020-07-02 | 杭州广立微电子有限公司 | Addressable test chip capable of improving resistance measurement accuracy and test system thereof |
| CN116879723A (en) * | 2023-09-04 | 2023-10-13 | 上海灵动微电子股份有限公司 | Universal chip test board |
-
2014
- 2014-12-18 CN CN201410788096.2A patent/CN104502830A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107861047A (en) * | 2017-11-01 | 2018-03-30 | 北京智芯微电子科技有限公司 | The detecting system and detection method of safety test pattern |
| WO2020135258A1 (en) * | 2018-12-29 | 2020-07-02 | 杭州广立微电子有限公司 | Addressable test chip capable of improving resistance measurement accuracy and test system thereof |
| CN116879723A (en) * | 2023-09-04 | 2023-10-13 | 上海灵动微电子股份有限公司 | Universal chip test board |
| CN116879723B (en) * | 2023-09-04 | 2023-11-21 | 上海灵动微电子股份有限公司 | Universal chip test board |
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| PB01 | Publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20150408 |
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| WD01 | Invention patent application deemed withdrawn after publication |