CN112014604A - Wafer testing device, testing system and testing method - Google Patents
Wafer testing device, testing system and testing method Download PDFInfo
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- CN112014604A CN112014604A CN201910452209.4A CN201910452209A CN112014604A CN 112014604 A CN112014604 A CN 112014604A CN 201910452209 A CN201910452209 A CN 201910452209A CN 112014604 A CN112014604 A CN 112014604A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/06—Measuring leads; Measuring probes
- G01R1/067—Measuring probes
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
- G01R31/2889—Interfaces, e.g. between probe and tester
Abstract
The embodiment of the invention relates to the technical field of testing, and discloses a wafer testing device, a wafer testing system and a wafer testing method. The invention provides a wafer testing device, comprising: the wafer test card comprises a plurality of electrode probes and at least one signal path connected with the wafer test card, wherein at least two electrode probes share one signal path; at least one signal path for providing a test electrical signal to the plurality of electrode probes; the electrode probes are used for connecting the chip to be tested on the wafer to be tested and testing the chip to be tested by utilizing the test electric signal. The wafer testing device, the wafer testing system and the wafer testing method provided by the embodiment of the invention can reduce the cost of the testing device.
Description
Technical Field
The embodiment of the invention relates to the technical field of testing, in particular to a wafer testing device, a wafer testing system and a wafer testing method.
Background
Generally, electronic devices manufactured by wafer processes must be tested electrically at a specific process stage, including a package test after the process is completed or a quality test before modularization, and under the situation that industry competition is more and more intense, each wafer manufacturer puts more emphasis on a high-efficiency wafer level test method. In the existing wafer testing method, a probe card is generally arranged on a wafer to be tested, each probe on the probe card is correspondingly provided with a signal path, and the whole chip on the wafer to be tested is tested by moving the probe card.
However, the inventors found that at least the following problems exist in the prior art: in the conventional test device, a probe card generally comprises a plurality of probes, and a signal path is correspondingly arranged for each probe, so that the test device has higher cost.
Disclosure of Invention
An object of embodiments of the present invention is to provide a wafer testing apparatus, a wafer testing system, and a wafer testing method, which can reduce the cost of the wafer testing apparatus.
In order to solve the above technical problem, an embodiment of the present invention provides a wafer testing apparatus, including: the wafer test card comprises a plurality of electrode probes and at least one signal path connected with the wafer test card, wherein at least two electrode probes share one signal path; at least one signal path for providing a test electrical signal to the plurality of electrode probes; the electrode probes are used for connecting the chip to be tested on the wafer to be tested and testing the chip to be tested by utilizing the test electric signal.
An embodiment of the present invention further provides a wafer testing system, including: the signal output device is connected with the wafer testing device; the signal output device is used for providing a test electrical signal for the wafer test device; the wafer testing device tests the wafer to be tested by utilizing the test electric signal.
The embodiment of the invention also provides a wafer testing method, which is applied to the wafer testing device, and the wafer testing method comprises the following steps: connecting a plurality of electrode probes with a chip to be tested on a wafer to be tested; a test electrical signal is provided to the plurality of electrode probes via the at least one signal path.
Compared with the prior art, the embodiment of the invention provides a testing device, which comprises: the wafer test card comprises a plurality of electrode probes and at least one signal path connected with the wafer test card, wherein at least two electrode probes share one signal path; at least one signal path for providing a test electrical signal to the plurality of electrode probes; the electrode probes are used for connecting the chip to be tested on the wafer to be tested and testing the chip to be tested by utilizing the test electric signal. In the embodiment of the invention, at least two electrode probes share one signal path, the at least one signal path provides test electric signals for the plurality of electrode probes on the wafer test card, and the number of the signal paths is less than that of the electrode probes of the wafer test card, so that the situation that one signal path is arranged for each electrode probe is avoided, and the cost of the test device is reduced.
In addition, the number of the electrode probes is less than that of the chips to be detected; preferably, the electrode probes on the wafer test card are arranged in an array. In the scheme, the chips to be tested on the wafer to be tested are usually arranged in an array mode, so that the electrode probes are arranged in the array mode, and testing is facilitated for testers.
In addition, the number of the electrode probes is equal to that of the chips to be tested, and the arrangement mode of the electrode probes on the wafer test card is the same as that of the chips to be tested on the wafer to be tested. When the wafer to be tested is tested in the scheme, all the electrode probes on the wafer test card can be aligned to all the chips to be tested on the wafer to be tested only by one-time alignment, so that the test time is greatly saved.
In addition, the wafer test card comprises a plurality of test units, each test unit at least comprises two electrode probes, the number of the electrode probes of each test unit is the same, and the number of the signal paths is the same as that of the electrode probes of each test unit; the signal path provides a test electrical signal to the electrode probe of each test cell. The test unit that provides the test signal of telecommunication through the switching of signal access in this scheme can accomplish the test, has reduced the time of every removal and the error that the counterpoint caused between the electrode greatly, has improved efficiency of software testing.
In addition, the wafer to be tested comprises a common first electrode, and each chip to be tested on the wafer to be tested comprises an independent second electrode; the plurality of electrode probes comprise a first electrode probe and a plurality of second electrode probes; the first electrode probe is used for connecting a common first electrode of the wafer to be tested, and the second electrode probe is used for connecting a second electrode of the chip to be tested.
In addition, the part of the electrode probe used for connecting the chip to be tested is a conductive elastic part. The part that is used for connecting the chip that awaits measuring with the electrode probe in this scheme carries out the test sets up to electrically conductive elasticity portion for testing personnel can cushion partial component in order to avoid causing the damage to the chip that awaits measuring when testing.
In addition, the wafer test system further includes: the camera device is connected with the signal output device; the camera device is used for obtaining a test picture when the wafer testing device tests the wafer to be tested when the signal output device provides a test electric signal for the wafer testing device.
Drawings
One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the figures in which like reference numerals refer to similar elements and which are not to scale unless otherwise specified.
FIG. 1 is a schematic structural diagram of a wafer testing apparatus according to a first embodiment of the present invention;
FIG. 2 is a schematic structural diagram of a wafer testing apparatus according to a first embodiment of the present invention;
FIG. 3 is a schematic structural diagram of a wafer test system according to a second embodiment of the present invention;
fig. 4 is a flowchart illustrating a wafer testing method according to a third embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention more apparent, embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, it will be appreciated by those of ordinary skill in the art that numerous technical details are set forth in order to provide a better understanding of the present application in various embodiments of the present invention. However, the technical solution claimed in the present application can be implemented without these technical details and various changes and modifications based on the following embodiments.
A first embodiment of the present invention relates to a wafer test apparatus, and as shown in fig. 1 and 2, the core of the present embodiment is to provide a test apparatus 1 including: the wafer test card 11 comprises a plurality of electrode probes 110, and at least one signal path 12 connected with the wafer test card 11, wherein at least two electrode probes 110 share one signal path 12; at least one signal path 12 for providing test electrical signals to the plurality of electrode probes 110; the electrode probes 110 are used for connecting the chips 30 to be tested on the wafer 3 to be tested, and testing the chips 30 to be tested by using the test electrical signals. In the embodiment of the present invention, at least two electrode probes 110 share one signal path 12, and the at least one signal path 12 provides a test electrical signal for the plurality of electrode probes 110 on the wafer test card 11, and the number of the signal paths 12 is smaller than the number of the electrode probes 110 on the wafer test card 11, thereby avoiding the need to provide one signal path 12 for each electrode probe 110, and reducing the cost of the test apparatus.
The following describes the details of the wafer testing apparatus of the present embodiment in detail, and the following is only provided for the convenience of understanding and is not necessary to implement the present embodiment.
As an implementation, as shown in fig. 1, the number of electrode probes 110 is less than the number of chips 30 to be tested; preferably, the electrode probes 110 on the wafer test card 11 are arranged in an array.
Specifically, the number of the electrode probes 110 on the wafer test card 11 is smaller than the number of the chips 30 to be tested, when the wafer 3 to be tested is tested, the wafer test card 11 is moved so that the electrode probes 110 are aligned with part of the chips 30 to be tested on the chip 3 to be tested, because the number of the signal paths 12 is smaller than the number of the electrode probes 110 on the wafer test card 11, and at least one signal path 12 connected to the wafer test card 11 can only provide test electrical signals for the electrode probes 110 equal to or smaller than the number of the signal paths, the signal paths 12 are required to switch the electrode probes 110 providing the test electrical signals, so that the test electrical signals are provided for the plurality of electrode probes 110, and the test of the part of the chips 30 to be tested on the wafer 3 to be tested is realized. The electrode probes 110 and the chips 30 to be tested on the wafer 3 to be tested are subjected to multiple alignment tests by moving the wafer test card 11, so that the chips 30 to be tested on the whole wafer 3 to be tested are tested. Preferably, the electrode probes 110 on the wafer test card 11 are arranged in an array, and since the chips 30 to be tested on the wafer 3 to be tested are usually arranged in an array, the electrode probes 110 are arranged in an array, which is beneficial for the tester to test.
It should be noted that, in general, all the chips 30 to be tested on the wafer 3 have independent first electrodes and second electrodes, in this case, the distance between two adjacent electrode probes 110 on the wafer test card 11 is the same as the distance between the first electrode and the second electrode of the chip 30 to be tested on the wafer 3, so that when the electrode probes 110 on the wafer test card 11 are aligned with the chips 30 to be tested, the first electrodes and the second electrodes of the chips 30 to be tested can be aligned at the same time, thereby implementing the test on the chips 30 to be tested. However, in this way, the distance between the two electrode probes 110 testing the same chip 30 to be tested is too close, which is likely to cause short circuit.
In order to avoid short circuit caused by too close distance between two adjacent electrode probes 110 for testing the same chip 30 to be tested, in this embodiment, the first electrodes of all the chips 30 to be tested on the wafer 3 to be tested are connected to form a common first electrode, and the second electrodes of the chips 30 to be tested are independent of each other. Therefore, in this embodiment, only one first electrode probe 1101 connected to the first electrode of the chip 30 to be tested and one second electrode probe 1102 connected to the second electrode of the chip 30 to be tested are needed, so that during testing, the common first electrode is led out by connecting one first electrode probe 1101 to connect the first electrodes of all the chips 30 to be tested, and the testing can be realized by only correspondingly connecting one second electrode probe 1102 to one chip 30 to be tested, thereby avoiding the short circuit caused by the proximity of two adjacent electrode probes 110, and improving the safety of the testing process.
Preferably, the first electrode probes 1101 may be independent from the second electrode probes 1102, and during testing, the fixed positions of the first electrode probes 1101 connected to the wafer 3 to be tested do not move, the second electrode probes 1102 are arranged in an array manner, and the second electrode probes are moved to test all the chips 30 to be tested on the entire wafer 3 to be tested.
As another implementation, as shown in fig. 2, the number of the electrode probes 110 is equal to the number of the chips 30 to be tested, and the arrangement of the electrode probes 110 on the wafer test card 11 is the same as the arrangement of the chips 30 to be tested on the wafer 3 to be tested.
Specifically, the number of the electrode probes 110 on the wafer test card 11 is equal to the number of the chips 30 to be tested, and the arrangement is the same, so that when the wafer 3 to be tested is tested, all the electrode probes 110 on the wafer test card 11 can be aligned to all the chips 30 to be tested on the wafer 3 to be tested only by one-time alignment, and the test time is greatly saved. Since the number of the signal paths 12 is less than the number of the electrode probes 110 of the wafer test card 11, and at least one of the signal paths 12 connected to the wafer test card 11 can only provide the test electrical signals for the electrode probes 110 whose number is equal to or less than the number of the signal path 12, the signal path 12 is required to switch the electrode probes 110 providing the test electrical signals, so as to provide the test electrical signals for all the electrode probes 110 on the wafer test card 11 to test all the chips 30 to be tested on the wafer 3.
It should be noted that, in general, all the chips 30 to be tested on the wafer 3 have independent first electrodes and second electrodes, in this case, the distance between two adjacent electrode probes 110 on the wafer test card 11 is the same as the distance between the first electrode and the second electrode of the chip 30 to be tested on the wafer 3, so that when the electrode probes 110 on the wafer test card 11 are aligned with the chips 30 to be tested, the first electrodes and the second electrodes of the chips 30 to be tested can be aligned at the same time, thereby implementing the test on the chips 30 to be tested. However, in this way, the distance between the two electrode probes 110 testing the same chip 30 to be tested is too close, which is likely to cause short circuit.
In order to avoid short circuit caused by too close distance between two adjacent electrode probes 110 for testing the same chip 30 to be tested, in this embodiment, the first electrodes on all the chips 30 to be tested on the wafer 3 to be tested are connected to form a common first electrode, and the second electrodes of the chips 30 to be tested are independent of each other. Therefore, in this embodiment, only one first electrode probe 1101 connected to the first electrode of the chip 30 to be tested and one second electrode probe 1102 connected to the second electrode of the chip 30 to be tested are needed, so that during testing, one first electrode probe 1101 is connected to the led-out common first electrode to connect the first electrodes of all the chips 30 to be tested, and the chip 30 to be tested can be tested only by connecting one second electrode probe 1102, thereby avoiding the short circuit caused by the proximity of two adjacent electrode probes 110, and improving the safety of the testing process.
It should be noted that, in the wafer test card 11 shown in fig. 2, since the number of the electrode probes 110 is the same as that of the chips 30 to be tested on the wafer 3 to be tested, the electrode probes 110 are arranged in a micro-convex shape, so as to prevent the electrode probes 110 from being too long and short-circuiting when the signal paths 12 provide electrical signals for the electrode probes 110. For the wafer 3 to be tested having the common first electrode, since the first electrode is shared, the first electrode probe 1101 can be disposed beside any second electrode (not shown in the figure), and when the first electrode probe 1101 is connected to the chip 30 to be tested corresponding to the position of the first electrode probe 1101, the connection of the first electrode of the chip 30 to be tested on the entire wafer 3 to be tested is realized.
Further, the wafer test card 11 includes a plurality of test units, each of the test units at least includes two electrode probes 110, and the number of the electrode probes 110 of each of the test units is the same, and the number of the signal paths 12 is the same as the number of the electrode probes 110 of each of the test units; the signal path 12 provides a test electrical signal to the electrode probe 110 of each test cell.
Specifically, in fig. 2, since the number of the electrode probes 110 is equal to the number of the chips 30 to be tested, and the arrangement of the electrode probes 110 on the wafer test card 11 is the same as the arrangement of the chips 30 to be tested on the wafer 3 to be tested, the wafer test card 11 only needs to be precisely aligned once. The test card includes at least two electrode probes 110 as a test unit (for example, every 1000 electrode probes 110 are a test unit), and the test unit providing test electrical signals through the switching 12 of the signal path can complete the test, thereby greatly reducing the time of each movement and the error caused by the alignment between the electrodes, and greatly improving the test efficiency.
Further, the portion of the electrode probe 110 for connecting to the chip 30 to be tested is a conductive elastic portion.
Specifically, the portion of the electrode probe 110 for connecting the chip 30 to be tested to the test is set as a conductive elastic portion, so that a part of the force can be buffered to avoid damage to the chip 30 to be tested when a tester performs a test. In an implementation manner, the electrode probe 110 is provided with a spring at a position for connecting with the chip 30 to be tested, and the front end material of the spring is a slightly soft material such as Polydimethylsiloxane (PDMS) so as to avoid the problem of insufficient chip warpage contact.
It should be noted that, in the present embodiment, the wafer 3 to be tested may be a Micro-LED wafer, the chip 30 to be tested is a Micro-LED, the first electrode common to the chips 30 to be tested is usually an N electrode, and the independent second electrode is a P electrode.
Compared with the prior art, the embodiment of the invention provides a wafer test device, at least two electrode probes 110 share one signal path 12, test electrical signals are provided for a plurality of electrode probes 110 on a wafer test card 11 through at least one signal path 12, the number of the signal paths 12 is smaller than that of the electrode probes 110 of the wafer test card 11, and one signal path 12 is not provided for each electrode probe 110, so that the cost of the test device is reduced.
A second embodiment of the present invention relates to a wafer test system, as shown in fig. 3, including: like the wafer test apparatus 1 and the signal output apparatus 2 of the first embodiment, the signal output apparatus 2 is connected to the wafer test apparatus 1; the signal output device 2 is used for providing a test electrical signal for the wafer test device 1; the wafer testing apparatus 1 tests the wafer 3 to be tested by using the test electrical signal.
The wafer test system further comprises: the image pickup device 4, the image pickup device 4 connects the signal output device 2; the camera device 4 is used for acquiring a test picture when the wafer testing device 1 tests the wafer 3 to be tested when the signal output device 2 provides a test electrical signal for the wafer testing device 1.
The following describes a method for using the wafer test system with a wafer 30Micro-LED wafer to be tested:
the wafer with the patterned Micro-LEDs in the horizontal structure is placed on a carrying platform of the system, then the wafer with the patterned Micro-LEDs is slowly moved upwards, the electrode probe 110 on the wafer test card 11 is accurately contacted with the P/N electrode of each Micro-LED on the wafer through the high-precision automatic alignment system, and meanwhile, the camera device 4 positioned below the wafer 30 to be tested is aligned with the Micro-LEDs contacted with the electrode probes. The signal output device 2 loads the test electrical signals to the wafer test device 1, and monitors and outputs the test electrical signal result of each Micro-LED and the brightness graph of the Micro-LED at the corresponding position. The test electrical signals output by the signal output device 2 vary according to different test items, and include a rated forward current, a rated reverse voltage, an electrostatic discharge (ESD) signal, and the like.
Compared with the prior art, the embodiment of the invention provides a wafer test system, which comprises: like the wafer test apparatus 1 and the signal output apparatus 2 of the first embodiment, the signal output apparatus 2 is connected to the wafer test apparatus 1; the signal output device 2 is used for providing a test electrical signal for the wafer test device 1; the wafer testing device 1 tests the wafer 3 to be tested by using the test electrical signal, and provides a low-cost implementation mode of a wafer testing system.
A third embodiment of the present invention relates to a wafer testing method, and the wafer testing method in this embodiment is as shown in fig. 4, and specifically includes:
step 101: and connecting the electrode probes with the chip to be tested on the wafer to be tested.
Specifically, if the number of the electrode probes is smaller than that of the chips to be tested on the wafer to be tested, the electrode probes on the wafer test card are aligned to part of the chips to be tested on the wafer to be tested during testing. After the part of the chips to be tested are tested, the wafer test card is moved to carry out multiple alignment tests on the electrode probes and the chips to be tested on the wafer to be tested, so that the chips to be tested on the whole wafer to be tested are tested. Preferably, the electrode probes include a first electrode probe and a second electrode probe, so that during actual alignment, only the second electrode probe needs to be aligned with a chip to be tested on the wafer to be tested. If the number of the electrode probes is equal to that of the chips to be tested on the wafer to be tested, the chips to be tested on the whole wafer to be tested can be tested only by once accurate alignment without multiple times of alignment.
Step 102: a test electrical signal is provided to the plurality of electrode probes via the at least one signal path.
Specifically, at least two electrode probes share one signal path, which indicates that the number of the signal paths is less than that of the electrode probes of the wafer test card, and at least one signal path connected with the wafer test card can only provide test electrical signals for the electrode probes equal to or less than the number of the signal paths, so that the signal paths are required to be switched to provide the electrode probes of the test electrical signals, and the electrode probes of the test electrical signals are provided by switching the signal paths, so that the test electrical signals are provided for all the electrode probes to test the chip to be tested.
Providing test electrical signals to the plurality of electrode probes via at least one signal path, specifically: the electrode probes of each test cell are provided with test electrical signals via the signal paths. Specifically, since the number of the electrode probes is equal to the number of the chips to be tested, and the arrangement mode of the electrode probes on the wafer test card is the same as that of the chips to be tested on the wafer to be tested, the wafer test card only needs to be aligned accurately once. The test card internally comprises at least two electrode probes as one test unit (for example, every 1000 electrode probes are one test unit), the test unit which provides test electric signals through the switching of signal paths can complete the test, and the signal paths sequentially provide test electric signals for the electrode probes, namely the test units, with the same number, so that the time of each movement and the errors caused by the alignment between the electrodes are greatly reduced, and the test efficiency is greatly improved.
Compared with the prior art, the embodiment of the invention provides a wafer testing method, which is applied to the wafer testing device in the first embodiment, and the wafer testing method comprises the following steps: connecting a plurality of electrode probes with a chip to be tested on a wafer to be tested; a test electrical signal is provided to the plurality of electrode probes via the at least one signal path. The scheme provides a test method for testing the wafer to be tested by using the low-cost wafer test device.
It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples for carrying out the invention, and that various changes in form and details may be made therein without departing from the spirit and scope of the invention in practice.
Claims (10)
1. A wafer test apparatus, comprising: the wafer test card comprises a plurality of electrode probes and at least one signal path connected with the wafer test card, wherein at least two electrode probes share one signal path;
the at least one signal path is used for providing test electrical signals for the plurality of electrode probes;
the electrode probes are used for connecting a chip to be tested on a wafer to be tested and testing the chip to be tested by utilizing the test electric signal.
2. The wafer test apparatus according to claim 1, wherein the number of the electrode probes is smaller than the number of the chips to be tested; preferably, the electrode probes on the wafer test card are arranged in an array manner.
3. The wafer test device as claimed in claim 1, wherein the number of the electrode probes is equal to the number of the chips to be tested, and the arrangement of the electrode probes on the wafer test card is the same as the arrangement of the chips to be tested on the wafer to be tested.
4. The wafer test apparatus as claimed in claim 3, wherein the wafer test card comprises a plurality of test units, each of the test units comprises at least two electrode probes, and the number of the electrode probes of each of the test units is the same, and the number of the signal paths is the same as the number of the electrode probes of each of the test units;
the signal path provides a test electrical signal for the electrode probe of each of the test cells.
5. The wafer test device as claimed in claim 1, wherein the wafer to be tested includes a common first electrode, and each of the chips to be tested on the wafer to be tested includes an independent second electrode; the plurality of electrode probes comprise a first electrode probe and a plurality of second electrode probes;
the first electrode probe is used for connecting a public first electrode of the wafer to be tested, and the second electrode probe is used for connecting a second electrode of the chip to be tested.
6. The wafer testing device as claimed in claim 1, wherein the portion of the electrode probe for connecting the chip to be tested is a conductive elastic portion.
7. A wafer test system, comprising: the wafer test device as claimed in any one of claims 1 to 6, and a signal output device connected to the wafer test device;
the signal output device is used for providing a test electric signal for the wafer test device;
the wafer testing device tests the wafer to be tested by using the test electric signal.
8. The wafer test system of claim 7, further comprising: the camera device is connected with the signal output device;
the camera device is used for acquiring a test picture when the wafer testing device tests a wafer to be tested when the signal output device provides a test electric signal for the wafer testing device.
9. A wafer testing method applied to the wafer testing apparatus as claimed in any one of claims 1 to 6, the wafer testing method comprising:
connecting a plurality of electrode probes with a chip to be tested on a wafer to be tested;
providing test electrical signals to the plurality of electrode probes via the at least one signal path.
10. The wafer testing method as claimed in claim 9, applied to the wafer testing apparatus as claimed in claim 4, wherein the providing of the test electrical signals to the plurality of electrode probes via the at least one signal path includes: providing a test electrical signal to the electrode probe of each of the test cells via the signal path.
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| CN113539870A (en) * | 2021-06-24 | 2021-10-22 | 浙江大学绍兴微电子研究中心 | Method for testing electrical characteristics of a switching device on a wafer |
| CN113484560A (en) * | 2021-07-07 | 2021-10-08 | 上海泽丰半导体科技有限公司 | Wafer and finished product test shared circuit board and design method thereof |
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