CN103094142A - Special wafer layout configuration method used for detecting probe card and manufacture of wafer - Google Patents
Special wafer layout configuration method used for detecting probe card and manufacture of wafer Download PDFInfo
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- CN103094142A CN103094142A CN2011103441939A CN201110344193A CN103094142A CN 103094142 A CN103094142 A CN 103094142A CN 2011103441939 A CN2011103441939 A CN 2011103441939A CN 201110344193 A CN201110344193 A CN 201110344193A CN 103094142 A CN103094142 A CN 103094142A
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Abstract
The invention discloses a special wafer layout configuration method used for detecting a probe card and manufacture of a wafer. The configuration method comprises that (1) the number of products needed to be achieved on the wafer is defined; (2) the wafer is divided into areas which are corresponding to the number of the products according to the number of the products, and an IO PAD array of a product is produced in each area to form a special wafer pattern. The manufacture of the wafer comprises that (1) the special wafer pattern is formed according to a special wafer layout configuration method; (2) production of different products is carried out according to different areas of the wafer pattern, so that the special wafer which contains different products is obtained. By means of the special wafer layout configuration method used for detecting the probe card and manufacture of the wafer, the probe card can be detected and analyzed effectively, the using efficiency of a special detecting wafer is improved and cost is reduced.
Description
Technical field
The present invention relates to a kind of method of detector probe card of the wafer sort for large scale integrated circuit, particularly relate to a kind of special wafer domain arrangement method for detection of probe and the making of wafer thereof.
Background technology
One is in carrying out the volume production test process of wafer, all need by probe, the signal of measuring head output to be sent to the pad (PAD) of tested chip on wafer, thereby add correct excitation to seal on chip, tester is given in the response of receiving chip simultaneously (i.e. output), judge correcting errors of chip testing result in tester, thereby judge whether chip is non-defective unit.
Can be found out by above-mentioned, as the important physical structure of a signal route, the performance of probe is apparent on the impact of test result.Particularly extensive same the survey, such as 128 chips are tested simultaneously, or in 512 chips process of testing simultaneously, thousands of probes have often been made on one piece of probe, in the volume production process, as long as when having a probe to come in contact bad characteristic, all can cause producing the phenomenon of certain chip under test solid failure, produced and killed, directly reduced the yield of product.
For probe is carried out regular analysis and processing, need to analyze the characteristic of probe with a kind of special-purpose wafer that is different from volume production, to avoid the restriction of pricking times.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of special wafer domain arrangement method for detection of probe and the making of wafer thereof, can make special wafer by the method, and the problem of probe itself is analyzed fast.
For solving the problems of the technologies described above, the special wafer domain arrangement method for detection of probe of the present invention comprises:
(1) define the number of the product that need to realize on wafer;
(2) according to the product number, wafer is divided into the zone corresponding with the product number, namely make the IO PAD array (I/O unit) of a product in each zone, form special wafer figure.
The number of described step (1) is one or more products.
In described step (2), the product the when framework of PAD array and volume production is in full accord.
In addition, the present invention also discloses a kind of manufacture method of the special wafer for detection of probe, comprising:
(1) according to above-mentioned special wafer domain arrangement method, form special wafer figure;
(2) carry out the production of different product according to the zones of different of wafer figure, obtain to contain one piece of special wafer of different product.
In described step (2), the term harmonization the when metal ingredient of the mask plate that uses in the wafer production process and the Fabrication parameter of the PAD term harmonization, particularly PAD during all with volume production and technological parameter and volume production, and with complete the working it out of PAD; Wherein, the chip circuit of wafer only needs top metal (top-level metallic) to get final product.
The present invention carries out regular analysis and processing by this special special-purpose wafer to probe, effectively quantizes to the contact performance to probe, thereby finds an effective pin pressure amount, instructs volume production.Simultaneously, can be fast the probe of loose contact in probe be positioned and analyzes, and avoid the restriction of pricking times on the volume production wafer.Therefore, the present invention can allow the supervisor of construction under the prerequisite that breaks away from the volume production wafer, can effectively check and analyze probe, has improved the utilization rate of dedicated test wafer, has reduced cost.
Description of drawings
The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment:
Accompanying drawing is the schematic diagram that is divided into the wafer area corresponding with 4 products.
Embodiment
Special wafer domain arrangement method for detection of probe of the present invention comprises:
(1) define the number of the product that need to realize on wafer, a minimum product, N products at most realized;
(2) according to the product number, wafer is divided into the zone corresponding with the product number, there is no special appointment on the physical location that is chosen in wafer in zone, size is changeable, can the garden.But in order to improve verification efficiency, preferably each zone is all done orthogonal or square.
When the simplest method is each regional profile of definition, the existing physical behavior of directly using wafer.As only dividing four when regional, wafer can be divided into four sector regions; In each zone, the IO PAD array of a product of regular production, make special wafer figure.As in this four products, the PAD arrangement mode of product A is that four PAD of inclination proterties arrange, and can be covered with oblique row's PAD in zone 1; The PAD of product B is arranging of four PAD of row, is covered with smooth vertical and horizontal PAD and arranges in zone 2, and like this, each product is next corresponding with the wafer area of a quadrant, as shown in Figure of description.Wherein, the product the when framework of PAD array and volume production is in full accord.
According to above-mentioned special wafer domain arrangement method, can be made into a kind of special wafer for detection of probe, concrete steps comprise:
(1) according to above-mentioned special wafer domain arrangement method, form special wafer figure;
(2) carry out the production of different product according to the zones of different of wafer figure, obtain to contain at last one piece of special wafer of different product.
Wherein, the mask plate that uses in the wafer production process and the Fabrication parameter of PAD all with the term harmonization of volume production, mask plate is in the volume production process makes the mask plate that this product uses, and can guarantee that like this wafer figure of figure in this special wafer and volume production is in full accord; The metal ingredient of PAD (uses the alloy of AL and Cu as one in addition, and their usage ratio separately) and the term harmonization of technological parameter (as the making temperature in technical process etc. to parameter) and volume production, the wafer that can fully guarantee like this PAD composition on special wafer and hardness and volume production is in full accord, thereby but has guaranteed referential and the validity of the data that obtain on this special wafer.
In addition, for the demand that checks the needle tracking quality, in order to reduce costs, other parts of the chip circuit of wafer need not to make, and only need top metal to get final product.
Moreover, in order to see simultaneously the electrical characteristic of probe, can accomplish lower ground, complete the working it out of PAD, be beneficial to further analysis, can pass through the test to the protective circuit of PAD, more comprehensively verify the contact performance between probe and PAD.
The special wafer figure of the present invention's design, the pad position that has comprised a plurality of products on this wafer figure, aborning, this special use, special wafer can quantize the contact performance of probe fast, so that the problem of probe itself is analyzed fast, and can be according to the product needed of reality, make different product parameters, thereby be used for probe is carried out detection and the reparation of characteristic, therefore, can effectively check probe and analyze, improve the utilization rate of dedicated test wafer, reduce costs.
Claims (8)
1. the special wafer domain arrangement method for detection of probe, is characterized in that, comprising:
(1) define the number of the product that need to realize on wafer;
(2) according to the product number, wafer is divided into the zone corresponding with the product number, make the IO PAD array of a product in each zone, form special wafer figure.
2. the method for claim 1, it is characterized in that: the number of described step (1) is one or more products.
3. the method for claim 1, it is characterized in that: in described step (2), the product the when framework of PAD array and volume production is in full accord.
4. the manufacture method of the special wafer for detection of probe as claimed in claim 1 is characterized in that: comprising:
(1) according to special wafer domain arrangement method as claimed in claim 1, form special wafer figure;
(2) carry out the production of different product according to the zones of different of wafer figure, obtain to contain one piece of special wafer of different product.
5. method as claimed in claim 4 is characterized in that: in described step (2), and the mask plate that uses in the wafer production process and the Fabrication parameter of the PAD term harmonization during all with volume production.
6. method as claimed in claim 5 is characterized in that: in described step (2), and the term harmonization the when metal ingredient of the PAD in the wafer production process and technological parameter and volume production.
7. method as claimed in claim 6, is characterized in that: in described step (2), with complete the working it out of PAD.
8. method as claimed in claim 4, it is characterized in that: in described step (2), the chip circuit of wafer only needs top-level metallic.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011103441939A CN103094142A (en) | 2011-11-04 | 2011-11-04 | Special wafer layout configuration method used for detecting probe card and manufacture of wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011103441939A CN103094142A (en) | 2011-11-04 | 2011-11-04 | Special wafer layout configuration method used for detecting probe card and manufacture of wafer |
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| CN103094142A true CN103094142A (en) | 2013-05-08 |
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| CN2011103441939A Pending CN103094142A (en) | 2011-11-04 | 2011-11-04 | Special wafer layout configuration method used for detecting probe card and manufacture of wafer |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104183512A (en) * | 2013-05-21 | 2014-12-03 | 中芯国际集成电路制造(上海)有限公司 | Wafer monitoring method |
| CN105139893A (en) * | 2015-09-27 | 2015-12-09 | 上海华力微电子有限公司 | Memorizer testing device and memorizer chip testing method |
| CN112014604A (en) * | 2019-05-28 | 2020-12-01 | 云谷（固安）科技有限公司 | Wafer testing device, testing system and testing method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5153507A (en) * | 1990-11-16 | 1992-10-06 | Vlsi Technology, Inc. | Multi-purpose bond pad test die |
| US20060132162A1 (en) * | 2004-12-16 | 2006-06-22 | Romi Mayder | Mock wafer, system calibrated using mock wafer, and method for calibrating automated test equipment |
| CN101943709A (en) * | 2009-07-07 | 2011-01-12 | 瑞萨电子株式会社 | Probe, proving installation and method of testing |
-
2011
- 2011-11-04 CN CN2011103441939A patent/CN103094142A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5153507A (en) * | 1990-11-16 | 1992-10-06 | Vlsi Technology, Inc. | Multi-purpose bond pad test die |
| US20060132162A1 (en) * | 2004-12-16 | 2006-06-22 | Romi Mayder | Mock wafer, system calibrated using mock wafer, and method for calibrating automated test equipment |
| CN101943709A (en) * | 2009-07-07 | 2011-01-12 | 瑞萨电子株式会社 | Probe, proving installation and method of testing |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104183512A (en) * | 2013-05-21 | 2014-12-03 | 中芯国际集成电路制造(上海)有限公司 | Wafer monitoring method |
| CN104183512B (en) * | 2013-05-21 | 2017-04-05 | 中芯国际集成电路制造(上海)有限公司 | A kind of wafer monitoring method |
| CN105139893A (en) * | 2015-09-27 | 2015-12-09 | 上海华力微电子有限公司 | Memorizer testing device and memorizer chip testing method |
| CN105139893B (en) * | 2015-09-27 | 2018-10-16 | 上海华力微电子有限公司 | A kind of memorizer test device and a kind of storage core chip test method |
| CN112014604A (en) * | 2019-05-28 | 2020-12-01 | 云谷（固安）科技有限公司 | Wafer testing device, testing system and testing method |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20140116 |
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Free format text: CORRECT: ADDRESS; FROM: 201206 PUDONG NEW AREA, SHANGHAI TO: 201203 PUDONG NEW AREA, SHANGHAI |
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Effective date of registration: 20140116 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Applicant before: Shanghai Huahong NEC Electronics Co., Ltd. |
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Application publication date: 20130508 |