CN103855045A - Adjustment method for parameters of chips on wafer - Google Patents
Adjustment method for parameters of chips on wafer Download PDFInfo
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- CN103855045A CN103855045A CN201210499889.3A CN201210499889A CN103855045A CN 103855045 A CN103855045 A CN 103855045A CN 201210499889 A CN201210499889 A CN 201210499889A CN 103855045 A CN103855045 A CN 103855045A
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- chip
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3177—Testing of logic operation, e.g. by logic analysers
Abstract
The invention discloses an adjustment method for parameters of chips on a wafer. The method includes the following steps: step1: grouping all chips on a test wafer into a plurality of test units; step2: measuring a specific parameter of each chip in a specific test unit through a probe card so as to obtain eigenvalues of the parameters of all the chips in the test unit; step3: obtaining a mean value of the eigenvalues of the parameters of all the chips in the test unit and using the mean value of the parameters as an adjustment target value of all the chips in the test unit and at the same time writing the mean value of the parameters into the chips for being used in follow-up tests and normal work so as to complete adjustment of a specific test unit on the test wafer; step4: repeating the step 2 and step3 until adjustment of all test units on the test wafer is completed. The adjustment method for the parameters of the chips on the wafer is capable of ensuring the adjustment accuracy while ensuring large-scale mass production.
Description
Technical field
The present invention relates to a kind of method of testing of large scale integrated circuit, be specifically related to the method for repairing and regulating of chip parameter on a kind of wafer.
Background technology
In the time testing, often there is the phenomenon that some parameter of chip need to trim in large scale integrated circuit.Each chip may have multiple different parameters and need to trim, as comprises reference voltage value, the function magnitude of voltage of chip, the current value of chip, the chip frequency of chip.Because the reason of producing, the eigenvalue of these parameters of chip may, not in the scope of application of this parameter, need to trim the parameter value of chip to its scope of application, could meet instructions for use.
While trimming, what some chips need to be born trims, and some chips need to carry out positive trimming; According to the difference of its eigenvalue, the value of trimming of each chip is also different.
But large-scale logic testing instrument, in the time of test chip, is considered from the angle of producing, and often adopts on a large scale test simultaneously, cannot impose the different values of trimming to each chip respectively, the accuracy trimming while causing scale of mass production is too low.Want to improve the accuracy trimming, can only trim each parameter of each chip respectively, cause being so again doubled and redoubled of testing time, cannot meet the needs of scale of mass production.
Summary of the invention
Technical problem to be solved by this invention is to provide the method for repairing and regulating of chip parameter on a kind of wafer, and it can shorten the testing time.
For solving the problems of the technologies described above, on wafer of the present invention, the technical solution of the method for repairing and regulating of chip parameter is:
Comprise the following steps:
The first step, all chips that at every turn can cover taking probe are a measuring unit, and all chips on test wafer are divided into multiple measuring units;
Second step, measures by probe a certain parameter that in a certain measuring unit, each chip need to trim, and obtains the eigenvalue of this parameter of whole chips in this measuring unit;
The parameter of described chip is reference voltage value, the function magnitude of voltage of chip, the current value of chip, the chip frequency of chip.
The 3rd step, parameter eigenvalue to whole chips in this measuring unit is averaged, using this mean parameter in this measuring unit all chips trim desired value, write in chip for chip simultaneously in follow-up test and normal work, thereby complete trimming of a certain measuring unit on test wafer;
While averaging, if the core number in measuring unit is abundant, after removing a maximum and a minimum value, then calculate the mean value of this measuring unit.
The 4th step, repeats second step to the three steps, completes trimming of another measuring unit on test wafer; Until complete on whole piece of test wafer all trimming of measuring units.
Or, comprise the following steps:
The first step, all chips that at every turn can cover taking probe are a measuring unit, the polylith region on selection test wafer is as the test unit of representative;
Distribution characteristics in polylith Regional Representative wafer face on described test wafer; Described polylith region press upper and lower, left and right in wafer face, in position distribution, or polylith region is all positioned at the periphery of test wafer.
Second step, measures respectively by probe a certain parameter that in the whole test unit of representative, each chip need to trim, and obtains in the test unit of representative all eigenvalues of this parameter of chips;
The parameter of described chip is reference voltage value, the function magnitude of voltage of chip, the current value of chip, the chip frequency of chip.
The 3rd step, parameter eigenvalue to whole chips in the test unit of representative is averaged, trim desired value using this mean parameter as this test wafer, write in chip for chip simultaneously in follow-up test and normal work, complete trimming of whole piece of test wafer.
The technique effect that the present invention can reach is:
The desired value that the present invention trims each parameter of all measuring units inside is unified, in the time being written in chip, can adopt the mode being written in parallel to, but not serial writes one by one, has greatly shortened the testing time.
The present invention can improve the accuracy trimming in ensureing scale of mass production.
Brief description of the drawings
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
Fig. 1 is the schematic diagram of the method for repairing and regulating of chip parameter on wafer of the present invention;
Fig. 2 is the schematic diagram that comprises 16 chips in each measuring unit;
Fig. 3 is the schematic diagram of another embodiment of the present invention.
Description of reference numerals in figure:
1 is measuring unit, and 10 is test wafer,
2 is the test unit of representative.
Embodiment
As shown in Figure 1, the method for repairing and regulating of chip parameter on wafer of the present invention, comprises the following steps:
The first step, all chips that at every turn can cover taking probe are a measuring unit, and all chips on test wafer 10 are divided into multiple measuring units (being divided into 14 measuring units 1 in Fig. 1);
As shown in Figure 2, if probe once can be pricked 16 chips, in each measuring unit, comprise at most 16 chips, the every bundle of probe once can measure the parameter eigenvalue of whole chips in measuring unit like this;
Second step, measures by probe a certain parameter that in a certain measuring unit, each chip need to trim, and obtains the eigenvalue of this parameter of whole chips in this measuring unit;
The parameter of chip can be reference voltage value, the function magnitude of voltage of chip, the current value of chip, the chip frequency of chip;
The 3rd step, parameter eigenvalue to whole chips in this measuring unit is averaged, using this mean parameter in this measuring unit all chips trim desired value, write in chip for chip simultaneously in follow-up test and normal work, thereby complete trimming of a certain measuring unit on test wafer 10;
If the core number in measuring unit is abundant, as exceed 32 more than chip, after can removing a maximum and a minimum value, then calculate the mean value of this measuring unit;
The 4th step, repeats second step to the three steps, completes trimming of another measuring unit on test wafer 10; Until complete on whole piece of test wafer 10 all trimming of measuring units.
Test wafer is divided into multiple measuring units by the present invention, and all chip under test in each measuring unit are adopted to the same value of trimming, and a measuring unit once trims, to shorten the testing time.
As another embodiment of the present invention, as shown in Figure 3, the present invention includes following steps:
The first step, all chips that at every turn can cover taking probe are a measuring unit, the polylith region on selection test wafer 10 is as the test unit of representative (selecting 5 test units of representative 2) in Fig. 3;
Polylith region on this test wafer 10 can represent the distribution characteristics in wafer face, polylith region can by the upper and lower, left and right in wafer face, in position distribution;
Consider that wafer is adding peripheral characteristics in the man-hour situation poorer than intermediate characteristic, middle data of testing the unit of representative also can be only for reference, and only get the data of the several test of the periphery unit of representative as the data source of desired value; Or the hits of the peripheral test unit of representative continues to be increased to proper number;
Second step, measures respectively by probe a certain parameter that in all (five) tests unit of representative, each chip need to trim, and obtains the eigenvalue of this parameter of whole chips in the test unit of representative;
The parameter of chip can be reference voltage value, the function magnitude of voltage of chip, the current value of chip, the chip frequency of chip;
The 3rd step, parameter eigenvalue to whole chips in the test unit of representative is averaged, and the desired value that trims using this mean parameter as this test wafer 10 is write in chip simultaneously, in follow-up test and normal work, complete trimming of whole piece of test wafer 10 for chip.
The present invention adopts the same desired value that trims to all chip under test in whole piece of test wafer, the analysis times that trims desired value can be reduced to a certain degree (as five times), to shorten the testing time.
The present invention carries out the test realization that trims of whole piece of wafer simultaneously.
Claims (6)
1. a method for repairing and regulating for chip parameter on wafer, is characterized in that, comprises the following steps:
The first step, all chips that at every turn can cover taking probe are a measuring unit, and all chips on test wafer are divided into multiple measuring units;
Second step, measures by probe a certain parameter that in a certain measuring unit, each chip need to trim, and obtains the eigenvalue of this parameter of whole chips in this measuring unit;
The 3rd step, parameter eigenvalue to whole chips in this measuring unit is averaged, using this mean parameter in this measuring unit all chips trim desired value, write in chip for chip simultaneously in follow-up test and normal work, thereby complete trimming of a certain measuring unit on test wafer;
The 4th step, repeats second step to the three steps, completes trimming of another measuring unit on test wafer; Until complete on whole piece of test wafer all trimming of measuring units.
2. the method for repairing and regulating of chip parameter on wafer according to claim 1, is characterized in that, the reference voltage value that the parameter of described chip is chip, the function magnitude of voltage of chip, the current value of chip, chip frequency.
3. the method for repairing and regulating of chip parameter on wafer according to claim 1, it is characterized in that, when described the 3rd step is averaged, if the core number in measuring unit is abundant, after removing a maximum and a minimum value, then calculate the mean value of this measuring unit.
4. a method for repairing and regulating for chip parameter on wafer, is characterized in that, comprises the following steps:
The first step, all chips that at every turn can cover taking probe are a measuring unit, the polylith region on selection test wafer is as the test unit of representative;
Second step, measures respectively by probe a certain parameter that in the whole test unit of representative, each chip need to trim, and obtains in the test unit of representative all eigenvalues of this parameter of chips;
The 3rd step, parameter eigenvalue to whole chips in the test unit of representative is averaged, trim desired value using this mean parameter as this test wafer, write in chip for chip simultaneously in follow-up test and normal work, complete trimming of whole piece of test wafer.
5. the method for repairing and regulating of chip parameter on wafer according to claim 4, is characterized in that, the distribution characteristics in the polylith Regional Representative wafer face on described test wafer; Described polylith region press upper and lower, left and right in wafer face, in position distribution, or polylith region is all positioned at the periphery of test wafer.
6. the method for repairing and regulating of chip parameter on wafer according to claim 4, is characterized in that, the reference voltage value that the parameter of described chip is chip, the function magnitude of voltage of chip, the current value of chip, chip frequency.
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| CN201210499889.3A CN103855045B (en) | 2012-11-29 | 2012-11-29 | The method for repairing and regulating of chip parameter on wafer |
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| CN201210499889.3A CN103855045B (en) | 2012-11-29 | 2012-11-29 | The method for repairing and regulating of chip parameter on wafer |
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| CN103855045B CN103855045B (en) | 2017-06-06 |
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Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104538327A (en) * | 2014-12-29 | 2015-04-22 | 上海华虹宏力半导体制造有限公司 | Trimming method |
| CN105206305A (en) * | 2015-09-22 | 2015-12-30 | 上海华虹宏力半导体制造有限公司 | Method for increasing flash device windows through test program |
| CN105242192A (en) * | 2015-10-09 | 2016-01-13 | 上海华虹宏力半导体制造有限公司 | Wafer testing method |
| CN105353293A (en) * | 2015-10-09 | 2016-02-24 | 上海华虹宏力半导体制造有限公司 | Wafer testing method |
| CN105551993A (en) * | 2015-12-23 | 2016-05-04 | 上海威伏半导体有限公司 | Trimming method and device of wafer parameter |
| CN107481765A (en) * | 2017-08-22 | 2017-12-15 | 珠海泓芯科技有限公司 | Flash chip trims method of testing and trims test device |
| CN109085491A (en) * | 2018-08-08 | 2018-12-25 | 上海华力微电子有限公司 | A method of improving analog quantity Trimming program test efficiency |
| CN109613420A (en) * | 2019-01-30 | 2019-04-12 | 上海华虹宏力半导体制造有限公司 | The test method of chip |
| CN109901650A (en) * | 2017-12-07 | 2019-06-18 | 北京确安科技股份有限公司 | A kind of a reference source method for repairing and regulating of embedded flash chip |
| CN111312608A (en) * | 2020-02-25 | 2020-06-19 | 上海华虹宏力半导体制造有限公司 | Wafer parameter trimming method |
| CN112147488A (en) * | 2020-09-25 | 2020-12-29 | 杰华特微电子（杭州）有限公司 | Chip parameter testing and calibrating method |
| TWI730510B (en) * | 2019-11-26 | 2021-06-11 | 松翰股份有限公司 | Whole-area image test method and architecture |
| CN114217206A (en) * | 2021-12-06 | 2022-03-22 | 广东利扬芯片测试股份有限公司 | Detection system of double-sided process PIN diode power management chip |
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Cited By (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104538327A (en) * | 2014-12-29 | 2015-04-22 | 上海华虹宏力半导体制造有限公司 | Trimming method |
| CN104538327B (en) * | 2014-12-29 | 2017-08-08 | 上海华虹宏力半导体制造有限公司 | A kind of method for repairing and regulating |
| CN105206305A (en) * | 2015-09-22 | 2015-12-30 | 上海华虹宏力半导体制造有限公司 | Method for increasing flash device windows through test program |
| CN105206305B (en) * | 2015-09-22 | 2018-08-21 | 上海华虹宏力半导体制造有限公司 | Increase the method for flash device windows by test program |
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| CN105242192A (en) * | 2015-10-09 | 2016-01-13 | 上海华虹宏力半导体制造有限公司 | Wafer testing method |
| CN105353293A (en) * | 2015-10-09 | 2016-02-24 | 上海华虹宏力半导体制造有限公司 | Wafer testing method |
| CN105353293B (en) * | 2015-10-09 | 2018-04-17 | 上海华虹宏力半导体制造有限公司 | Crystal round test approach |
| CN105551993A (en) * | 2015-12-23 | 2016-05-04 | 上海威伏半导体有限公司 | Trimming method and device of wafer parameter |
| CN105551993B (en) * | 2015-12-23 | 2018-06-12 | 上海威伏半导体有限公司 | The method for repairing and regulating and device of a kind of wafer parameters |
| CN107481765A (en) * | 2017-08-22 | 2017-12-15 | 珠海泓芯科技有限公司 | Flash chip trims method of testing and trims test device |
| CN109901650A (en) * | 2017-12-07 | 2019-06-18 | 北京确安科技股份有限公司 | A kind of a reference source method for repairing and regulating of embedded flash chip |
| CN109085491A (en) * | 2018-08-08 | 2018-12-25 | 上海华力微电子有限公司 | A method of improving analog quantity Trimming program test efficiency |
| CN109613420A (en) * | 2019-01-30 | 2019-04-12 | 上海华虹宏力半导体制造有限公司 | The test method of chip |
| CN109613420B (en) * | 2019-01-30 | 2021-04-06 | 上海华虹宏力半导体制造有限公司 | Chip testing method |
| TWI730510B (en) * | 2019-11-26 | 2021-06-11 | 松翰股份有限公司 | Whole-area image test method and architecture |
| CN111312608A (en) * | 2020-02-25 | 2020-06-19 | 上海华虹宏力半导体制造有限公司 | Wafer parameter trimming method |
| CN112147488A (en) * | 2020-09-25 | 2020-12-29 | 杰华特微电子（杭州）有限公司 | Chip parameter testing and calibrating method |
| CN114217206A (en) * | 2021-12-06 | 2022-03-22 | 广东利扬芯片测试股份有限公司 | Detection system of double-sided process PIN diode power management chip |
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