CN104916559B - The position failure method for detecting of binding entity coordinate - Google Patents
The position failure method for detecting of binding entity coordinate Download PDFInfo
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- CN104916559B CN104916559B CN201410084502.7A CN201410084502A CN104916559B CN 104916559 B CN104916559 B CN 104916559B CN 201410084502 A CN201410084502 A CN 201410084502A CN 104916559 B CN104916559 B CN 104916559B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
Abstract
The invention discloses a kind of position of binding entity coordinate failure method for detecting, Wafer alignment detection data are first obtained in this method, and it includes the image of each layer of defect and the entities coordinate of this defect in a wafer；Then, a failure detecting step is carried out, to obtain the digital coordinates of fail bit in wafer, and this digital coordinates is changed into provider location, and provider location is overlapped in entities coordinate, quickly to obtain the relevance between fail bit and defect.
Description
Technical field
Have the invention relates to a kind of failure analytical approach (Failure Analysis Methodology), and particularly
Fail method for detecting for a kind of position on binding entity coordinate.
Background technology
Persistently reduced with the line width of IC techniques, the accurate control for element is also more important with monitoring.With nanometer generation
From the point of view of semiconductor technology, to increase the yield of element certainly will will carry out accurate detection and analysis to it.
The method for analyzing (failure analysis, FA) currently used for chip failure includes a kind of referred to as position failure detecting
The technology of (Bitmap failure), can obtain fail bit (failure bits) and finds out its provider location, and can basis
Failure project (failure item) come predict be chip internal the failure of which Rotating fields.
However, because causing the reason for position is failed to fail to understand, if it is intended to accurate obtain the reason for failing in place, it is just necessary
Tested whole chip is ground since surface, until that Rotating fields that position is failed may be caused, then it is scanned
Formula electron microscope (SEM) surface analysis.Therefore, current position failure analysis work consuming takes.
The content of the invention
The present invention provides a kind of position failure method for detecting of binding entity coordinate, when can significantly shorten the analysis of position failure
Between.
The present invention separately provides a kind of position failure method for detecting of binding entity coordinate, can quickly obtain the entity position of fail bit
Put and failure cause.
The position failure method for detecting of the binding entity coordinate of the present invention includes first obtaining Wafer alignment detection data.It is described
Wafer alignment detection datagram includes the image and the defect of each layer of multiple defects in a wafer in many in the wafer
Individual entities coordinate.In this method, a failure detecting step is carried out, to obtain a numeral of multiple fail bits in the wafer
Coordinate, and the digital coordinates are changed into line or polygonal multiple provider locations.Then, provider location is overlapped in wafer
Entities coordinate, to obtain the relevance between fail bit and defect.
In one embodiment of this invention, above-mentioned method also includes the provider location correspondence according to the respectively fail bit
The entities coordinate in the wafer, obtains micro- (SEM) image of scanning electron of the defect, then according to SEM images
The reason for judgement causes the fail bit.
In one embodiment of this invention, the step of above-mentioned provider location is overlapped in the entities coordinate in wafer includes basis
Different defects, the fail bit is classified in Wafer alignment detection data.
The position failure method for detecting of another binding entity coordinate of the present invention includes carrying out a failure detecting step, to take
The digital coordinates of all fail bits in a wafer are obtained, then the digital coordinates are converted into a graphic data system coordinate (GDS
File coordinate) or a testing result coordinate (inspection result file coordinate).Then, compare
The data of the graphic data system coordinate or the testing result coordinate and database (database) archives of the wafer,
To export multiple provider locations of the fail bit.Compare the testing result shelves of the provider location and the wafer, you can
To defect corresponding with fail bit.
In another embodiment of the invention, above-mentioned method also includes entering the fail bit according to resulting defect
Row classification.
In another embodiment of the invention, if what above-mentioned digital coordinates were changed is testing result coordinate, then comparing
In the step of data and Data Base Pile, by testing result coordinate directly with detecting defective wafer figure (defect Klarf map)
It is compared.
In another embodiment of the invention, if what above-mentioned digital coordinates were changed is graphic data system coordinate, then exist
Comparison data is with before Data Base Pile, the coordinate for detecting defective wafer figure first to be switched to the coordinate of graphic data system file.
In the various embodiments of the invention, the digital coordinates obtained by upper bit fail detecting step include multiple bit lines
Failure and multiple wordline failure.
In the various embodiments of the invention, the failure of above-mentioned bit line or the failure of wordline may include open circuit (open), short circuit
Or path (close) (short).
In the various embodiments of the invention, the position of drawbacks described above includes wordline, bit line, polysilicon layer or contact hole.
In the various embodiments of the invention, above-mentioned method also includes comparing the quantity of fail bit and the sum of defect,
To obtain the probability (also known as " the defective effect yield ratio that source layer is produced ") for the defect that inducement fails in position.
In the various embodiments of the invention, above-mentioned method also includes the detection by being located at different crystal grain in the wafer
As a result the system defect (repeating systematic defects) repeated.
Based on above-mentioned, the present invention can once obtain the analysis result of hundreds if not thousands of positions failure in a short time, and
The source (layer) of wordline failure or the lethality of defect type can be obtained by the ratio between defects count and fail bit.And
The present invention passes through the chip image stored by chip detecting system, moreover it is possible to directly obtain the image for the rejected region for triggering position failure
And judge its defect type.
For the features described above and advantage of the present invention can be become apparent, special embodiment below, and coordinate institute's accompanying drawings
It is described in detail below.
Brief description of the drawings
Fig. 1 is a kind of position failure detecting block diagram of binding entity coordinate according to the first embodiment of the present invention.
Fig. 2 is the Wafer alignment testing result figure in first embodiment.
Fig. 3 A are according to Wafer alignment to detect that data are classified the bar graph of fail bit in first embodiment.
Fig. 3 B are the wafer figures (wafer map) obtained via Fig. 3 A.
Fig. 4 is a kind of position failure detecting block diagram of binding entity coordinate according to the second embodiment of the present invention.
Fig. 5 is the coordinate schematic diagram obtained by second embodiment.
Fig. 6 is the SEM striographs of the defective locations in Fig. 5.
【Symbol description】
100~130,400~430：Step
301~309：Type
500：Coordinate
502：Straight line
504：Region
506：Defect
Embodiment
Fig. 1 is a kind of position failure detecting block diagram of binding entity coordinate according to the first embodiment of the present invention.
Fig. 1 is refer to, the method for the present embodiment first carries out step 100, obtain Wafer alignment detection (wafer
Mapping) data.So-called Wafer alignment detection is by detecting board according to wafer figure (wafer map) and actual wafer
Align and obtain image, therefore the crystal grain of each in wafer (die) can be detected in real time, and for the various defects in crystal grain in crystalline substance
Coding is marked in different colors on circle diagram, as shown in Figure 2 (though Fig. 2 is actually colour with white and black displays).Above-mentioned image one
As be with scanning electron micro- (SEM) obtain, so can be deposited and be named respectively with die locations or defect kind.At this
In embodiment, Wafer alignment detection datagram includes defect image in single wafer in each Rotating fields and each lacks
Sink into the entities coordinate (physical coordinates) in the wafer.The position of drawbacks described above such as wordline, bit line, many
Structure in the wafers such as crystal silicon layer, contact hole.
Then, in step 110, line position failure detecting (Bitmap failure) step is entered, to obtain in above-mentioned wafer
The digital coordinates of fail bit (failure bits).The technology of so-called position failure detecting is to measure failure using Detecting device
Position, and with digital coordinates output result.The digital coordinates obtained by upper bit fail detecting step can include different types of
Failed caused by position failure, the failure of such as bit line, the failure of wordline or All other routes.Moreover, the failure of bit line either wordline
Failure can also be categorized into the failure caused by different reasons, for example open a way (open), short-circuit (short) or path
(close) etc..
Then, in the step 120, above-mentioned digital coordinates are changed into line or the provider location of polygon (polygon).Due to
Data obtained by current position failure detecting step are the physical layouts that fail bit is shown with GDSII coordinate forms, so can
By the specific software in above-mentioned Detecting device or other appropriate equipment, digital coordinates are converted into correspond to step 100
Wafer alignment detection entities coordinate archives.
Then, in step 130, above-mentioned provider location is overlapped in the entities coordinate in wafer, with obtain fail bit with
Relevance between defect.For example, it can obtain including defect numbering (defect ID), x and y after step 130 is performed
Coordinate value, defect classification, the data such as source layer (source layer), corresponding SEM images (if any).As above
State, the step 130 of the present embodiment can further detect defects different in data according to Wafer alignment, and the fail bit is carried out
Classification, refer to the bar graph 3A obtained after classification, and it shows 9 kinds of different defect types 301~309 and its is corresponding
Quantity, and the quantity of all defect is 1647.If analyzing distribution of the different defects on wafer, it can be pushed away via software is counter
Obtain Fig. 3 B wafer figure (though Fig. 3 B are with white and black displays but actually colored).
Further, since according to the entities coordinate in the provider location of each fail bit correspondence wafer, each defect can be obtained
SEM images, and the reason for fail bit can be caused according to SEM scope interpretations.SEM images herein are above-mentioned Wafer alignment inspection
Acquired image during survey, so not needing the extra time to obtain the image of these defects.Certain present invention is not limited to
This, as long as according to the entities coordinate in the provider location of fail bit correspondence wafer, the position with regard to defect can be obtained, and and then compare
Feature (signature) and fail bit.
In addition, can also be come according to the method for first embodiment by comparing the quantity of fail bit and the sum of defect
Probability (also known as " defective effect yield ratio (the source killing that source layer is produced of the defect failed to inducement in position
ratio)」).In other words, Wafer alignment detection data display defects count a total of m obtained by step 100, and from step
Rapid 130 are obtained being that n is individual corresponding to the defects count of fail bit, then inducement can be obtained by (n/m × 100%) in lacking that position is failed
Sunken probability.
Furthermore, because first embodiment is the detecting to whole wafer progress, therefore can be by being located at the not isomorphous in wafer
The system defect (repeating systematic defects) that the testing result of grain (die) is repeated.For example, such as
Fruit sets allowable error as 1 μm, and the defect in same position ± 1 μm of different crystal grain can regard as the system repeated
(repeating defect)。
Fig. 4 is a kind of position failure detecting block diagram of binding entity coordinate according to the second embodiment of the present invention.
Fig. 4 is refer to, the method for the present embodiment first in step 400, carries out a failure detecting step, brilliant to obtain one
The digital coordinates of all fail bits in circle.Digital coordinates obtained by upper bit fail detecting step can include different types of position
Failed caused by failure, the failure of such as bit line, the failure of wordline or All other routes.Moreover, the failure of bit line either wordline
Failure can also be categorized into the failure caused by different reasons, for example open circuit (open), short-circuit (short) or path (close)
Deng.
In step 410, above-mentioned digital coordinates are converted into graphic data system coordinate (GDS coordinate) or inspection
Survey result coordinate (inspection result coordinate, such as Klarf file coordinate).GDS file is general
It is the circuit design file for being laid out (layout), so the entities coordinate with wafer.In addition, current wafer detection system
As a result GDS coordinates can be also converted into via specific software.It is, for example, the detection device via KLA companies as testing result coordinate
Resulting result shelves (also known as Klarf).Specifically, digital coordinates (such as coordinate of bitmap files) can be converted into entity
GDS coordinates or Klarf coordinates.
Then, at step 420, graph data system coordinates or the data and above-mentioned wafer of testing result coordinate are compared
Database (database) archives, to export the provider location of fail bit.Specifically, if being conversion in previous step 410
For Klarf coordinates, then directly it is compared again with detection defective wafer figure (defect Klarf map).If in addition,
GDS coordinates are converted into previous step 410, then need that the coordinate (Klarf coordinates) for detecting defective wafer figure first is switched into GDS seats
Mark, then compare both.
Then, in step 430, testing result shelves (the inspection result of above-mentioned provider location and wafer are compared
File), you can obtain defect corresponding with each fail bit.What for example Fig. 5 was shown is exactly to carry out available seat after step 430
Sign is intended to.In Figure 5, the straight line 502 in coordinate 500 is the entity position for the fail bit that GDS coordinates are converted into via step 410
Put, and region 504 is exactly the position of the defect 506 corresponding with fail bit obtained by step 403.Although Fig. 5 only shows one
Bar straight line 502 (i.e. one fail bit), but thousands of or tens thousand of fail bits are actually had in single wafer, therefore the present invention is simultaneously
Not limited to this.It is during wafer process to be additionally, since so-called " testing result shelves (inspection result file) "
The wafer detection performed as each step is carried out, such as Wafer alignment detection (wafer mapping), so can take simultaneously
The image of actual each layer of wafer is obtained, so it is micro- to find out corresponding scanning electron according to the coordinate in Fig. 5 region 504
(SEM) striograph 6, and the reason for fail bit (502) can be caused according to SEM scope interpretations.If the SEM of a certain layer in prediction
Discovery defect is had no in image, then defect can be found out by the SEM images for the same position for inspecting other layers.
Moreover, can also be classified according to resulting defect to the fail bit.For example, because the position of defect
It is probably the two or more structure of wordline, bit line, polysilicon layer, contact hole or more, so can also be by the fail bit measured
(1) is categorized into because fail bit, (2) are because of fail bit, (3) caused by the defect of bit line in itself caused by the defect of wordline in itself
Because fail bit, (4) caused by the defect of contact hole because fail caused by the defect of polysilicon layer (such as grid structure)
Position ... etc..
In addition, in a second embodiment, can by comparing the quantity of fail bit and the sum of defect, come obtain inducement in
Probability (also known as " defective effect yield ratio (the source killing that source layer is produced of the defect of position failure
ratio)」).It can also be repeated in a second embodiment by being located at the testing result of not isomorphous position (die ID) in wafer
System defect (repeating systematic defects).
In summary, the present invention can once obtain the analysis result of hundreds if not thousands of positions failure in a short time, and
By obtaining exact position of the defect with respect to fail bit, be conducive to detecting fail bit and find out its reason.The present invention can also pass through
Ratio between defects count and fail bit obtains source (layer) lethality of wordline failure.Because the present invention is detected using chip
Chip image stored by system, so the image for the rejected region for triggering position failure can also be obtained directly.In addition, according to this hair
Bright method can also obtain the system defect of repetition.
Although the present invention is disclosed above with embodiment, so it is not limited to the present invention, any art
Middle tool usually intellectual, without departing from the spirit and scope of the present invention, when a little change and retouching can be made, thus it is of the invention
Protection domain when depending on being defined that appended claims scope is defined.
Claims (12)
1. a kind of position failure method for detecting of binding entity coordinate, including：
Wafer alignment detection data are obtained, the Wafer alignment detection data include each layer of multiple defects in a wafer
Image and the defect are in multiple entities coordinates in the wafer；
A failure detecting step is carried out, to obtain a digital coordinates of multiple fail bits in the wafer；
The digital coordinates are changed into line or polygonal multiple provider locations；And
The provider location is overlapped in the entities coordinate in the wafer, with obtain the fail bit and the defect it
Between relevance.
2. the position failure method for detecting of binding entity coordinate according to claim 1, is further included：
According to the entities coordinate in the provider location of the respectively fail bit correspondence wafer, many of the defect are obtained
Individual scanning electron micro-imaging；And
The reason for judging to cause the fail bit according to the scanning electron micro-imaging.
3. the position failure method for detecting of binding entity coordinate according to claim 1, wherein the provider location is overlapped in
The step of entities coordinate in the wafer, includes：The defects different in data are detected according to the Wafer alignment,
The fail bit is classified.
4. a kind of position failure method for detecting of binding entity coordinate, including：
A failure detecting step is carried out, to obtain a digital coordinates of all fail bits in a wafer；
The digital coordinates are converted into a graphic data system coordinate or a testing result coordinate；
Compare a data and the database shelves of the wafer for the graphic data system coordinate or the testing result coordinate
Case, to export multiple provider locations of the fail bit；And
The testing result shelves of the provider location and the wafer are compared, it is corresponding with the fail bit multiple scarce to obtain
Fall into.
5. the position failure method for detecting of binding entity coordinate according to claim 4, is further included according to the defect to institute
Fail bit is stated to be classified.
6. the position failure method for detecting of binding entity coordinate according to claim 4, wherein digital coordinates conversion
If being the testing result coordinate, then in the step of data are with the Data Base Pile is compared, the detection is tied
Fruit coordinate is directly compared with detection defective wafer figure.
7. the position failure method for detecting of binding entity coordinate according to claim 4, wherein digital coordinates conversion
If being the graphic data system coordinate, then further included before the step of data are with the Data Base Pile is compared：Will
Detection defective wafer figure coordinate switchs to the coordinate of a graphic data system file.
8. the position failure method for detecting of the binding entity coordinate according to claim 1 or 4, wherein position failure detecting step
The digital coordinates of rapid gained include the failure of multiple bit lines and the failure of multiple wordline.
9. the position failure method for detecting of binding entity coordinate according to claim 8, wherein failure or the institute of the bit line
Stating the failure of wordline includes open circuit (open), short-circuit (short) or path (close).
10. the position failure method for detecting of the binding entity coordinate according to claim 1 or 4, wherein the position of the defect
Including wordline, bit line, polysilicon layer or contact hole.
11. the position failure method for detecting of the binding entity coordinate according to claim 1 or 4, is further included by relatively more described
The sum of the quantity of fail bit and the defect, to obtain the probability for the defect that inducement fails in position.
12. the position failure method for detecting of the binding entity coordinate according to claim 1 or 4, is further included by the wafer
The system defect that the interior testing result positioned at different crystal grain is repeated.
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Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107833843B (en) * | 2017-11-02 | 2020-02-21 | 武汉新芯集成电路制造有限公司 | Defect source analysis method and system, and defect detection device |
| CN108519550B (en) * | 2018-03-28 | 2020-06-23 | 上海华岭集成电路技术股份有限公司 | Integrated circuit wafer test optimization method |
| CN110690136A (en) * | 2019-10-12 | 2020-01-14 | 上海华力微电子有限公司 | Defect detection method and system |
| CN113092981B (en) * | 2019-12-23 | 2022-04-26 | 长鑫存储技术有限公司 | Wafer data detection method and system, storage medium and test parameter adjustment method |
| EP3982326A4 (en) | 2020-07-27 | 2022-10-19 | Changxin Memory Technologies, Inc. | Failure pattern acquisition method and acquisition apparatus |
| CN114004778A (en) * | 2020-07-27 | 2022-02-01 | 长鑫存储技术有限公司 | Failure graph obtaining method and device |
| CN114169286A (en) * | 2020-09-11 | 2022-03-11 | 长鑫存储技术有限公司 | Wafer defect tracing method and device, electronic equipment and computer readable medium |
| US11927544B2 (en) | 2020-09-11 | 2024-03-12 | Changxin Memory Technologies, Inc. | Wafer defect tracing method and apparatus, electronic device and computer readable medium |
| CN114397985B (en) * | 2022-03-25 | 2022-07-12 | 杭州广立微电子股份有限公司 | Wafer yield data processing method and device |
| CN114399508A (en) * | 2022-03-25 | 2022-04-26 | 杭州广立微电子股份有限公司 | Wafer data processing method and device, electronic device and storage medium |
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