CN114399508A

CN114399508A - Wafer data processing method and device, electronic device and storage medium

Info

Publication number: CN114399508A
Application number: CN202210300070.3A
Authority: CN
Inventors: 王子鑫; 刘永利
Original assignee: Hangzhou Guangli Microelectronics Co ltd
Current assignee: Hangzhou Guangli Microelectronics Co ltd
Priority date: 2022-03-25
Filing date: 2022-03-25
Publication date: 2022-04-26

Abstract

The application relates to a method and a device for processing wafer data, an electronic device and a storage medium, wherein the method for processing the wafer data comprises the following steps: obtaining a wafer map of a target wafer, wherein the wafer map is divided into a plurality of bare chip areas; respectively determining an electrical failure type and at least one defect type corresponding to each bare chip in the target wafer; and respectively setting identification information matched with the electrical failure type and identification information matched with the at least one defect type in a plurality of die areas in the wafer map. By the method and the device, the technical problem that the value of the wafer data cannot be used by a user is solved, the user can directly determine the correlation between the electrical failure data and the defect data of the bare chip according to the wafer data, the defect reason causing the electrical failure of the bare chip is further visually determined, and the speed and the convenience for analyzing the wafer yield based on the detection result are improved.

Description

Wafer data processing method and device, electronic device and storage medium

Technical Field

The present disclosure relates to the field of wafer inspection, and in particular, to a method and an apparatus for processing wafer data, an electronic apparatus, and a storage medium.

Background

Wafers are becoming increasingly important in the fields of chips, semiconductors, and the like as silicon dies that are essential for the manufacture of semiconductor integrated circuits. Due to problems of manufacturing process, material, environment, etc., defects may occur in the wafer during the manufacturing process, and therefore, the wafer defects need to be detected.

In the prior art, a wafer is generally inspected by a needle touch method, an atomic force method, an optical method, and the like, so as to obtain wafer defect information such as an electrical failure type, a defect position, a defect type, a bare chip region to which a defect belongs, and the like of the wafer. However, the causes, time, locations, etc. of wafer defects are different, and in the prior art, the electrical failure type of the wafer and the wafer defect information can only be displayed in the form of characters or tables, so that the result of wafer defect detection is not intuitive enough, and a user cannot directly analyze the wafer yield according to the detection result, thereby failing to exert the important value of wafer data.

Aiming at the technical problem that the value of wafer data in the related technology cannot be used by a user, no effective solution is provided at present.

Disclosure of Invention

The present embodiment provides a method, an apparatus, an electronic apparatus, and a storage medium for processing wafer data, so as to solve the problem in the related art that the value of the wafer data cannot be used by a user.

In a first aspect, a method for processing wafer data is provided in this embodiment, including:

obtaining a wafer map of a target wafer, wherein the wafer map is divided into a plurality of bare chip areas;

respectively determining an electrical failure type and at least one defect type corresponding to each bare chip in the target wafer;

and respectively setting identification information matched with the electrical failure type and identification information matched with the at least one defect type in a plurality of die areas in the wafer map.

In some embodiments, the setting the identification information matching the at least one defect type in the plurality of die areas in the wafer map respectively includes:

determining the position of a defect in the wafer map;

and setting identification information matched with the at least one defect type in a die region to which the defect position belongs on the basis of the defect position.

In some of these embodiments, said determining the location of the defect in said wafer map comprises:

acquiring the coordinate position of a defect point in the target wafer in an original coordinate system, wherein the original coordinate system comprises a coordinate system based on which the target wafer is observed in the process flow;

and determining the coordinate position of the defect point in the reference coordinate system based on the conversion relation between the original coordinate system and the reference coordinate system corresponding to the wafer map.

In some of these embodiments, the transformation relationship between the original coordinate system and the reference coordinate system is determined as follows:

respectively determining original reference coordinates of at least two reference points in the original coordinate system and reference coordinates in the reference coordinate system;

and determining a conversion relation between the original coordinate system and the reference coordinate system based on the original reference coordinate and the reference coordinate.

In some embodiments, the respectively setting the identification information matching the electrical failure type and the identification information matching the at least one defect type in the plurality of die areas in the wafer map further includes:

receiving a first operation instruction, wherein the first operation instruction is used for instructing to acquire the die area corresponding to at least one target electrical failure type and/or at least one target defect type;

highlighting all of the die regions in the wafer map that correspond to the target electrical failure type and/or target defect type.

receiving a second operation instruction, wherein the second operation instruction is used for instructing to acquire a die image corresponding to at least one target die area;

determining the die image associated with the identification information according to the identification information of the target die area;

displaying the die image corresponding to the target die area.

In some embodiments, the receiving the second operation instruction further comprises:

and respectively judging whether the corresponding bare chip image exists in each bare chip area, and if so, setting preset identification information in the bare chip area.

In some embodiments, the second operation instruction is further used for instructing to acquire failure and defect information corresponding to at least one of the target die areas, and the receiving the second operation instruction further includes:

displaying the failure and defect information corresponding to the target bare chip area, wherein the failure and defect information comprises at least one of the following information: defect identification, coordinates of the target wafer area, failure type, defect generation process step and defect source process step.

In some embodiments, the obtaining the wafer map of the target wafer further includes:

determining drawing data according to the target wafer, wherein the drawing data at least comprises a wafer diameter, a bare chip size and a wafer edge, and also comprises at least one of a wafer gap and a bare chip offset;

and drawing the wafer map based on the wafer data.

In some embodiments, the setting of the identification information matching the electrical failure type in the plurality of die areas in the wafer map includes:

obtaining bare chip coordinates of the bare chip under a reference coordinate system corresponding to the wafer map;

and setting identification information matched with the electrical failure type in the corresponding die area based on the die coordinates.

determining whether at least one end corner of the die region is within a wafer region in the wafer map;

and if the type of the electrical failure exists, setting identification information matched with the electrical failure type in the bare chip area.

In some embodiments, after the setting of the identification information matching the electrical failure type in the plurality of die areas in the wafer map, the method further includes:

and cutting the wafer map based on the edge of the wafer area in the wafer map.

In a second aspect, a device for processing wafer data is provided in this embodiment, including:

the wafer processing device comprises an acquisition module, a processing module and a processing module, wherein the acquisition module is used for acquiring a wafer map of a target wafer, and the wafer map is divided into a plurality of bare chip areas;

the determining module is used for respectively determining the electrical failure type and at least one defect type corresponding to each bare chip in the target wafer;

and the setting module is used for respectively setting the identification information matched with the electrical failure type and the identification information matched with the at least one defect type in a plurality of die areas in the wafer map.

In a third aspect, in this embodiment, an electronic apparatus is provided, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and when the processor executes the computer program, the method for processing wafer data according to the first aspect is implemented.

In a fourth aspect, in the present embodiment, a storage medium is provided, on which a computer program is stored, and the program is executed by a processor to implement the method for processing wafer data according to the first aspect.

Compared with the related art, the present embodiment provides a method, an apparatus, an electronic apparatus, and a storage medium for processing wafer data, where the method includes: obtaining a wafer map of a target wafer, wherein the wafer map is divided into a plurality of bare chip areas; respectively determining an electrical failure type and at least one defect type corresponding to each bare chip in the target wafer; and respectively setting identification information matched with the electrical failure type and identification information matched with the at least one defect type in a plurality of die areas in the wafer map. By setting the corresponding identification information in the bare chip area corresponding to the bare chip, a user can visually observe the electrical failure type and the defect type of each bare chip and the distribution rules of the bare chips under different electrical failure types and defect types, the bare chip to be observed does not need to be determined first, and then the information corresponding to the bare chip is searched through characters or tables, so that the technical problem that the value of wafer data cannot be used by the user is solved, the user can directly determine the association between the electrical failure data and the defect data of the bare chip according to the wafer data, further visually determine the defect reason causing the electrical failure of the bare chip, and the speed and the convenience for analyzing the wafer yield based on the detection result of the user are improved.

The details of one or more embodiments of the application are set forth in the accompanying drawings and the description below to provide a more thorough understanding of the application.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:

FIG. 1 is a block diagram of a terminal hardware structure of a method for processing wafer data according to an embodiment of the invention;

FIG. 2 is a flow chart illustrating a method for processing wafer data according to an embodiment of the invention;

FIG. 3 is a schematic view of a wafer map in accordance with one embodiment of the present invention;

FIG. 4 is a schematic view of a wafer map of another embodiment of the present invention;

FIG. 5 is a schematic diagram of a die image according to an embodiment of the invention;

fig. 6 is a block diagram of a wafer data processing apparatus according to an embodiment of the present invention.

Detailed Description

For a clearer understanding of the objects, aspects and advantages of the present application, reference is made to the following description and accompanying drawings.

Unless defined otherwise, technical or scientific terms used herein shall have the same general meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The use of the terms "a" and "an" and "the" and similar referents in the context of this application do not denote a limitation of quantity, either in the singular or the plural. The terms "comprises," "comprising," "has," "having," and any variations thereof, as referred to in this application, are intended to cover non-exclusive inclusions; for example, a process, method, and system, article, or apparatus that comprises a list of steps or modules (elements) is not limited to the listed steps or modules, but may include other steps or modules (elements) not listed or inherent to such process, method, article, or apparatus. Reference throughout this application to "connected," "coupled," and the like is not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Reference to "a plurality" in this application means two or more. "and/or" describes an association relationship of associated objects, meaning that three relationships may exist, for example, "A and/or B" may mean: a exists alone, A and B exist simultaneously, and B exists alone. In general, the character "/" indicates a relationship in which the objects associated before and after are an "or". The terms "first," "second," "third," and the like in this application are used for distinguishing between similar items and not necessarily for describing a particular sequential or chronological order.

The method embodiments provided in the present embodiment may be executed in a terminal, a computer, or a similar computing device. For example, the method is executed on a terminal, and fig. 1 is a block diagram of a terminal hardware structure of the method for processing wafer data according to the embodiment. As shown in fig. 1, the terminal may include one or more processors 102 (only one shown in fig. 1) and a memory 104 for storing data, wherein the processor 102 may include, but is not limited to, a processing device such as a microprocessor MCU or a programmable logic device FPGA. The terminal may also include a transmission device 106 for communication functions and an input-output device 108. It will be understood by those of ordinary skill in the art that the structure shown in fig. 1 is merely an illustration and is not intended to limit the structure of the terminal described above. For example, the terminal may also include more or fewer components than shown in FIG. 1, or have a different configuration than shown in FIG. 1.

The memory 104 may be used to store a computer program, for example, a software program and a module of an application software, such as a computer program corresponding to the wafer data processing method in the embodiment, and the processor 102 executes the computer program stored in the memory 104 to execute various functional applications and data processing, i.e., to implement the method. The memory 104 may include high speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include memory located remotely from the processor 102, which may be connected to the terminal over a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

The transmission device 106 is used to receive or transmit data via a network. The network described above includes a wireless network provided by a communication provider of the terminal. In one example, the transmission device 106 includes a Network adapter (NIC) that can be connected to other Network devices through a base station to communicate with the internet. In one example, the transmission device 106 may be a Radio Frequency (RF) module, which is used to communicate with the internet in a wireless manner.

In the chip field, the chip manufacturing process usually includes steps of wafer manufacturing, wafer coating, wafer lithography, doping impurities, wafer testing, and chip packaging. After the wafer (wafer) is subjected to photolithography and doping, a plurality of grid-shaped dies (die) are formed, and electrical characteristics of each die need to be detected by a probe test or the like to determine whether the die meets electrical requirements, and an electrical failure type of a failed die and a defect type causing the electrical failure. Because the number of bare chips of each wafer is huge, the analysis process of the wafer detection result is relatively complex, and many wafer data in the detection result cannot be fully utilized, so that the important value of the wafer data cannot be exerted. Based on this, the invention provides a method for processing wafer data, so as to improve the analysis speed of the wafer detection result and the utilization rate of the wafer data.

Referring to fig. 2, fig. 2 is a flowchart illustrating a method for processing wafer data according to an embodiment of the invention.

In one embodiment, a method for processing wafer data includes:

s202: a wafer map of a target wafer is acquired, and the wafer map is divided into a plurality of bare chip areas.

Illustratively, a wafer map of a target wafer established in advance is acquired, and the wafer map refers to a display image established in a computer device and used for displaying information such as the shape, size, orientation and observation point of the target wafer. Specifically, the wafer map is divided into a plurality of die regions, each die region corresponding to a die in the target wafer. Wherein the die comprises the whole chip area of the complete design and a partial dividing groove area between adjacent chips.

Referring to fig. 3, fig. 3 is a schematic diagram of a wafer map according to an embodiment of the invention.

In one embodiment, a plurality of scribe line regions (reticles) are also provided in the wafer map for dividing the target wafer as a whole. Each scribe line region is in turn divided into a plurality of die regions. As shown in fig. 3, the grid defined by the black grid lines is the scribed line region, and the grid defined by the white grid lines is the die region.

In the embodiment of the present application, a function of selecting different wafers may be provided to a user in the user interface, so that the user may select or switch to a target wafer of interest in the user interface.

S204: and respectively determining the electrical failure type and at least one defect type corresponding to each bare chip in the target wafer.

Each die in the target wafer is inspected, for example, by needle touch, optical methods, etc., to determine the type of electrical failure and the type of defect for each die. Wherein, the electrical failure means that the electrical characteristics of the die do not meet the requirements of the die, and the type of the electrical failure includes but is not limited to different reasons causing the die to fail. For example, in a wafer test (CP), the failure causes due to different electrical test parameters may be set to different failure types, such as bins commonly used in CP tests, for example, the failure causes due to the failure of the electrical test parameter scan may be classified as a type of bin, and the failure causes due to the failure of the electrical test parameter leakage current may be classified as a type of bin. The defect type refers to a type corresponding to a defect in a die, and the defect may be classified based on a generation cause, generation time, generation process, and influence on a wafer. Specifically, the defect types include physical foreign matter defects, chemical contamination defects, pattern defects, crystal defects, and the like. The physical foreign matter defect refers to the existence of abnormal redundant objects on the surface or inside of the wafer, such as micro dust, process residues, abnormal reaction products, and the like; chemical contamination defects refer to the existence of chemical residues on the wafer, such as chemicals or organic solvents; the pattern defect refers to the defect of the pattern of the wafer, such as abnormal imaging in the imaging or etching process, mechanical scratch deformation, color abnormality caused by uneven thickness, and the like; the crystal defects refer to defects in the crystal structure, such as structural defects existing in the wafer itself, or process defects such as slip lines and stacking faults.

In one embodiment, the defect type is a process defect, i.e., a defect type associated with a process flow in which a wafer is manufactured. Based on the type of process defect, the process flow that generated the process defect may be determined. The manufacturing process of the wafer comprises deoxidation and purification, crystal bar manufacturing, wafer slicing, wafer polishing, wafer coating, photoetching, crystal doping and the like, and the types of wafer defects generated in different manufacturing processes are different. For example, if the process defect type is mechanical damage, it indicates that the process defect is generated during wafer slicing or polishing; if the process defect type is the presence of internal impurities, it indicates that the process defect is generated during the deoxidation purification and the manufacture of the crystal bar.

S206: and respectively setting identification information matched with the electrical failure type and identification information matched with at least one defect type in a plurality of die areas in the wafer map.

For example, after determining the electrical failure type and the defect type corresponding to each die, the above information of each die is associated to the corresponding die area in the wafer map. The correlation method comprises the following steps: and setting identification information matched with the electrical failure type, setting identification information matched with the defect type, and setting the identification information in the corresponding bare chip area.

Specifically, the step of setting the identification information matched with the electrical failure type to the corresponding bare chip area includes: acquiring an electrical failure type of the bare chip, and setting identification information based on the electrical failure type; and determining the position of the corresponding bare chip area in the wafer map based on the position of the bare chip in the target wafer, and finally setting the identification information to the bare chip area to which the position belongs.

Specifically, the identification information includes, but is not limited to, color identification, shape identification, and the like, and is used for distinguishing different electrical failure types and different defect types on the visual display. More specifically, the identification information may further include information such as an identification belonged die region for determining the electrical failure type and a die region corresponding to the defect type, and an identification position for determining a specific position of the defect point in the wafer map.

Referring to fig. 4, fig. 4 is a schematic diagram of a wafer map according to another embodiment of the invention.

In one embodiment, after determining the die area of the wafer map, the electrical failure type and defect type of the wafer are further displayed in the wafer map in an identifying manner. As shown in fig. 4, determining the electrical failure type of each die region based on different color fills (different color fills are indicated by different shades in the figure), wherein each color of the color fills corresponds to one electrical failure type; the defect type of each die region is determined based on different shape identifiers, wherein each shape of the shape identifiers corresponds to one defect type.

Specifically, by the method, the bare chip area, the electrical failure type and the defect type are displayed in a wafer map in an overlapping manner, so that a user can visually observe the distribution condition of defect points and the incidence relation between the defect points and the electrical failure type. As shown by the dotted rectangle in fig. 4, the electrical failure type corresponding to the vertical line shaded area can be found intuitively, which is probably caused by the defect type corresponding to the star mark. For example, the star mark corresponds to a defect that is a mechanical scratch, and the defect causes electrical failure of the die to which the scratch belongs.

Specifically, in this embodiment, the setting sequence of the identification information corresponding to the electrical failure type and the identification information corresponding to the defect type is not limited. Taking color filling as an example of identification information corresponding to the electrical failure type, in one specific embodiment, if the layer level of the identification information is associated with the setting sequence, the identification information corresponding to the electrical failure type needs to be set first, and then the identification information corresponding to the defect type needs to be set, so as to avoid that the color filling covers the identification information corresponding to the defect type, which causes that the identification information corresponding to the defect type cannot be displayed; in another specific embodiment, the layer of the identification information corresponding to the defect type may be set to the highest level in advance, so that no matter whether the color filling is set first or later, the identification information corresponding to the defect type is not covered.

It should be noted that the die region in the present embodiment may correspond to a single die or a plurality of dies. In most scenarios, each die needs to be analyzed separately to determine the inspection data of each die and the distribution of multiple dies. However, in some scenarios, such as when it is desired to reduce the amount of data analyzed to increase the analysis speed, a single die region may be set to correspond to multiple dies. In the analysis process, a die area is established in the wafer map based on areas formed by a plurality of dies, and the electrical failure type of the die area is the electrical failure type of the corresponding plurality of dies.

The method includes the steps that a wafer map of a target wafer is obtained, and the wafer map is divided into a plurality of bare chip areas; respectively determining an electrical failure type and at least one defect type corresponding to each bare chip in a target wafer; and respectively setting identification information matched with the electrical failure type and identification information matched with at least one defect type in a plurality of die areas in the wafer map. By setting the corresponding identification information in the bare chip area corresponding to the bare chip, a user can visually observe the electrical failure type and the defect type of each bare chip and the distribution rules of the bare chips under different electrical failure types and defect types, the bare chip to be observed does not need to be determined first, and then the information corresponding to the bare chip is searched through characters or tables, so that the technical problem that the value of wafer data cannot be used by the user is solved, the user can directly determine the association between the electrical failure data and the defect data of the bare chip according to the wafer data, further visually determine the defect reason causing the electrical failure of the bare chip, and the speed and the convenience for analyzing the wafer yield based on the detection result of the user are improved.

In another embodiment, the step of respectively setting the identification information matched with at least one defect type in the plurality of die areas in the wafer map comprises the following steps:

step 1: determining the position of the defect in the wafer map;

step 2: and setting identification information matched with at least one defect type in the bare chip region to which the defect position belongs on the basis of the defect position.

Exemplarily, determining a defect position in a wafer map and a die area to which the defect position belongs according to the position of the defect point on a target wafer; identification information that matches the defect identification is determined and set at the location of the defect within the die region.

According to the method for setting the identification information matched with the defect type at the defect position, the user can visually determine the position and distribution condition of the defect point based on the wafer map, and the speed and convenience for analyzing the wafer yield based on the detection result are improved.

In another embodiment, determining the defect location in the wafer map comprises:

step 1: acquiring the coordinate position of a defect point in a target wafer in an original coordinate system, wherein the original coordinate system comprises a coordinate system based on the target wafer in the process flow during observation;

step 2: and determining the coordinate position of the defect point in the reference coordinate system based on the conversion relation between the original coordinate system and the reference coordinate system corresponding to the wafer map.

Illustratively, the target wafer is detected to obtain the defect points in the target wafer and the coordinate positions of the defect points in the original coordinate system. The original coordinate system refers to a coordinate system for observing the target wafer in each process flow, namely the original coordinate system is associated with physical size information of the target wafer, and each physical point in the target wafer can be mapped to a coordinate under the original coordinate system.

Illustratively, a conversion relation between the original coordinate system and a reference coordinate system of the wafer map is determined, the coordinate position of the defect point in the original coordinate system is converted into the coordinate position in the reference coordinate system, and identification information matched with the defect type of the defect point is further set based on the converted coordinate position. The reference coordinate system refers to an image coordinate system established based on the wafer map, and each image point in the wafer map can be mapped to a coordinate under the reference coordinate system.

Specifically, since the defect point on the target wafer is generated in a plurality of process flows, and the location information of the target wafer in each process flow, such as the placement position and the orientation of the notch, may change, the defect position in the wafer map cannot be determined and the identification information cannot be further set according to the coordinate position of the defect point in the original coordinate system.

Specifically, the reference coordinate system of the wafer map is a fixed coordinate system, and the position of the defect point in the wafer map can be determined only by determining the original coordinate system of the target wafer in each process flow and based on the coordinate conversion relationship.

Specifically, the original coordinate system or the reference coordinate system includes, but is not limited to, a rectangular coordinate system and a polar coordinate system, and the transformation relationship of the coordinate system includes, but is not limited to, a transformation relationship between the rectangular coordinate system and the rectangular coordinate system, a transformation relationship between the polar coordinate system and the polar coordinate system, and a transformation relationship between the rectangular coordinate system and the polar coordinate system.

In this embodiment, the coordinate position of the defect point in the target wafer is converted into the coordinate position in the reference coordinate system through the conversion relationship between the original coordinate system and the reference coordinate system. Through this embodiment, the problem that the positions of the defect points in different process flows change and can not be observed in a unified manner is solved, the positions of the defect points in the target wafer in different process flows are converted into the positions in the wafer map in a unified manner, a user can observe the defect points of all the process flows directly based on the wafer map, the defect points do not need to be observed based on different process flows respectively, and the speed and the convenience for analyzing the wafer yield based on detection results are improved.

In another embodiment, the transformation relationship between the original coordinate system and the reference coordinate system is determined as follows:

step 1: respectively determining original reference coordinates of at least two reference points in an original coordinate system and reference coordinates in a reference coordinate system;

step 2: and determining the conversion relation between the original coordinate system and the reference coordinate system based on the original reference coordinate and the reference coordinate.

Illustratively, at least two reference points in the target wafer are selected, and an original reference coordinate of the reference point in an original coordinate system of the target wafer and a reference coordinate of the reference point in a reference coordinate system of the wafer map are respectively determined, and the reference point with the position saliency characteristic is preferably selected to facilitate calculation of the reference coordinate thereof in the original coordinate system and the reference coordinate system.

Illustratively, the conversion relationship between the original coordinate system and the reference coordinate system is determined by the correspondence relationship between the original reference coordinates and the reference coordinates. Specifically, a stretching parameter, a rotating parameter and a translation parameter between the original reference coordinate and the reference coordinate are determined through the original reference coordinate and the reference coordinate, and then a conversion relation between an original coordinate system and a reference coordinate system is determined.

In one embodiment, the observed center point and the notch point of the target wafer are selected as reference points. The notch point refers to a point position of a notch which is arranged in the manufacturing process of the wafer for conveniently determining the direction of the wafer. It is understood that other corner points and drawing points of the target wafer can be used as reference points for observation of the target wafer.

In another embodiment, the coordinate systems are rectangular coordinate systems. The observation center point of the target wafer is used as the origin of an original coordinate system, the direction of a connecting line from the observation center point to the notch point is used as the X axis of the original coordinate system, the direction perpendicular to the X axis is used as the Y axis of the original coordinate system, the original coordinate system is determined, and the reference coordinate system is determined in the wafer map by the same method.

In another embodiment, the coordinate systems are polar coordinate systems. The method comprises the steps of taking an observation central point of a target wafer as a pole of an original coordinate system, taking the direction of a connecting line from the observation central point to a notch point as a polar axis of the original coordinate system, taking the distance from the observation central point to the notch point as a polar diameter of the original coordinate system, selecting a counterclockwise direction as a positive direction, determining the original coordinate system, and determining the reference coordinate system in a wafer map by the same method.

In the two embodiments, when determining the conversion relationship between the original coordinate system and the reference coordinate system, only the stretching parameters between the coordinate systems need to be determined, thereby simplifying the calculation process of the conversion relationship between the coordinate systems.

In the embodiment, the conversion relation between the original coordinate system and the reference coordinate system is determined by selecting at least two reference points, the coordinate positions of the reference points are easy to obtain, and the conversion relation between the original coordinate system and the reference coordinate system can be determined without complex coordinate operation, so that the calculated amount of wafer data processing is reduced, and the processing efficiency is improved.

In another embodiment, after the step of respectively setting the identification information matching the electrical failure type and the identification information matching the at least one defect type in the plurality of die areas in the wafer map, the method further includes:

step 1: receiving a first operation instruction, wherein the first operation instruction is used for indicating to acquire a bare chip area corresponding to at least one target electrical failure type and/or at least one target defect type;

step 2: all die regions corresponding to the target electrical failure type and/or the target defect type are highlighted in the wafer map.

For example, when a user analyzes the distribution condition of the bare chip region based on the electrical failure type and the defect type, the user may send a first operation instruction through the interactive interface, where the first operation instruction includes a target electrical failure type and a target defect type that the user needs to observe, so as to instruct to acquire the corresponding bare chip region.

Illustratively, the system receives the first operation instruction, acquires all die areas corresponding to the target electrical failure type and the target defect type based on the first operation instruction, and highlights the die areas in the wafer map, so that a user can intuitively analyze the distribution conditions of the die areas. Specifically, the electrical failure type and the defect type are linked with the corresponding bare chip area, and a user selects a control corresponding to the target electrical failure type and the target defect type on the interactive interface, so that the system can be linked to the corresponding bare chip area and highlighted.

More specifically, the system database stores the electrical failure type and the corresponding relationship between the defect type and the corresponding bare chip region, and after the user selects the corresponding control, the system accesses the database to obtain the target electrical failure type and the bare chip region corresponding to the target defect type.

More specifically, the die area is determined by position coordinate information or grid coordinate information in the system database. The position coordinate information refers to coordinate information of at least one reference point of the bare chip area, preferably, a central point or a vertex is used as the reference point, and the grid coordinate refers to a coordinate system established by determining unit length according to grid size. And when the electrical failure type and the corresponding relation between the defect type and the corresponding bare chip area are stored in the system database, the electrical failure type and the defect type are stored in a way of being associated with the corresponding position coordinate information or the grid coordinate information.

In one embodiment, a user selects a target wafer in a left screening bar of the interactive interface, selects at least one process flow, obtains a die region with defects in the process flow, and highlights the die region in a wafer map, so that the user can observe distribution conditions based on the highlighted die region. In another embodiment, a user selects at least one defect type and observes a step condition of a corresponding die region.

In the embodiment, the first operation instruction is received, and all the bare chip regions corresponding to the target electrical failure type and/or the target defect type are directly highlighted based on the first operation instruction, so that the interaction process is simple, and a user does not need to search the corresponding bare chip regions one by one based on the target electrical failure type and/or the target defect type, thereby improving the speed and convenience of analyzing the wafer yield based on the detection result.

step 1: receiving a second operation instruction, wherein the second operation instruction is used for instructing to acquire a die image corresponding to at least one target die area;

step 2: determining a die image associated with the identification information according to the identification information of the target die area;

and step 3: and displaying a die image corresponding to the target die area.

Illustratively, a die image corresponding to the die area is also stored in the system, wherein the die image refers to an image containing the die detail content captured by an image sensing device such as a microscope camera. When a user needs to access the bare chip image corresponding to the bare chip area, a second operation instruction can be sent through the interactive interface, and the second operation instruction includes a target bare chip area which the user needs to observe, so as to instruct to acquire the corresponding bare chip image.

Illustratively, the system receives a second operation instruction, determines identification information corresponding to the target die area based on the second operation instruction, and further acquires and displays a die image corresponding to the identification information.

Specifically, a link relationship exists between the bare chip area and the corresponding bare chip image, and after a user clicks the target bare chip area on the interactive interface, the system links to the corresponding bare chip image and displays the bare chip image.

More specifically, the system database stores a correspondence between identification information of the die region and the die image. After a user clicks a target bare chip area, the system acquires identification information of the target area, and acquires and displays a related bare chip image based on the identification information.

Specifically, when the die image is displayed, a connection relationship also exists between the target die area and the die image, and is used for determining a corresponding relationship between the target die areas and the die images. Based on the connection relationship, the user can intuitively determine the bare chip image corresponding to the currently observed target bare chip area.

In one embodiment, the identification information includes a defect location. In the process of obtaining the bare chip image, if the bare chip has a defect point, obtaining the bare chip image corresponding to the bare chip, and storing the defect position of the defect point in the wafer map and the corresponding bare chip image into a system database in an associated manner.

Referring to fig. 5, fig. 5 is a schematic diagram of a die image according to an embodiment of the invention.

In another embodiment, when the user selects a single or multiple target die areas, the die image corresponding to the target die area as shown in fig. 5 is displayed on the right side of the interactive interface, and the user can zoom in or zoom out the die image by hovering the mouse over the die image and rolling a wheel, so as to observe the image information of the die. Further, the user may also click on the location of the defect in the die image to view detailed information of the defect.

According to the embodiment, the bare chip image corresponding to the target bare chip area is obtained through the second operation instruction, the interaction process is simple, a user does not need to search the corresponding bare chip image based on the target bare chip area to be observed respectively, the bare chip image can be observed directly only by clicking the target bare chip area, and therefore the speed and the convenience of analyzing the wafer yield based on the detection result of the user are improved.

In another embodiment, before receiving the second operation instruction, the method further comprises:

and respectively judging whether each bare chip area has a corresponding bare chip image, and if so, setting preset identification information in the bare chip area.

Illustratively, whether each bare chip area stores a corresponding bare chip image is judged, and if yes, preset identification information is set in the bare chip area. It can be understood that if there is no corresponding die image, other preset identification information different from the preset identification information may be set, or the preset identification information may not be set, so as to distinguish a die region where the die image exists from a die region where the die image does not exist, so as to facilitate a user to determine whether the corresponding die image exists in the die region before obtaining the die image.

Specifically, the system memory stores a correspondence between identification information of the die area and the die image. When judging whether the corresponding bare chip image exists in the bare chip area, firstly, the identification information corresponding to the bare chip area is obtained, and searching and matching are carried out in a system database based on the identification information so as to judge whether the corresponding bare chip image is stored.

The embodiment judges whether the corresponding bare chip image exists in the bare chip area, and identifies the area where the bare chip image exists. When obtaining the die image, a user can firstly determine whether the die image exists in the die area based on the preset identification information, so that invalid operation is avoided.

In another embodiment, the second operation instruction is further used for instructing to acquire failure and defect information corresponding to at least one target die region, and after receiving the second operation instruction, the method further includes:

displaying failure and defect information corresponding to the target bare chip area, wherein the failure and defect information comprises at least one of the following information: defect identification, coordinates of a target wafer area, a failure type, a defect type, a process step of generating a defect, and a source process step of the defect.

Illustratively, the second operating instructions are also for directing the obtaining of failure and defect information for the target die region. And the system receives a second operation instruction, determines failure and defect information corresponding to the target bare chip area based on the second operation instruction and displays the failure and defect information. The failure and defect information includes defect identification, coordinates of a target wafer region, a failure type, a defect generation process step, a defect source process step and the like.

Specifically, a link relation exists between the bare chip area and the corresponding failure and defect information, and after a user clicks the target bare chip area on the interactive interface, the system links to the corresponding failure and defect information and displays the failure and defect information.

In one embodiment, the system receives a second operation instruction, and simultaneously displays the die image corresponding to the target die area and the failure and defect information based on the second operation instruction.

In the embodiment, the failure and defect information corresponding to the target bare chip area is directly displayed through the second operation instruction, a user does not need to search the corresponding failure and defect information in characters or tables according to the target bare chip area, and can directly obtain the failure and defect information only by clicking the target bare chip area, so that the speed and the convenience of analyzing the wafer yield based on the detection result of the user are improved.

In another embodiment, before acquiring the wafer map of the target wafer, the method further includes:

step 1: determining drawing data according to a target wafer, wherein the drawing data at least comprises a wafer diameter, a bare chip size and a wafer edge, and also comprises at least one of a wafer gap and a bare chip offset;

step 2: based on the wafer data, a wafer map is drawn.

Illustratively, based on the observed target wafer, drawing data such as wafer diameter (diameter), die size, wafer edge (margin), wafer notch (notch), and die offset (dieOffsetX) are determined. Wherein the die size includes a die width (dieWidth) and a die height (dieHeight).

Specifically, the edge of the wafer refers to the black frame on the outer edge in fig. 3, and the notch of the wafer refers to a notch that can be visually observed and is used for positioning in the subsequent manufacturing process flows of cutting, testing and the like; the die offset refers to the offset of the die area in the wafer map, and more die areas can be ensured to exist in the wafer map by adjusting the die offset. It will be appreciated that if the number of die regions in the wafer map itself has reached a maximum, then no die offset adjustment may be made.

Illustratively, after the above drawing data is acquired, a wafer map is drawn in a computer device based on the drawing data. Specifically, the step of drawing the wafer map includes: size data, shape data, die data, and the like of the target wafer are determined, and a wafer map is drawn in the map drawing software based on the data. More specifically, a link control of the data is established, and the link control is dragged into a drawing area in the graph drawing software to generate a wafer graph. The graphic drawing software includes, but is not limited to, JMP software, Minitab software, and the like.

According to the embodiment, the drawing data of the wafer map is determined in advance according to the target wafer, and the wafer map is drawn based on the drawing data, so that the accuracy of the wafer map is improved, and the accuracy of analyzing the yield of the bare chips based on the wafer map by a user is further ensured.

In another embodiment, the step of setting the identification information matched with the electrical failure type in the plurality of die areas in the wafer map comprises the following steps:

step 1: obtaining bare chip coordinates of the bare chip under a reference coordinate system corresponding to the wafer map;

step 2: and setting identification information matched with the electrical failure type in the corresponding die area based on the die coordinates.

Illustratively, the type of electrical failure of the die, and corresponding identification information, is predetermined. In the setting process of the identification information, determining bare chip coordinates of the bare chip under a reference coordinate system corresponding to the wafer map; and setting identification information corresponding to the electrical failure type to a bare chip area to which the bare chip coordinate belongs based on the bare chip coordinate.

Specifically, the step of obtaining die coordinates of the die in the reference coordinate system corresponding to the wafer map includes: selecting a reference point of an observed bare chip, converting the coordinate of the reference point under the original coordinate system into the coordinate under the reference coordinate system based on the conversion relation between the original coordinate system of the target wafer and the reference coordinate system of the wafer image, and taking the coordinate as the coordinate of the bare chip corresponding to the observed bare chip. Preferably, a point having a position-significant feature, such as a center point or an end angle, is used as the reference point.

In one embodiment, the wafer data includes die coordinates and electrical failure types, each of which has corresponding color identifying information. And after the wafer data is obtained, drawing the bare chip area according to the bare chip coordinate and the color identification information corresponding to the bare chip.

In another embodiment, a reference coordinate system is established with the center point of the wafer map as the origin and the lateral and longitudinal directions of the wafer map as coordinate axis directions. It will be appreciated that the center point of the wafer map is typically the die coordinates located in the center die region. If there is a die offset, then coordinate offset compensation needs to be performed on the die coordinates of the central die area.

In another embodiment, after the identification information matching with the electrical failure type is set, a scribe line can be drawn in the wafer map to divide the wafer map into a plurality of scribe line regions (reticules), so that a user can observe different scribe line regions conveniently.

Specifically, the scribe line region is drawn according to the die region. The step of drawing the scribed line region includes: and determining a scribing line area where the central bare chip area is located, and drawing a scribing line in the wafer map further based on the coordinates of the bare chip area where the lower left corner of the scribing line area is located in the reference coordinate system and the size of the scribing line area. For example, as shown in fig. 3, the size of each die region is 1 × 1, the size of each scribe line region is 3 × 4, and the coordinates of the die region to which the lower left corner of the scribe line region where the center die region is located belongs are (-1.5, -2). Due to the rounding requirement, the coordinates of the corresponding decimal point are converted to (-1, -2). Finally, the scribe line area is plotted in the wafer map based on coordinates (-1, -2) and scribe line area size 3 x 4.

The bare chip coordinate is determined through the reference coordinate system, the identification information matched with the electrical failure type is set in the corresponding bare chip area based on the bare chip coordinate, the identification is carried out on the corresponding bare chip area through the correlation between the bare chip coordinate and the identification information, the calculation mode of the bare chip coordinate is simple, and therefore the complexity of setting the corresponding identification information in the bare chip area is reduced.

step 1: judging whether at least one end corner of the bare chip area exists in the wafer area in the wafer map;

step 2: if the identification information exists, the identification information matched with the electrical failure type is set in the bare chip area.

Illustratively, the location of the end corners of the die area is obtained and it is determined whether the end corners are within the wafer area in the wafer map. Further, whether at least one end corner of the bare chip area exists in the wafer area in the wafer map is judged, if yes, the bare chip area is partially or completely located in the wafer area, and identification information matched with the electrical failure type is set in the bare chip area; if the die area does not exist, the die area is completely located outside the wafer area and belongs to the worthless die area, and identification information does not need to be set.

Specifically, the coordinates of the four end angles of the wafer area under the reference coordinate system corresponding to the wafer map are determined, and the distance from the end angle to the center of the wafer map is calculated according to the distance between the coordinates and the center point of the wafer map. Further, comparing the distance with the radius of the wafer area of the wafer map, if the distance is smaller than the radius of the wafer area, indicating that the end angle is located in the wafer area; if the radius is larger than the radius of the wafer area, the end angle is located outside the wafer area. When at least one end corner of the die area exists in the wafer area, the identification information is set for the die area.

Specifically, since the scribe line region is similar to the die region and has a problem of crossing the edge of the wafer region, it is necessary to determine whether the scribe line region is partially or entirely located in the wafer region, so as to eliminate an invalid scribe line region that does not belong to the wafer region. The method of determining whether the scribe line region is partially or fully located within the wafer region is similar to the die region, i.e., determining the end angle of the scribe line region and determining whether the end angle is located within the wafer region. If at least one end angle is located in the wafer area, the scribed line area is partially or completely located in the wafer area, and the scribed line area needs to be drawn; if the end angle does not exist in the wafer area, the scribing area is completely outside the wafer area and belongs to a non-valuable scribing area, and drawing is not needed.

Specifically, if at least one bare chip area in all bare chip areas in the scribe line area is partially or completely located in the wafer area, it indicates that the scribe line area is partially or completely located in the wafer area, and the scribe line area needs to be drawn.

In this embodiment, whether the bare chip area is partially or completely located in the wafer area of the wafer map is determined by the end angle position, and identification information is set for the bare chip area partially or completely located in the wafer area, so that the bare chip area not belonging to the wafer area is excluded, and thus identification of the worthless bare chip area is avoided.

In another embodiment, after the setting of the identification information matching the electrical failure type in the plurality of die areas in the wafer map, the method further includes:

and cutting the wafer map based on the edge of the wafer area in the wafer map.

Illustratively, after the step of setting the identification information matched with the electrical failure type is completed, the wafer map is cut according to the edge data of the wafer area, so that only the wafer area part is reserved.

Specifically, since the wafer map is drawn based on the edge data of the wafer area, the edge data of the wafer area is already stored in the system memory in advance. And obtaining edge data by accessing the corresponding storage address, and cutting the wafer map based on the edge data.

In the embodiment, the wafer map is cut through the edge data to obtain the target wafer map only including the wafer region, and the invalid part not belonging to the wafer region is removed, so that a user can conveniently and visually analyze the wafer map, and the analysis speed is improved.

It should be noted that the steps illustrated in the above-described flow diagrams or in the flow diagrams of the figures may be performed in a computer system, such as a set of computer-executable instructions, and that, although a logical order is illustrated in the flow diagrams, in some cases, the steps illustrated or described may be performed in an order different than here.

In this embodiment, a device for processing wafer data is further provided, and the device is used to implement the foregoing embodiments and preferred embodiments, and details are not repeated for what has been described. The terms "module," "unit," "subunit," and the like as used below may implement a combination of software and/or hardware for a predetermined function. Although the means described in the embodiments below are preferably implemented in software, an implementation in hardware, or a combination of software and hardware is also possible and contemplated.

Fig. 6 is a block diagram of a wafer data processing apparatus according to the present embodiment, and as shown in fig. 6, the apparatus includes:

an obtaining module 10, configured to obtain a wafer map of a target wafer, where the wafer map is divided into a plurality of bare chip areas;

a determining module 20, configured to determine an electrical failure type and at least one defect type corresponding to each die in a target wafer respectively;

a setting module 30, configured to set identification information matched with the electrical failure type and identification information matched with at least one defect type in a plurality of die areas in a wafer map, respectively;

the setting module 30 is further used for determining the defect position in the wafer map;

setting identification information matched with at least one defect type in a bare chip region to which the defect position belongs on the basis of the defect position;

the setting module 30 is further configured to obtain a coordinate position of a defect point in the target wafer in an original coordinate system, where the original coordinate system includes a coordinate system based on which the target wafer is observed in the process flow;

determining the coordinate position of the defect point in the reference coordinate system based on the conversion relation between the original coordinate system and the reference coordinate system corresponding to the wafer map;

the setting module 30 is further configured to determine an original reference coordinate of the at least two reference points in the original coordinate system and a reference coordinate in the reference coordinate system, respectively;

determining a conversion relation between an original coordinate system and a reference coordinate system based on the original reference coordinate and the reference coordinate;

the setting module 30 is further configured to obtain die coordinates of the die in a reference coordinate system corresponding to the wafer map;

setting identification information matched with the electrical failure type in the corresponding bare chip area based on the bare chip coordinate;

a setting module 30, configured to determine whether at least one end corner of the die region exists in the wafer region in the wafer map;

if the type of the electrical failure exists, setting identification information matched with the type of the electrical failure in the bare chip area; the processing device of the wafer data also comprises a first operation module;

the first operation module is used for receiving a first operation instruction, and the first operation instruction is used for indicating to obtain a bare chip area corresponding to at least one target electrical failure type and/or at least one target defect type;

highlighting all die regions corresponding to the target electrical failure type and/or the target defect type in the wafer map;

the processing device of the wafer data also comprises a second operation module;

the second operation module is used for receiving a second operation instruction, and the second operation instruction is used for indicating to acquire a die image corresponding to at least one target die area;

determining a die image associated with the identification information according to the identification information of the target die area;

displaying a die image corresponding to the target die area;

the second operation module is further configured to display failure and defect information corresponding to the target bare chip area, where the failure and defect information includes at least one of the following information: defect identification, coordinates of a target wafer area, a failure type, a defect generation process step and a defect source process step;

the processing device of the wafer data also comprises a judging module;

the judging module is used for respectively judging whether each bare chip area has a corresponding bare chip image, and if so, setting preset identification information in the bare chip area;

the processing device of the wafer data also comprises a drawing module;

the drawing module is used for determining drawing data according to the target wafer, wherein the drawing data at least comprises the diameter of the wafer, the size of a bare chip and the edge of the wafer, and also comprises at least one of a wafer gap and a bare chip offset;

drawing a wafer map based on the wafer data;

the processing device of the wafer data also comprises a cutting module;

and the cutting module is used for cutting the wafer map based on the edge of the wafer area in the wafer map.

The above modules may be functional modules or program modules, and may be implemented by software or hardware. For a module implemented by hardware, the modules may be located in the same processor; or the modules can be respectively positioned in different processors in any combination.

There is also provided in this embodiment an electronic device comprising a memory having a computer program stored therein and a processor arranged to run the computer program to perform the steps of any of the above method embodiments.

Optionally, the electronic apparatus may further include a transmission device and an input/output device, wherein the transmission device is connected to the processor, and the input/output device is connected to the processor.

Optionally, in this embodiment, the processor may be configured to execute the following steps by a computer program:

s1, acquiring a wafer map of the target wafer, wherein the wafer map is divided into a plurality of bare chip areas;

s2, respectively determining the electrical failure type and at least one defect type corresponding to each bare chip in the target wafer;

and S3, respectively setting identification information matched with the electrical failure type and identification information matched with at least one defect type in a plurality of bare chip areas in the wafer map.

It should be noted that, for specific examples in this embodiment, reference may be made to the examples described in the foregoing embodiments and optional implementations, and details are not described again in this embodiment.

In addition, in combination with the method for processing wafer data provided in the foregoing embodiment, a storage medium may also be provided in this embodiment. The storage medium having stored thereon a computer program; the computer program, when executed by a processor, implements a method of processing wafer data as in any of the above embodiments.

It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to be limiting. All other embodiments, which can be derived by a person skilled in the art from the examples provided herein without any inventive step, shall fall within the scope of protection of the present application.

It is obvious that the drawings are only examples or embodiments of the present application, and it is obvious to those skilled in the art that the present application can be applied to other similar cases according to the drawings without creative efforts. Moreover, it should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another.

The term "embodiment" is used herein to mean that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the present application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is to be expressly or implicitly understood by one of ordinary skill in the art that the embodiments described in this application may be combined with other embodiments without conflict.

The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the patent protection. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present application shall be subject to the appended claims.

Claims

1. A method for processing wafer data, comprising:

2. The method as claimed in claim 1, wherein the setting of the identification information matching the at least one defect type in the die areas of the wafer map respectively comprises:

determining the position of a defect in the wafer map;

3. The method of claim 2, wherein the determining the defect location in the wafer map comprises:

4. The method as claimed in claim 3, wherein the transformation relationship between the original coordinate system and the reference coordinate system is determined as follows:

5. The method as claimed in claim 1, wherein the step of setting the identification information matching the electrical failure type and the identification information matching the at least one defect type in the plurality of die regions in the wafer map further comprises:

6. The method as claimed in claim 1, wherein the step of setting the identification information matching the electrical failure type and the identification information matching the at least one defect type in the plurality of die regions in the wafer map further comprises:

displaying the die image corresponding to the target die area.

7. The method as claimed in claim 6, wherein the step of receiving the second operation command further comprises:

8. The method as claimed in claim 6, wherein the second operation command is further used for instructing to obtain failure and defect information corresponding to at least one of the target die areas, and the receiving the second operation command further comprises:

9. The method as claimed in claim 1, wherein the step of obtaining the wafer map of the target wafer further comprises:

and drawing the wafer map based on the wafer data.

10. The method as claimed in claim 1, wherein the setting of the identification information matching the electrical failure type in the die areas of the wafer map comprises:

11. The method as claimed in claim 1, wherein the setting of the identification information matching the electrical failure type in the die areas of the wafer map comprises:

12. The method as claimed in claim 1, wherein the step of setting the identification information matching the electrical failure type in the die areas of the wafer map further comprises:

and cutting the wafer map based on the edge of the wafer area in the wafer map.

13. A wafer data processing apparatus, comprising:

14. An electronic device comprising a memory and a processor, wherein the memory has stored therein a computer program, and the processor is configured to execute the computer program to perform the method of processing wafer data according to any one of claims 1 to 12.

15. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method of processing wafer data according to any one of claims 1 to 12.