CN104376878A - Semiconductor device failure analysis method - Google Patents
Semiconductor device failure analysis method Download PDFInfo
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- CN104376878A CN104376878A CN201410469022.2A CN201410469022A CN104376878A CN 104376878 A CN104376878 A CN 104376878A CN 201410469022 A CN201410469022 A CN 201410469022A CN 104376878 A CN104376878 A CN 104376878A
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- 238000003486 chemical etching Methods 0.000 claims description 4
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Abstract
The present invention relates to the field of semiconductor reliability analysis, particularly to a semiconductor device failure analysis method. According to the present invention, a failure analysis method for the memory is established, and the voltage comparison analysis on the connection through holes at the failure region and the peripheral region, and the analysis on the voltage comparison analysis result are performed to detect the adjacent region failure problem caused by the redundancy replacing memory region defect being subjected to reliability testing or actual use of the flash memory; and analysis is performed on the redundancy replaced information during the reliability failure so as to provide the strong analysis basis for the reliability failure problem caused by the replacement of the redundancy circuit and provide the analysis and improvement direction for the reduction of the reliability failure rate.
Description
Technical field
The present invention relates to semiconductor reliability analysis field, particularly relate to a kind of method that semiconductor device failure is analyzed.
Background technology
Along with flash memory (Flash Memory) storage unit is constantly towards the future development of high integration and high capacity, storer manufacturing process is more and more loaded down with trivial details, storer occurs that the possibility of defect also promotes thereupon in the fabrication process, in order to compensate the physical imperfection of the storage unit produced in manufacture process, redundancy (Redundancy) circuit is adopted to substituted for the region of this defect to realize repairing (Repair) out of order storage unit in usual On-Wafer Measurement process, thus the memory property improved as high integration memory device and chip yield.But, after the reliability testing of certain hour or number of times, normal region near this defect physically still existed can affect, thus cause integrity problem, namely because the replacement of redundant circuit improves reliability failures rate.
Current failure analysis (FA) technology can only go according to electrical fail address to analyze physical failure pattern, if when On-Wafer Measurement does not record redundancy replacement information or cannot obtain this information, this region just cannot be known whether because the replacement of redundant circuit in wafer sort causes the inefficacy of reliability.Unfavorable to the analysis of the basic reason of reliability failures problem, be also difficult to the direction that improvement is provided.Thus, how to analyze the memory reliability problem caused due to storage unit redundancy and become a great problem that those skilled in the art face.
Summary of the invention
Flash memory user is actual use or do endurance (Endurance) reliability testing time, be the process repeatedly writing (Program) and erasing (Erase).For the defective region be replaced, actual physics is also present in this storage array, the process of erasing can have the effect of soft-erase (soft Erase) always to this region to the voltage added by the tagma (bulk) of whole device, but the action of write does not almost affect this region, threshold voltage is made to become more and more lower like this, electric leakage (leakage) becomes large, thus observes this to the exception being replaced region by the voltage-contrast of connecting through hole.
The method that semiconductor device failure is analyzed, it is characterized in that, described method comprises:
There is provided a tool defective inefficacy sample;
Determine the physical location that described defect is residing on described inefficacy sample;
Front reduction process is carried out to described inefficacy sample, all to be exposed by the connecting through hole being positioned at described physical location and closing on this physical location;
Voltage-contrast analysis is carried out, to obtain the token image of the connecting through hole of exposure to the described connecting through hole exposed;
Judge whether it is because redundant circuit replaces the described defect caused according to described token image;
If because redundant circuit replaces the described defect caused, be then optimized the redundant arithmetic of described inefficacy sample.
Above-mentioned semiconductor device failure analysis method, wherein, described method also comprises:
The physical location that described defect is residing on described inefficacy sample is determined by the method for the method and/or dynamic hotspot failure analysis that adopt electrical property failure analysis.
Above-mentioned semiconductor device failure analysis method, wherein, described method also comprises:
The method of described inefficacy sample being carried out to the analysis of described employing electrical property failure obtains described defect physical location residing on described inefficacy sample;
If can not determine the physical location that described defect is residing on described inefficacy sample, then continue to adopt the method for described dynamic hotspot failure analysis to determine the physical location that described defect is residing on described inefficacy sample.
Above-mentioned semiconductor device failure analytical approach, wherein, described method also comprises:
The inefficacy sample that described inefficacy sample is ineffective part after actual use or adopts the mode of reliability testing to obtain.
Above-mentioned semiconductor device failure analysis method, wherein, described method also comprises:
Confirm whether it exists exception by the bright-dark degree of the image judging described continuously arranged some connecting through holes.
Above-mentioned semiconductor device failure analysis method, wherein, described method also comprises:
If in the image of described continuously arranged some connecting through holes, the image bright-dark degree being positioned at the connecting through hole of described physical locations and the image bright-dark degree being positioned at the connecting through hole closing on described physical locations there are differences, then the image confirming to be positioned at the connecting through hole of described physical locations exists abnormal.
Above-mentioned semiconductor device failure analysis method, wherein, described method also comprises:
When there is the different connecting through hole figure of brightness in the image of described continuously arranged some connecting through holes, and the brightness being positioned at the figure of the connecting through hole of non-physical position is when being better than the figure of the connecting through hole being positioned at described physical locations, then there is physical imperfection in the connecting through hole place being positioned at described physical locations.
Above-mentioned semiconductor device failure analysis method, wherein, described method also comprises:
Under the condition being less than 1kv, scanning electron microscope or focused beam Electronic Speculum is adopted to carry out described voltage-contrast analysis to described inefficacy sample.
Above-mentioned semiconductor device failure analysis method, wherein, described method also comprises:
Adopt grinding technics and chemical etching process to carry out described front reduction process to described inefficacy sample successively, to remove the part metals interconnection layer being arranged in described inefficacy sample, and stop on described connecting through hole.
Above-mentioned semiconductor device failure analysis method, wherein, described method also comprises:
Again carry out thinning to wafer after obtaining described token image, to obtain the true picture of physical imperfection;
Wherein, it is abnormal if occur in described token image, the image of continuously arranged some connecting through holes exists, although then confirm that described physical imperfection is replaced by redundant circuit, after actual use, bring integrity problem because redundant circuit at least affects described close region.
The present invention establishes a kind of method of failure analysis, by with detect storage area defect that flash memory replaces due to redundancy through reliability testing or actual use after the Problem of Failure of close region that causes.Analyze the information that redundancy is replaced in reliability failures, the reliability failures problem that the replacement for redundant circuit causes provides strong analysis foundation, and the reduction of reliability failures rate is provided to the direction analyzed and improve.
Concrete accompanying drawing explanation
Fig. 1 is the process flow diagram causing Reliability Problems Analysis method for memory product redundancy;
Fig. 2 is the structural representation that the thinning rear connecting through hole of storage unit occurs;
Fig. 3 utilizes scanning beam to carry out the structural representation of voltage-contrast analysis to connecting through hole;
Fig. 4 is connecting through hole light levels change structural representation after scanning beam scanning.
Embodiment
Below in conjunction with accompanying drawing and specific embodiment, the present invention is further illustrated, but not as limiting to the invention.
The invention provides a kind of method, integrity problem memory product redundancy caused with dissecting needle.First, actual effect sample reliability failures sample being provided or obtaining through test, then according to method of the present invention, the defective addresses of inefficacy sample is located, comprise electrical property failure analysis and dynamic hotspot analysis, after getting physical imperfection address, under adopting the low acceleration environment of scanning beam of scanning electron microscope or focused ion beam Electronic Speculum, voltage-contrast analysis is carried out to connecting through hole, the connecting through hole of continuum becomes clear illustrates it is that redundant circuit replaces the integrity problem caused, this type of integrity problem can be solved by improving redundant arithmetic, if not, then that other integrity problems cause, then continue other failure analysis process.By this method, the reliability failures problem that the replacement for redundant circuit causes provides strong analysis foundation, and the reduction of reliability failures rate is provided to the direction analyzed and improve.
The specific embodiment of the present invention is:
1) provide inefficacy sample, preferably, this inefficacy sample returns sample or reliability testing inefficacy sample for client.
2) physical location that failed areas is residing in memory array is determined, preferably, first electrical property failure analysis (Electrical Failure Analysis is adopted, be called for short EFA) method determination failed areas physical location in memory arrays, the electrical property failure analysis namely in process flow diagram shown in Fig. 1.
3) if obtain the physical location of failed areas in memory array smoothly by electrical property failure analytical approach, then carry out step 5), otherwise, carry out step 4).
4) if described physical location cannot be obtained by electrical property failure analysis, then the mode of dynamic hotspot (dynamical hotspot) is adopted to obtain the physical location of failed areas.Also the method for dynamic hotspot can be directly adopted to obtain the physical location of failed areas in storer.
5) thinning above-mentioned failed areas and neighboring area thereof, its metal interconnection layer thinning and dielectric layer, preferably, as shown in Figure 2, thinning employing cmp (Chemical MechanicalPolishing, be called for short CMP) and the method for chemical etching, thinning connecting through hole 1 (Contact hole the is called for short CT) appearance ending at failed areas and neighboring area thereof and have.
6) voltage-contrast analysis is carried out, preferably, adopt scanning electron microscope (Scanning ElectronMicroscope, be called for short SEM) or focused ion beam (Focused Ion Beam, being called for short FIB) scanning beam 2 of Electronic Speculum carries out voltage-contrast (Voltage Contrast to connecting through hole under low accelerating voltage (~ 1KV) condition, be called for short VC) analyze, as shown in Figure 3.
Preferably, after carrying out above-mentioned processing step, namely after above-mentioned voltage-contrast analytical procedure, also again can carry out reduction process to above-mentioned inefficacy sample, to obtain the physical imperfection image of the defect of this inefficacy sample, and after this physical imperfection image is analysed and compared, to be optimized the device architecture of the corresponding physical locations of subsequent product, to reduce the risk that subsequent product produces defect further.
7) above-mentioned voltage-contrast analysis result is analyzed, as shown in Figure 4, 3 representatives do not have to become bright connecting through hole, 4 represent the bright connecting through hole of the rear change of scanning beam scanning, even if 6 expressions scan through scanning beam, still could not become bright through hole, the namely failed areas that causes of redundant circuit of the present invention, surrounding many through holes all become bright and this failed areas does not work, explanation is the integrity problem because redundant circuit causes, now can solve this type of integrity problem by the redundant arithmetic improved in wafer sort, otherwise carry out step 8).
8) if do not occur that around described failed areas, many connecting through holes all become bright continuously, then illustrate it is other integrity problems, now proceed other failure analysis methods.
In sum, first the present invention adopts electrical property failure analytical approach to determine to inefficacy sample the position that its failed areas is residing in storage array, if electrical property failure analytical approach cannot measure the position of failed areas in storage array, the mode of dynamic hotspot is then adopted to obtain the physical location of inefficacy, electrical property failure analysis and dynamic hotspot method are all state of the art, do not repeat at this, then adopt the thinning failed areas of method and the neighboring area thereof of chemical grinding and chemical etching, metal interconnection layer and the dielectric layer of failed areas that thinning is, until connecting through hole occurs, then under adopting the scanning beam low accelerating voltage condition of scanning electron microscope or focused ion beam Electronic Speculum, voltage-contrast analysis is carried out to connecting through hole, carry out judgement to analysis result to identify, if do not occur that many connecting through holes become bright continuously, then illustrate that this failed areas is not the integrity problem because redundant circuit causes, carry out other error analyses, if there are many connecting through holes continuously to become bright, and can physical imperfection be observed, and become bright continuously, dim connecting through hole is had inside through hole, then explanation is the integrity problem because redundant circuit causes, now can solve this type of integrity problem by the redundant arithmetic improved in wafer sort.
It should be appreciated by those skilled in the art that those skilled in the art are realizing described change case in conjunction with prior art and above-described embodiment, do not repeat at this.Such change case does not affect flesh and blood of the present invention, does not repeat them here.
Above preferred embodiment of the present invention is described.It is to be appreciated that the present invention is not limited to above-mentioned particular implementation, the equipment wherein do not described in detail to the greatest extent and structure are construed as to be implemented with the common mode in this area; Any those of ordinary skill in the art, do not departing under technical solution of the present invention ambit, the Method and Technology content of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or being revised as the Equivalent embodiments of equivalent variations, this does not affect flesh and blood of the present invention.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solution of the present invention protection.
Claims (10)
1. a method for semiconductor device failure analysis, it is characterized in that, described method comprises:
There is provided a tool defective inefficacy sample;
Determine the physical location that described defect is residing on described inefficacy sample;
Front reduction process is carried out to described inefficacy sample, all to be exposed by the connecting through hole being positioned at described physical location and closing on this physical location;
Voltage-contrast analysis is carried out, to obtain the token image of the connecting through hole of exposure to the described connecting through hole exposed;
Judge whether it is because redundant circuit replaces the described defect caused according to described token image;
If because redundant circuit replaces the described defect caused, then improve the redundant arithmetic of described inefficacy sample.
2. semiconductor device failure analytical approach according to claim 1, is characterized in that, described method also comprises:
The physical location that described defect is residing on described inefficacy sample is determined by the method for the method and/or dynamic hotspot failure analysis that adopt electrical property failure analysis.
3. semiconductor device failure analytical approach according to claim 2, is characterized in that, described method also comprises:
The method of described inefficacy sample being carried out to the analysis of described employing electrical property failure obtains described defect physical location residing on described inefficacy sample;
If can not determine the physical location that described defect is residing on described inefficacy sample, then continue to adopt the method for described dynamic hotspot failure analysis to determine the physical location that described defect is residing on described inefficacy sample.
4. semiconductor device failure analytical approach according to claim 1, is characterized in that, described method also comprises:
The inefficacy sample that described inefficacy sample is ineffective part after actual use or adopts the mode of reliability testing to obtain.
5. semiconductor device failure analytical approach according to claim 1, is characterized in that, described method also comprises:
Confirm whether it exists exception by the bright-dark degree of the image judging described continuously arranged some connecting through holes.
6. semiconductor device failure analytical approach according to claim 5, is characterized in that, described method also comprises:
If in the image of described continuously arranged some connecting through holes, the image bright-dark degree being positioned at the connecting through hole of described physical locations and the image bright-dark degree being positioned at the connecting through hole closing on described physical locations there are differences, then the image confirming to be positioned at the connecting through hole of described physical locations exists abnormal.
7. semiconductor device failure analytical approach according to claim 6, is characterized in that, described method also comprises:
When there is the different connecting through hole figure of brightness in the image of described continuously arranged some connecting through holes, and the brightness being positioned at the figure of the connecting through hole of non-physical position is when being better than the figure of the connecting through hole being positioned at described physical locations, then there is physical imperfection in the connecting through hole place being positioned at described physical locations.
8. semiconductor device failure analytical approach as claimed in claim 1, it is characterized in that, described method also comprises:
Under the condition being less than 1kv, scanning electron microscope or focused beam Electronic Speculum is adopted to carry out described voltage-contrast analysis to described inefficacy sample.
9. semiconductor device failure analytical approach as claimed in claim 1, it is characterized in that, described method also comprises:
Adopt grinding technics and chemical etching process to carry out described front reduction process to described inefficacy sample successively, to remove the part metals interconnection layer being arranged in described inefficacy sample, and stop on described connecting through hole.
10. semiconductor device failure analytical approach as claimed in claim 1, it is characterized in that, described method also comprises:
Again carry out thinning to wafer after obtaining described token image, to obtain the true picture of physical imperfection.
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105044105A (en) * | 2015-06-08 | 2015-11-11 | 公安部四川消防研究所 | Method for analyzing reliability of circuit conductor |
| CN105699410A (en) * | 2016-01-28 | 2016-06-22 | 武汉新芯集成电路制造有限公司 | Nondestructive positioning method for GOI failure point and GOI failure analysis method |
| CN108010556A (en) * | 2017-11-23 | 2018-05-08 | 长江存储科技有限责任公司 | A kind of method for the small defect failure address for being used to be accurately positioned large-size device |
| CN112285611A (en) * | 2020-09-18 | 2021-01-29 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | Device failure positioning analysis method |
| CN113393422A (en) * | 2021-05-14 | 2021-09-14 | 深圳米飞泰克科技有限公司 | Method and device for determining probe card abnormity, terminal equipment and storage medium |
| CN114023366A (en) * | 2021-04-20 | 2022-02-08 | 苏州鲲腾智能科技有限公司 | Preparation method of three-dimensional memory failure analysis sample |
| CN114399508A (en) * | 2022-03-25 | 2022-04-26 | 杭州广立微电子股份有限公司 | Wafer data processing method and device, electronic device and storage medium |
| US11984176B2 (en) | 2021-05-27 | 2024-05-14 | Changxin Memory Technologies, Inc. | Method and apparatus of testing word line to detect fault after repair |
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105044105A (en) * | 2015-06-08 | 2015-11-11 | 公安部四川消防研究所 | Method for analyzing reliability of circuit conductor |
| CN105699410A (en) * | 2016-01-28 | 2016-06-22 | 武汉新芯集成电路制造有限公司 | Nondestructive positioning method for GOI failure point and GOI failure analysis method |
| CN105699410B (en) * | 2016-01-28 | 2018-05-29 | 武汉新芯集成电路制造有限公司 | A kind of lossless localization method of GOI failpoints and GOI failure analysis methods |
| CN108010556A (en) * | 2017-11-23 | 2018-05-08 | 长江存储科技有限责任公司 | A kind of method for the small defect failure address for being used to be accurately positioned large-size device |
| CN112285611A (en) * | 2020-09-18 | 2021-01-29 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | Device failure positioning analysis method |
| CN112285611B (en) * | 2020-09-18 | 2024-06-18 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | Device failure positioning analysis method |
| CN114023366A (en) * | 2021-04-20 | 2022-02-08 | 苏州鲲腾智能科技有限公司 | Preparation method of three-dimensional memory failure analysis sample |
| CN113393422A (en) * | 2021-05-14 | 2021-09-14 | 深圳米飞泰克科技有限公司 | Method and device for determining probe card abnormity, terminal equipment and storage medium |
| CN113393422B (en) * | 2021-05-14 | 2022-03-22 | 深圳米飞泰克科技股份有限公司 | Method and device for determining probe card abnormity, terminal equipment and storage medium |
| US11984176B2 (en) | 2021-05-27 | 2024-05-14 | Changxin Memory Technologies, Inc. | Method and apparatus of testing word line to detect fault after repair |
| CN114399508A (en) * | 2022-03-25 | 2022-04-26 | 杭州广立微电子股份有限公司 | Wafer data processing method and device, electronic device and storage medium |
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| CN104376878B (en) | 2018-08-03 |
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