KR100244916B1 - Analysis method for a wafer defect - Google Patents

Abstract

The present invention relates to a semiconductor wafer defect analysis method capable of easily analyzing defects generated on a wafer on which a semiconductor device manufacturing process has been performed.

The present invention provides a semiconductor wafer defect analysis method for analyzing a defect of a wafer on which a multilayer film quality is formed by a semiconductor device manufacturing process, the step S2 of addressing a defect formed on the wafer; Step S4 of removing the protective film formed on the defect, step S6 of marking the addressed defect, step S8 of preparing the specimen by cutting the marked defect and the specimen with a transmission electron microscope (TEM). It includes the step S10 to shoot.

Therefore, there is an effect of improving the reliability of the analysis results of defects in the analysis process.

Description

Semiconductor Wafer Defect Analysis Method

The present invention relates to a semiconductor wafer defect analysis method, and more particularly to a semiconductor wafer defect analysis method that can easily analyze the defects generated on the wafer in which the semiconductor device manufacturing process has been performed.

In a semiconductor device manufacturing process, a specific circuit is formed by repeatedly performing a wafer processing process such as an oxidation process, a photolithography process, a diffusion process, and a metal process on a silicon wafer, followed by a wire bonding process and A semiconductor device is manufactured by performing a molding process.

However, after the wafer processing step, a large number of defects (D effects) occur on the wafer due to various causes. That is, a pattern bridge phenomenon in which a pattern and a pattern formed on a wafer are connected, a poor etching quality of a film formed on a wafer, a defect on an opening of a contact hole connecting a device and a device, or a wiring Various problems, such as disconnection, arise.

Since the semiconductor device having the above-mentioned problems may be inevitably malfunctioned after being manufactured as a semiconductor device, each chip constituting the wafer by performing an analysis process on the wafer where the wafer processing process has been performed After checking and selecting whether the chip is defective, the reproducible chip is repaired among the defective chips, and the run in which the defective chips are produced is taken early to prevent the production of the defective chips.

In the past, the semiconductor wafer defect analysis method includes a microscope in which an operator first selects a wafer having the lowest defect among the wafers released in the lowest yield run, and scans a pattern formed on the wafer by scanning an electron beam. Analytical work using a microscope or scanning electron microscope (SEM) was performed.

However, in recent years, highly integrated semiconductor devices with more than 16 MBIT Dynamic Random Access Memory (DRAM) have defects such as D-defects, oxygen precipitates, and crystal defects such as COP (Crystal Originated Particles), which have not been a problem in the past. Since the defects cannot be analyzed by the past methods, the defects are analyzed by wet etching and the laser method (OPP (Oxygen Precipitate Profile)) is completed. A method of analyzing defects on a semiconductor device is used.

First, in the method using the first wet etching method, the operator first selects the wafer having the lowest defect among the wafers released in the lowest yield run in the preliminary inspection, and then forms a multilayer on the wafer using a specific chemical. It is a fracture test that is sequentially etched and analyzed by SEM.

In the second OPP method, the operator first selects the wafer having the lowest defect among the wafers released in the lowest yield run, and then helium (He) laser on the film formed in multiple layers on the wafer. Project (Laser). At this time, if there is no crystal defect on the wafer, the laser penetrates the wafer, and if there is a crystal defect, the laser is scattered at a particular angle. In this case, the operator is a non-destructive test method that analyzes the crystal defect by analyzing the scattered angle.

In addition, the method of analyzing the defect source on the third completed semiconductor device, first, in the pre-inspection, the operator uses the chip cut from the wafer having the lowest defect among the wafers discharged in the lowest yield run. Form. Subsequently, the defective semiconductor device is electrically energized by addressing the defect position according to whether electricity is supplied to the finished semiconductor device, and then the multilayer film quality formed on the wafer is sequentially etched using chemicals, and again, SEM is used. How to analyze defects.

However, the first conventional method is inefficient because the entire wafer surface must be inspected, and the probability of defect inspection is very low. In addition, crystal defects and oxide-related defects are destroyed when the etching process is performed, and there is a problem in that the defects of the vertical structure cannot be analyzed.

In addition, the second method has a problem that the scanning area is very small, only the inside of the wafer can be analyzed, and the types of defects cannot be distinguished.

In addition, the third method could address the location of the defect according to whether electrical current was supplied, but the problem of not being able to analyze the defect of the vertical structure by etching the film quality laminated on the semiconductor device using the chemical as in the first method. There was this.

An object of the present invention is to provide a semiconductor wafer defect analysis method capable of analyzing the defect of the vertical structure by identifying the point of the defect formed on the wafer on which the semiconductor device manufacturing process has been performed.

1 is a view for explaining an embodiment of a semiconductor wafer defect analysis method according to the present invention.

The semiconductor wafer defect analysis method according to the present invention for achieving the above object is a semiconductor wafer defect analysis method for analyzing the defect of a wafer having a multi-layered film formed by a semiconductor device manufacturing process, on the wafer Step S2 of addressing the formed defect, step S4 of removing the protective film formed on the addressed defect, step S6 of marking the addressed defect, and cutting the marked defect into a specimen. S8 step and the step S10 to shoot the specimen with a transmission electron microscope (TEM).

The step S2 of addressing the defect formed on the wafer is performed by a bit map test, and the step S4 of removing the protective film formed on the addressed defect is preferably performed by a wet etching method.

In addition, the step S6 of marking the addressed defect and the step S8 of preparing the specimen by cutting the marked defect is preferably performed by using a focus ion beam (FIB) using an ion source.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a view for explaining an embodiment of a semiconductor wafer defect analysis method according to the present invention.

Referring to FIG. 1, first, as in the prior art, the operator first selects a wafer having the lowest defect among the wafers discharged in the run with the lowest yield by the preliminary inspection, and then the defect formed on the wafer in step S2. Address. In other words, by applying a pin (Pin) to the pad (Pad) formed on the wafer to apply a voltage of 3V, 5V, etc. to operate the semiconductor device, the bit map test to address the defect point by analyzing the energized current Perform a Bit Map Test.

Subsequently, the protective film formed on the semiconductor device in step S4 is removed using chemicals.

Subsequently, the defect formed on the semiconductor device is marked by using an FIB (Focus Ion Beam) device which etches an object by applying an ion source to the defect with the numerical value addressed in the step S2 in the step S6 ( Marking).

Next, a TEM sample is prepared by cutting the defects marked on the wafer using FIB in step S8.

Finally, in step S10, the electron beam is transmitted to the medium to enlarge the pattern and the defect of the vertical structure formed on the cut sample using a TEM capable of enlarging the state of the medium.

Therefore, according to the present invention, after accurately addressing a defect point formed on a semiconductor device through a bitmap test, a vertical structure of the defect can be analyzed, and a TEM sample capable of analyzing the entire pattern can be prepared and analyzed. This progresses, since the pattern and defects can be prevented from being destroyed when etching a plurality of films formed on the wafer using conventional chemicals, thereby improving the reliability of the analysis process.

Although the present invention has been described in detail only with respect to the described embodiments, it will be apparent to those skilled in the art that various modifications and variations are possible within the technical scope of the present invention, and such modifications and modifications are within the scope of the appended claims.

Claims (5)

A semiconductor wafer defect analysis method of analyzing a defect of a wafer on which a multilayer film quality is formed by performing a semiconductor device manufacturing process, the method comprising: addressing a defect formed on the wafer; Step S4 of removing the protective film formed on the addressed defect; S6 step of marking the addressed defect; S8 step of producing a specimen by cutting the marked defects; And photographing the specimen with a transmission electron microscope (TEM). Semiconductor wafer defect analysis method comprising a. The method of claim 1, wherein the S2 step of addressing a defect formed on the wafer is performed by a bit map test. The method of claim 1, wherein the removing of the protective layer formed on the addressed defect is performed by a wet etching method. The method of claim 1, wherein the marking of the addressed defect is performed using a focus ion beam (FIB). The method of claim 1, wherein the step S8 of cutting the marked defect to prepare a specimen is performed by using a focus ion beam (FIB).

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