JP2001319955A - Luminescence analysis method and apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a means for specifying a luminescent transistor position from the influence on a luminescence shape observed from the surface of the semiconductor and estimating the luminescence shape. SOLUTION: A three-dimensional location relation around a luminescent position is reproduced from layout data, and the luminescent point is shifted thereby. Then a location in which the luminescent point agrees with the real luminescent image shape is obtained, and the accuracy in agreement is enhanced by changing the luminescent shape.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a luminescence analysis method and apparatus for specifying the position of a luminescence point detected by a luminescence microscope.

[0002]

2. Description of the Related Art The manufacture of a semiconductor device includes a wafer processing step of forming a semiconductor device on a so-called silicon substrate, and an assembling step of separating the semiconductor device from the substrate and packaging the semiconductor device. Of these, the wafer processing step includes large steps such as element isolation, element formation, and wiring, and these large steps comprise the end of processing such as film formation, exposure, and etching. Before and after each processing, steps such as cleaning and quality inspection are added as necessary. For this reason, the number of processing steps in the wafer processing step reaches several hundreds.

On the other hand, the processing size of these steps is often 1
It is micrometer or less, and the processing accuracy is about one-tenth of the processing size, and fine and high-precision processing is performed. Therefore, if any trouble occurs in the processing apparatus, the required processing accuracy cannot be maintained, resulting in a failure. As described above, hundreds of processes are performed in the manufacturing process of a semiconductor device. Therefore, when a defect occurs, it takes a lot of time to find a process that caused the defect. Therefore, since defective products continue to be generated until the cause of the failure is specified and the countermeasures are completed, it is extremely important to reduce the analysis time of the failure cause. It is required to establish a semiconductor manufacturing method incorporating the semiconductor device.

For a memory product such as a DRAM (Dynamic Random Access Memory), a method of so-called fail bit analysis as disclosed in Japanese Patent Application Laid-Open No. Sho 61-243378 is known. This is a method of classifying the array pattern of fail bits (bids that do not work) in the memory into several basic patterns, associating a defective portion that causes the basic pattern with each basic pattern, and facilitating observation of the defective portion. .

However, system LSIs other than memory products (La
In rge Scale Integrated Circuit), the fail bit analysis method can be applied only to the built-in memory unit, and cannot be applied to other logical operation units. In a system LSI, a method called emission analysis disclosed in Japanese Patent Application Laid-Open No. 5-251538 or the like is used. This is to obtain a clue for the cause analysis of a defect by detecting light emission at a defective portion of a semiconductor device or at a portion where a load is applied due to the presence of a defect. For example, a light emitting point is cut by FIB (Focused Ion Beam), and by observing its cross-sectional shape, what kind of abnormality has occurred is analyzed.

[0006] The defective portion is identified by the above-mentioned light emission analysis, and the FIB
In general, the steps up to the physical analysis such as the one shown in FIG. 2 proceed. First, the electrical characteristics are measured by a probe inspection, the contents of the failure are journalized, and a target wafer for failure analysis is specified.

Next, a representative chip to be analyzed is selected with reference to a foreign matter map or a shape defect map inspected by the foreign matter inspection device or the appearance inspection device. At this stage, at present, the chip is cut and temporarily sealed, and a test pattern is applied from a tester to perform light emission analysis. At this time, the light-emitting transistor is identified by referring to CAD (Computer Aided Design) data and the light-emission status. However, actually, the light-emission portion may not match the defective portion that is the cause of the defect.

This depends on what is the cause of the defect. If the transistor itself is defective, the light-emitting portion coincides with the defective portion. Often it is a place that goes back along the route. In such a case, it is necessary to check the signal transmission by using an EB (Electron Beam) tester (electron beam tester) alone or in combination with opening a window in the FIB, and to trace the wiring path. By this work, when the defective part is identified,
Observe the appearance of the defect using a scanning electron microscope (SEM), and perform structural and elemental analysis to try to identify the cause of the defect.

In the failure analysis in such a process, it is important to select a chip to be analyzed. Actually, however, a specific experience is required to determine whether the analysis location of the selected chip is a typical failure of a wafer or its lot. Often, only the person can judge.

[0010] Therefore, a technique for making it possible to grasp the distribution of light emission on the wafer surface is described in Japanese Patent Application Laid-Open No. 10-4128. As shown in FIG. 3, light is emitted by a device in which a light-emitting microscope composed of an optical microscope 54 and a CCD (Charged Coupled Device) camera 1 is combined with an auto-prober 56 that automatically operates probing with a probe card 55. It has a function of acquiring the wafer map 12. This makes it possible to grasp the macroscopic distribution state of the light emitting points in the wafer, to determine whether the distribution has a specific pattern or to be unevenly distributed in a specific region, and to be effective in selecting a chip to be analyzed. Information can be obtained.

[0011] At this time, the materials of the lecture of the 10th Semiconductor Workshop, “Failure Analysis of Semiconductors by Optical Technology and Semiconductor X-Light,” “Novel Hot Electron Analyzing Technology us
As described in "ingPHEMOS & THEMOS = Novell Hot Electron Analyzing Technology Using Fimos and Temos," it has been found that the emission spectrum differs depending on the cause of emission, and the spectrum is important in the field of failure analysis. The spectrum is generally expected to be utilized in the future.
It is said that light emission at the longer wavelength side is at a forward pn junction and light emission due to an intermediate wavelength between them at an intermediate potential at the gate of the transistor.

Therefore, by obtaining the light-emitting wafer map 12, selecting a chip to be analyzed, and further selecting an analysis point, and performing a spectrum analysis as shown in FIG. This gives guidance on the analysis procedure as to what analysis should be performed next.
This is a fault in the wiring system when the spectrum is at an intermediate wavelength. In this case, the light emitting point and the defective point do not generally coincide with each other. This is because the light emitting point and the defective point coincide with each other, and if the point is analyzed, the cause of the defect can be analyzed.

[0013]

The light emission phenomenon occurs in the transistor portion, which is in the lowermost layer of the LSI,
There are several wiring layers on it. Accordingly, as shown in FIG. 6, light from the light emitting point 3 of the transistor 36 is reflected or diffracted by the wiring 35 and reaches the surface, which is detected by the light emitting microscope and captured as an image by the CCD camera.

For this reason, even when the number of light emission points is one, the light emission may appear as several points. On the contrary, the appearance of the light emission changing as shown in FIGS. Estimating the position of the light emitting point from the wiring pattern is performed by an experienced analysis person. If any operator of the light-emitting microscope can make the same determination, increase the accuracy of specifying a defective transistor, and estimate the light-emitting cause, the analysis efficiency can be improved.

[0015]

In a real semiconductor device, the light emission which is cut off by an upper wiring layer and observed on the surface is a simulation of a light path which is affected by the wiring layer in consideration of reflection or diffraction. Is used to perform tracking in the reverse direction and specify a light emitting point.

[0016]

Embodiments of the present invention will be described below with reference to the drawings.

A method shown in FIG. 1 is employed as a light emission simulation for tracking a light emission path in reverse. This is CA
From the D data, input the transistor arrangement and wiring pattern information of the area where light emission occurs, first place a light emitting point at the end of the drain region of the transistor part, scan it around the actual light emitting position, Simulates the light emission state that is reflected or diffracted from the surface and emitted from the surface.
It finds the position of the light emitting point close to the actual light emission. On top of that, the shape of the light emitting point is scanned as a point in the transistor area to simulate the light emitting state on the surface,
A simulation in the case where the shape of light emission is expanded from a point to a region at the drain end is also executed to obtain a state closest to the actual light emission state. This makes it possible to specify the transistor that emits light and estimate the shape of the light emission.

Here, the shape of the light emission is estimated as follows. Generally, light emission due to transistor system failure is point emission, and light emission due to wiring system failure is surface emission near the gate in the drain region. This is because if the shape can be grasped, this also helps in estimating the cause of the defect. At this stage, an actual light emission image and a layout diagram of the transistors indicating the light emission positions are displayed on the screen 72, and the estimated light emission shape, the coordinates of the light emission point at which the light emission occurs, and the light emission point belong. The displayed circuit block, the transistor number in the circuit block, and the data of the estimated light emission shape are displayed. The data of the emission spectrum analysis is added to this to estimate the cause of the failure. Here, on the screen 72, data on the emission spectrum information, the estimated failure factor, and the analysis means to be executed next are displayed.

Further, a layout diagram and a logic diagram around the light emitting point may be displayed. This is particularly useful in the case of a wiring system failure because it is necessary to trace the wiring route back to the logic. By combining the emission spectrum information with the identification of the light-emitting transistor and the estimation of the light-emitting shape in this way, the estimation accuracy is increased, and the determination of whether or not the light-emitting portion can be directly processed and analyzed in the analysis of the next process can be reliably performed. It can be. If the result of the actual analysis indicates that the transistor system is defective, an analysis in which the next physical processing is performed and the light emitting portion is observed can be immediately started, and the analysis time can be reduced.

[0020]

According to the present invention, it is possible to improve the accuracy of estimating the cause of a failure by adding spectrum information after facilitating the specification of a light emitting transistor, and to shorten the analysis time by obtaining an effective guideline for failure analysis. Becomes possible.

[Brief description of the drawings]

FIG. 1 is a flowchart of an analysis process showing a method of failure analysis using light emission simulation.

FIG. 2 is a flowchart of a failure analysis step using a conventional emission microscope.

FIG. 3 is a front view showing a schematic configuration of a conventional light emitting wafer map acquisition system.

FIG. 4 is a graph showing a relationship between light emission intensity and wavelength to show a difference in spectrum due to a defect which is a factor of light emission.

FIG. 5 is a flowchart of a failure analysis step of performing spectrum analysis after obtaining a light emitting wafer map.

FIG. 6 is a cross-sectional view of the LSI showing that an optical path of light emission is affected by an upper wiring layer.

[Explanation of symbols]

1… CCD camera 12… Light emitting wafer map 35… Wiring
36 ... Transistor 37 ... Lighting point 38 ... Wiring 39
... Transistor 40 ... Source 41 ... Gate 42 ... Drain 43 ... Emission point 44 ... Emission 45 ... Emission
46 ... Wiring 47 ... Emission spectrum 54 ... Optical microscope 55 ... Probe card 56 ... Auto prober 5
7… dark box 58… control PC 59… CRT 72… screen

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Toshiyuki Majima 5-2-1, Kamimizuhoncho, Kodaira-shi, Tokyo F-term in Hitachi Semiconductor Co., Ltd. (Reference) 2G032 AA00 AC00 AC08 4M106 AA01 AA02 AB09 BA10 CA21 CA38 CA40 DA15

Claims (5)

[Claims] 1. A method for applying a voltage to a semiconductor device in which a plurality of wiring layers and a plurality of transistor portions are formed and analyzing a state of light emission generated in the semiconductor device, the method comprising: A transistor that emits light by simulating a reflection or diffraction phenomenon on an optical path of light emission from the transistor portion of the semiconductor device reflected or diffracted by the upper wiring layer based on pattern information of the transistor and the wiring; A light emission analysis method characterized by identifying the light emission. 2. A method for analyzing a state of light emission generated in a semiconductor device by applying a voltage to a semiconductor device having a plurality of wiring layers and a plurality of transistor portions, the method comprising: An optical path of light emission from the transistor portion of the semiconductor device, which is reflected or diffracted by the upper wiring layer, is arranged on the wiring portion based on the pattern information of the transistor and the wiring. Scan the light emitting point and deform the light emitting point shape to simulate the shape of the light emission reaching the surface layer, and find the conditions that make the shape of the light emission closest to the observed actual light emission shape A light emitting transistor is specified and a light emitting shape is inferred. 3. A method for applying a voltage to a semiconductor device in which a plurality of wiring layers and a plurality of transistor portions are formed and analyzing a state of light emission generated in the semiconductor device, the method comprising: The light path of light emission from the transistor portion of the semiconductor device reflected or diffracted by the upper wiring layer is determined based on the pattern information of the transistor and the wiring. By scanning the points and deforming the light emission point shape, simulating the shape of the light emission reaching the surface layer, and finding the conditions under which the shape of the light emission becomes the shape closest to the observed actual light emission shape A light emission analysis method characterized by identifying a light emitting transistor, estimating a light emission shape, and adding light emission spectrum information to estimate a light emission cause. 4. A light emission analyzer comprising a stage means, a prober means or a socket means, an optical system means, an image detection means, a light emission analysis means and a controller means, wherein said light emission analysis means comprises a plurality of wirings. The light path of light emission from the transistor portion of the semiconductor device, which is reflected or diffracted by the upper wiring layer of the plurality of wiring layers of the semiconductor device in which the layer and the plurality of transistor portions are formed, the pattern information of the transistor and the wiring; A light emission analyzing apparatus characterized in that a light emitting transistor is specified by simulating a reflection or diffraction phenomenon based on the light emitting transistor. 5. A light emission analyzer comprising a stage means, a prober means or a socket means, an optical system means, an image detection means, a light emission analysis means and a controller means, wherein said light emission analysis means comprises a plurality of wirings. The light path of light emission from the transistor portion of the semiconductor device, which is reflected or diffracted by the upper wiring layer of the plurality of wiring layers of the semiconductor device in which the layer and the plurality of transistor portions are formed, the pattern information of the transistor and the wiring; The light emission point in the transistor portion is changed based on the above, and the shape of the light emission reaching the surface layer when the light emission point shape is deformed is obtained by simulation, and the light emission shape obtained by the simulation is the image. By obtaining the conditions that make the shape closest to the actually observed light emission shape via the detection means, Performed analogy specific and emission shape data, by adding the emission spectrum information, emission analysis apparatus characterized by estimating the emission causes.