CN112331573B

CN112331573B - Electric leakage analysis method of three-dimensional memory and three-dimensional memory

Info

Publication number: CN112331573B
Application number: CN202011128587.6A
Authority: CN
Inventors: 范光龙; 陈金星
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2020-10-20
Filing date: 2020-10-20
Publication date: 2021-08-03
Anticipated expiration: 2040-10-20
Also published as: CN112331573A

Abstract

The embodiment of the disclosure discloses a leakage analysis method of a three-dimensional memory and the three-dimensional memory, wherein a stacking structure of the memory comprises insulating layers and K conductive gate layers which are alternately stacked, K is a positive integer, a first end of the stacking structure is provided with a first step area, and a second end of the stacking structure is provided with a second step area; the method comprises the following steps: forming K conductive first plugs in one-to-one corresponding contact with the K gate layers in the first step area; forming a plurality of conductive second plugs in one-to-one corresponding contact with the plurality of gate layers in the second step area; wherein, a gate layer which is not contacted with the second plug is arranged between adjacent gate layers which are contacted with the second plug; injecting conductive first particles into the first plug, and injecting conductive second particles into the second plug; wherein the first particles have an electrical property opposite to that of the second particles; and carrying out electrical detection on the first plug, and carrying out electric leakage analysis based on a detection result.

Description

Electric leakage analysis method of three-dimensional memory and three-dimensional memory

Technical Field

The embodiment of the disclosure relates to the technical field of semiconductors, in particular to a three-dimensional memory and leakage analysis thereof.

Background

In manufacturing a three-dimensional memory device, a step region is formed at an end portion of a stack structure including insulating layers and conductive gate layers alternately stacked, a contact hole connected to the gate layer is formed by etching on each step, and then the contact hole is filled to form a conductive plug (contact), thereby drawing an electrical signal of the gate layer by using the conductive plug.

As the demand for data storage density is increasing, the number of layers of the stacked structure is increasing. When the contact hole is formed, in order to ensure that the gate layer in the lower step relatively close to the substrate can be smoothly led out, the gate layer in the upper step relatively far away from the substrate is easily over-etched (over etch), and a punch through (punch through) occurs, so that the adjacent two gate layers are short-circuited through the conductive plug, and the product yield is reduced.

In the prior art, the analysis accuracy of the contact hole subjected to etching and punching is low, and the quality of the manufactured three-dimensional memory is difficult to ensure.

Disclosure of Invention

The embodiment of the disclosure provides a leakage analysis method of a three-dimensional memory and the three-dimensional memory.

According to a first aspect of the embodiments of the present disclosure, there is provided a leakage analysis method for a three-dimensional memory, where a stacked structure of the memory includes insulating layers and conductive K gate layers that are alternately stacked, K is a positive integer, a first end of the stacked structure has a first step region, and a second end of the stacked structure has a second step region;

the method comprises the following steps:

forming K conductive first plugs in one-to-one corresponding contact with the K gate layers in the first step area;

forming a plurality of conductive second plugs in one-to-one corresponding contact with the gate layers in the second step area; wherein, a gate layer which is not contacted with the second plug is arranged between adjacent gate layers which are contacted with the second plug;

injecting conductive first particles into the first plug, and injecting conductive second particles into the second plug; wherein the first particles have an electrical property opposite to that of the second particles;

and carrying out electrical detection on the first plug, and carrying out electric leakage analysis based on a detection result.

In some embodiments, the electrically testing the first plug and performing leakage analysis based on the testing result includes:

carrying out electron beam detection on the first plug to obtain a detection result; and performing leakage analysis based on the image presented by the first plug in the detection result.

In some embodiments, said performing a leakage analysis based on an image presented by said first plug in said detection result comprises:

when the images presented by two adjacent first plugs in the detection result are the same, one first plug which is in contact with the upper layer grid layer and corresponds to the two adjacent first plugs leaks electricity;

images presented by two adjacent first plugs in the detection result are different, the brightness of the image presented by one first plug is smaller than or equal to a first brightness threshold, and when the brightness of the image presented by the other first plug is larger than or equal to a second brightness threshold, the two adjacent first plugs are not electrified;

when the images presented by two adjacent first plugs in the detection result are different, one first plug presenting the image brightness smaller than or equal to the first brightness threshold value is not leaked with electricity, and the other first plug presenting the image brightness larger than the first brightness threshold value and smaller than the second brightness threshold value is leaked with electricity;

when the images presented by two adjacent first plugs in the detection result are different, one first plug presenting the image brightness which is greater than or equal to the second brightness threshold value is not leaked with electricity, and the other first plug presenting the image brightness which is greater than the first brightness threshold value and less than the second brightness threshold value is leaked with electricity;

wherein the first brightness threshold is less than the second brightness threshold.

In some embodiments, the gate layers comprise a first type gate layer and a second type gate layer; wherein the content of the first and second substances,

the first type gate layer is contacted with the first plug which is not electrically leaked, and the first type gate layer is not electrically connected with the second plug; the first plug which is electrically connected with the first type grid layer and does not leak electricity presents image brightness which is the first brightness threshold value;

the second type gate layer is in contact with the other first plug which is not electrically leaked, and the second type gate layer is electrically connected with the second plug; the first plug which is electrically connected with the second type grid layer and is not electrically leaked presents image brightness which is the second brightness threshold value.

In some embodiments, the implanting conductive first particles into the first plug and implanting conductive second particles into the second plug comprises:

spraying the first particles on the surface of the first plug, and loading a first voltage on the first plug; wherein the first voltage has an electrical property consistent with that of the first particles;

spraying the second particles on the surface of the second plug, and loading a second voltage on the second plug; wherein the electrical property of the second voltage is consistent with the electrical property of the second particles.

In some embodiments, the first particles are electrically positive; the second particles have an electrical property of electronegativity.

In some embodiments, the method further comprises:

when the three-dimensional memory is detected to comprise at least one leaky first plug, detecting the leaky first plug by using a transmission electron microscope to determine a leaky position of the three-dimensional memory.

In some embodiments, the stacked structure is located in a virtual memory block of the three-dimensional memory;

and/or the presence of a gas in the gas,

the stacking structure is located in a storage block of the three-dimensional memory; wherein the memory block is used to perform a memory function.

According to a second aspect of embodiments of the present disclosure, there is provided a three-dimensional memory including:

a stacked structure comprising: the insulating layers and the conductive K gate layers are alternately stacked; the first end of the stacked structure is provided with a first step area, and the second end of the stacked structure is provided with a second step area;

k conductive first plugs which are vertical to the grid layers, are respectively in one-to-one corresponding contact with the K grid layers in the first step area and are used for transmitting control signals;

a plurality of conductive second plugs which are vertical to the grid layers and are in one-to-one corresponding contact with the grid layers in the second step area; a gate layer which is not contacted with the second plug is arranged between adjacent gate layers which are respectively contacted with different second plugs correspondingly;

the first plug and the second plug are used for conducting leakage analysis on the three-dimensional memory.

In some embodiments, the stack structure, the first plug, and the second plug are located within a virtual storage block and/or a storage block of the three-dimensional memory; wherein the memory block is used for storing electric charge.

In the embodiment of the disclosure, in a stacked structure including K gate layers, a conductive first plug is formed in a first step region of the stacked structure corresponding to each gate layer, and a plurality of conductive second plugs in one-to-one contact with the gate layers are formed in a second step region of the stacked structure, wherein a gate layer not in contact with the second plug exists between adjacent gate layers in contact with adjacent second plugs, so that one of the adjacent two gate layers is electrically connected with the first plug and the second plug, and the other gate layer is connected with only the first plug but not the second plug. When the first plug does not leak electricity, the first plug is connected with only one grid layer in the two adjacent grid layers; when the first plug leaks electricity, the leaked first plug is electrically connected with the two adjacent grid layers at the same time.

According to the embodiment of the disclosure, the first particles which are conductive are injected into the first plug, and the second particles which are opposite in electrical property to the first particles are injected into the second plug, so that the electron concentration in the gate layer which is electrically connected with the first plug and the second plug can be increased, and the difference between the electron concentration in the gate layer which is only connected with the first plug but not electrically connected with the second plug can be increased, thereby increasing the difference between the electron concentrations in the adjacent first plugs, so that the electrical detection result of the first plug which is not electrically leaked is different from the detection result of the first plug which is electrically leaked, so that the first plug which is electrically leaked can be visually determined based on the detection result, and the visual analysis effect is good.

In addition, the method provided by the disclosure does not physically damage the three-dimensional memory structure in the detection process, does not need to cause waste of three-dimensional memory products, can directly monitor the electric leakage condition in a manufacturing workshop (FAB, or called clean room), carries out on-line monitoring (inline monitor), and reduces the analysis cost, shortens the analysis time and further can accelerate the process research and development speed compared with the electric leakage analysis through a Transmission Electron Microscope (TEM).

Drawings

FIG. 1a is a partial schematic diagram of a three-dimensional memory including a leaky conductive plug in accordance with an exemplary embodiment;

FIG. 1b is an image obtained by performing a voltage contrast test on the three-dimensional memory shown in FIG. 1 a;

FIG. 2 is a flow diagram illustrating a method for leakage analysis of a three-dimensional memory according to an exemplary embodiment;

FIGS. 3a, 3b, and 3c are schematic diagrams of a three-dimensional memory leakage analysis;

FIG. 4 is a schematic diagram illustrating a method of leakage analysis for a three-dimensional memory, according to an example embodiment;

FIG. 5 is a three-dimensional stored local test result diagram in accordance with an exemplary embodiment;

FIG. 6 is a schematic illustration of another three-dimensional stored local test result in accordance with an exemplary embodiment;

FIG. 7 is a schematic illustration of yet another three-dimensional stored local test result in accordance with an exemplary embodiment;

FIG. 8 is a schematic diagram illustrating a three-dimensional memory in accordance with an exemplary embodiment.

Detailed Description

The technical solutions of the present disclosure will be further explained in detail with reference to the drawings and examples. While exemplary implementations of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

The present invention is more particularly described in the following paragraphs with reference to the accompanying drawings by way of example. Advantages and features of the present disclosure will become apparent from the following description and claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present disclosure.

In the disclosed embodiment, the term "a is connected to B" includes A, B where a is connected to B in contact with each other, or A, B where a is connected to B in a non-contact manner with other components interposed between the two.

In the embodiments of the present disclosure, the terms "first", "second", and the like are used for distinguishing similar objects, and are not necessarily used for describing a particular order or sequence.

The technical means described in the embodiments of the present invention may be arbitrarily combined without conflict.

In the fabrication process of a three-dimensional memory, a stacked structure including a plurality of insulating layers and a plurality of sacrificial layers alternately stacked in sequence is generally formed, and two adjacent sacrificial layers are separated by the insulating layers. Then, an insulating dielectric layer is covered on the edge of the stacked structure in a step shape, and a contact hole (SSCT) is formed in the dielectric layer. The sacrificial layer in the stack structure is replaced by a conductive gate layer to form a gate stack structure of the three-dimensional memory.

In order to reduce the over-etching of the gate layer during the formation of the contact hole, the stacked structure may be divided into an upper region and a lower region when the contact hole is formed in the step region. The upper area is an area corresponding to the upper part of the step-shaped edge of the stacked structure and is an area with smaller depth of the contact hole to be formed; the lower region is a region corresponding to the lower portion of the step-like edge of the stacked structure, and is a region in which the depth of the contact hole to be formed is large. Then, two masks and two etching programs (masks) are respectively adopted to respectively carry out photoetching on the upper area and the lower area.

However, the two masks and the two etching programs are used to respectively perform the photolithography etching on the upper region and the lower region of the stacked structure, which results in a problem of high production cost. Therefore, in order to reduce the production cost, the two photomasks can be combined into one photomask, all contact holes are formed by adopting a one-time etching process after the dielectric layer is subjected to photoetching, and electric leakage analysis is performed on the conductive plugs after the conductive plugs are formed in the contact holes so as to determine whether the quality of the three-dimensional memory meets the requirements.

Referring to fig. 1a, the conductive plug formed in the over-etched contact hole is an abnormal conductive plug. The abnormal conductive plug penetrates through the first gate layer and is connected with the second gate layer. That is, the abnormal conductive plug leaks electricity, so that the first gate layer and the second gate layer are shorted.

FIG. 1b shows a Bright Voltage Contrast (BVC) image obtained by performing a Voltage Contrast (VC) test on the memory shown in FIG. 1 a. Through voltage comparison detection, whether the conductive plug is electrically connected with the grid layer can be determined. Since the abnormal conductive plug is electrically connected to both the first gate layer and the second gate layer, in the bright voltage contrast image, the image presented by the abnormal conductive plug is the same as the image presented by the normal conductive plug (both white or bright), i.e., it is impossible to determine whether the conductive plug leaks electricity through the bright voltage contrast image.

Moreover, as the number of layers of the three-dimensional memory is gradually increased, the thicknesses of the sacrificial layer and the insulating layer are both reduced, and the over-etching problem of the contact hole may be more serious, so that a method for accurately and rapidly analyzing the leakage of the three-dimensional memory is urgently needed.

Fig. 2 is a flow chart illustrating a method for three-dimensional memory leakage analysis according to an example embodiment. The stacking structure of the three-dimensional memory comprises insulating layers and K conductive gate layers which are alternately stacked, wherein K is a positive integer, a first end of the stacking structure is provided with a first step area, a second end of the stacking structure is provided with a second step area, and the first end and the second end of the stacking structure are respectively located at different ends of the stacking structure.

Referring to fig. 2, the method includes the steps of:

s110: forming K conductive first plugs in one-to-one corresponding contact with the K gate layers in the first step area;

s120: forming a plurality of conductive second plugs in one-to-one corresponding contact with the plurality of gate layers in the second step area; wherein, a gate layer which is not contacted with the second plug is arranged between adjacent gate layers which are contacted with the second plug;

s130: injecting conductive first particles into the first plug, and injecting conductive second particles into the second plug; wherein the first particles have an electrical property opposite to that of the second particles;

s140: and carrying out electrical detection on the first plug, and carrying out electric leakage analysis based on a detection result.

The three-dimensional memory may include a three-dimensional NAND gate (3D NAND) memory. The three-dimensional memory can be any one of three-dimensional memories to be subjected to leakage analysis. It should be understood that the three-dimensional memory to be subjected to leakage analysis in the embodiments of the present disclosure is not limited to a device that completes the entire manufacturing process of the three-dimensional memory, and may also include a device structure after the manufacturing process of the stacked structure is completed on a production line.

The three-dimensional memory may include a substrate for supporting the stacked structure. In the first step area or the second step area, for two adjacent steps, the lower step protrudes out of the upper step along the direction parallel to the substrate, wherein the lower step is a step relatively close to the substrate, and the upper step is a step relatively far away from the substrate.

In general, an insulating dielectric layer covering the stacked structure is formed during the fabrication process of the three-dimensional memory, and the upper surface of the dielectric layer may be flush with the upper surface of the stacked structure, or the upper surface of the dielectric layer may be slightly higher than the upper surface of the stacked structure. The lower surface of the dielectric layer is in contact with the substrate and the stacked structure. The lower surface and the upper surface of the dielectric layer are opposite surfaces.

Illustratively, the vertical distance between each gate layer and the substrate is different for K gate layers arranged in parallel and in column. The gate layer with the smallest vertical distance from the substrate may be referred to as a 1 st gate layer, the gate layer with the largest vertical distance from the substrate may be referred to as a kth gate layer, and the gate layers except the 1 st gate layer and the kth gate layer may be numbered sequentially in a direction from the 1 st gate layer to the kth gate layer.

It should be noted that, no matter how the gate layers are numbered in the present disclosure, it is required to ensure that one of the two adjacent gate layers in the stacked structure is electrically connected to the first plug and the second plug at the same time, and the other gate layer is electrically connected to only the first plug but not to the second plug, so that after the first particles are injected into the first plug and the second particles are injected into the second plug, the difference between the electron concentrations of the two adjacent gate layers is large.

For example, one of two adjacent gate layers, which is electrically connected to the first plug and the second plug at the same time, may be referred to as a first gate layer; only one gate layer electrically connected to the first plug and not electrically connected to the second plug may be referred to as a second gate layer.

When the first plug is not leaked, one first plug is electrically connected with one first grid layer or one second grid layer; when the first plugs leak electricity, one first plug is electrically connected with the adjacent first grid layer and the second grid layer at the same time.

S110 may include: forming a first contact hole penetrating through the dielectric layer in the first step region to expose the gate layer; filling the first contact hole to form a first plug.

Note that, in the case where no leakage occurs, each gate layer is electrically connected to a different first plug in the first step region. When etching through occurs in the process of forming the first contact hole, a first plug filled in the first contact hole with the etching through is electrically connected with at least two adjacent gate electrode layers at the same time, and the first plug leaks electricity.

S120 may include: forming a second contact hole penetrating through the dielectric layer in the second step area to expose the gate layer; and filling the second contact hole to form a second plug.

Illustratively, the first contact hole and the second contact hole perpendicular to the stacked structure may be formed by photolithography and etching, the first plug may be formed in the first contact hole by chemical vapor deposition, and the second plug may be formed in the second contact hole by chemical vapor deposition.

When the first contact hole and the second contact hole are formed through photoetching and etching, the same photomask can be used for carrying out imaging processing on the dielectric layer coated with the photoresist so as to simultaneously form a first pattern corresponding to the first contact hole and a second pattern corresponding to the second contact hole in the photoresist covering the dielectric layer, and then the first contact hole and the second contact hole are simultaneously formed through one-time etching.

For example, the first contact hole and the second contact hole may be simultaneously filled to form the first plug in the first contact hole and simultaneously form the second plug in the second contact hole. Thus, the process is simple.

For the K gate layers, the gate layer electrically connected to the second plug is numbered N. It is to be understood that one second plug is electrically connected to only one gate layer, and different second plugs are electrically connected to different gate layers, respectively.

It should be emphasized that, in the same embodiment, the values of N are both positive and odd. Or, in the same embodiment, the values of N are all positive and even numbers. In addition, in the same embodiment, the value of N cannot include both positive odd numbers and positive even numbers. Therefore, the numbers of the gate layers in contact with the second plugs are all positive even numbers. Or the numbers of the grid layers in contact with the second plugs are positive odd numbers. K is a natural number greater than 1.

For example, when the value of N is positive and odd, the first second plug is electrically connected to the first gate layer, the second plug is electrically connected to the third gate layer, and the third second plug is electrically connected to the fifth gate layer.

For another example, when N is a positive even number, the first second plug is electrically connected to the second gate layer, the second plug is electrically connected to the fourth gate layer, and the third second plug is electrically connected to the sixth gate layer.

When K is an odd number, the number of the second plugs formed is (K-1)/2 or (K + 1)/2. When K is an even number, the number of second plugs formed is K/2.

It can be understood that, since the gate layer not connected to the second plug and the at least two insulating layers are further stacked between the two adjacent gate layers connected to the second plug, the depth difference between the two adjacent second contact holes is greater than that between the two adjacent first contact holes, so that the possibility of etch punch-through during formation of the second contact holes is less than that during formation of the first contact holes. Therefore, it can be regarded that no leakage occurs in the second plug.

In the embodiment of the disclosure, the first particles which are conductive are injected into the first plug, and the second particles which are opposite to the first particles in electrical property are injected into the second plug, so that the concentration of electrons in the first gate layer which is electrically connected with the first plug and the second plug is different from the concentration of electrons in the second gate layer which is electrically connected with the first plug only.

When electric leakage occurs, the first electric leakage plug is simultaneously contacted with the first grid layer and the second grid layer, electrons can move between the first grid layer and the second grid layer through the first electric leakage plug, so that the difference between the concentration of the electrons in the first grid layer electrically connected with the first electric leakage plug and the concentration of the electrons in the second grid layer is smaller, and the concentration of the electrons in the first grid layer electrically connected with the first electric leakage plug and the concentration of the electrons in the second grid layer can be regarded as the same.

When leakage does not occur, each first plug is in contact with only one of the first gate layer and the second gate layer, and the difference between the concentration of electrons in the first gate layer and the concentration of electrons in the second gate layer is large.

When the adjacent first gate layer and the second gate layer are electrically insulated, that is, the first plug does not leak electricity, the concentration of electrons in the first gate layer or the concentration of electrons in the second gate layer is greatly different from the number of electrons in the first gate layer and the second gate layer which are electrically connected due to the leakage of the first plug.

Therefore, in the embodiment of the disclosure, by performing the electrical detection on the first plug, since the concentration of electrons in the gate layer electrically connected to the first plug with leakage is different from the concentration of electrons in the gate layer electrically connected to the first plug without leakage, the detection result of the first plug connected to the first gate layer and the second gate layer is different from the detection result of the first plug connected to the first gate layer or the second gate layer. Therefore, the first plug with electric leakage can be visually determined based on the detection result of the electric detection of the first plug, and the visual analysis effect is good.

In addition, the method provided by the disclosure can not physically damage the three-dimensional memory structure in the detection process, does not need to cause waste of three-dimensional memory products, can directly monitor the electric leakage condition in a manufacturing workshop, carries out on-line monitoring, reduces the analysis cost, shortens the analysis time and further can accelerate the process research and development speed compared with the electric leakage analysis through a transmission electron microscope.

In some embodiments, S140 comprises: carrying out electron beam detection on the first plug to obtain a detection result; and performing electric leakage analysis based on the image presented by the first plug in the detection result.

In S140, performing Electron Beam Inspection (EBI) on the first plug may be implemented by an electron Beam Inspection apparatus.

An electron beam inspection apparatus is generally used for defect inspection in a semiconductor device production process, and uses a focused electron beam as an inspection source, and when performing electron beam inspection, the electron beam irradiated on a sample excites secondary electrons in the sample, and the inspection apparatus captures defects by collecting and analyzing the secondary electrons.

The obtained detection result at least comprises: and acquiring an electron beam detection image. The detection result may include an image presented by the first plug with leakage current and an image presented by the first plug with no leakage current, and therefore, the detection result may also include an electron beam detection contrast image.

Referring to fig. 3a, when a conductive third plug is formed corresponding to each gate layer in the second step region instead of the second plug, and the first particles are injected into the first plug and the second particles (e.g., negatively charged electrons) are injected into the third plug, since each gate layer is electrically connected to the first plug and the third plug at the same time, the number of electrons in the upper gate layer and the number of electrons in the lower gate layer in the two adjacent gate layers can be considered to be approximately the same.

Therefore, as shown in fig. 3b, when neither the first plug nor the second first plug leaks current, the concentration of electrons in the gate layer electrically connected to the first plug is approximately equal to the concentration of electrons in the gate layer electrically connected to the second first plug, so that the first plug and the second first plug present the same pattern in the detection result.

Referring to fig. 3c, when the first plug leaks current and the second first plug does not leak current, the first plug is electrically connected to the upper gate layer and the lower gate layer. Therefore, the second particles injected into the upper gate layer and the lower gate layer through the third plugs can flow in the upper gate layer and the lower gate layer through the first plugs, so that the electron concentration in the upper gate layer and the electron concentration in the lower gate layer are still approximately the same. Therefore, in the detection result, the patterns presented by the first leaked first plug and the second first non-leaked plug are still the same.

That is, when the leakage analysis is performed on the three-dimensional memory with the structure shown in fig. 3a, the first plug with the leakage cannot be detected.

In some embodiments, S130 comprises:

spraying first particles on the surface of the first plug, and loading a first voltage on the first plug; wherein the electrical property of the first voltage is consistent with the electrical property of the first particles;

spraying second particles on the surface of the second plug, and loading a second voltage on the second plug; wherein the electrical property of the second voltage is consistent with the electrical property of the second particles.

For example, a high-current electron scattering technology may be introduced on the basis of an electron beam inspection apparatus, first particles are sprayed on the surface of the first plug, and a first voltage is applied to the first plug, so that the first particles enter a gate layer electrically connected to the first plug. And then spraying second particles on the surface of the second plug, and loading a second voltage on the second plug so that the second particles enter the grid layer electrically connected with the second plug.

The first particles may be electrically positive. The first particles may include: a positively charged hole or a positively charged first ionic group. By applying the first voltage, the first particles can move toward the gate layer electrically connected to the first plug under the influence of the electric field force.

The second particles may be negatively charged. The second particles may include: a negatively charged electron or a negatively charged second ion group. By applying the second voltage, the second particles can move toward the gate layer electrically connected to the second plug under the influence of the electric field force.

It will be appreciated that when it is desired to inject positively charged holes into the first plug, this can be achieved by extracting negatively charged electrons from the first plug. Here, the number of negatively charged electrons extracted from the first plug is equal to the number of positively charged holes injected into the first plug.

Hereinafter, description will be given taking as an example that the first particles are positively charged holes, the second particles are negatively charged electrons, and the positively charged particles are injected into the first plugs by extracting the negatively charged electrons from the first plugs. Referring to fig. 4, after injecting the first particles into the first plugs and before injecting the negatively charged electrons into the second plugs, the number of negatively charged electrons in the upper gate layer and the lower gate layer is the same.

After injecting negatively charged electrons into the second plug, since the upper gate layer is not electrically connected to the second plug and the lower gate layer is electrically connected to the second plug, the number of electrons in the lower gate layer is significantly greater than that in the upper gate layer, so that the density of electrons in the lower gate layer is significantly greater than that in the upper gate layer.

It should be noted that the image presented by the first plug depends mainly on the density of electrons in the gate layer electrically connected to the first plug. When the electron density in the grid layer electrically connected with the first plug is higher, the image brightness presented by the first plug is higher; when the density of electrons in the gate layer electrically connected with the first plug is smaller, the brightness of an image displayed by the first plug is smaller.

In some embodiments, the performing leakage analysis based on the image presented by the first plug in the detection result includes:

and when the images displayed by the two adjacent first plugs in the detection result are the same, one first plug which is in contact with the upper layer grid layer in the two adjacent first plugs is subjected to electric leakage.

Referring to fig. 5, when the first plug leaks current, the upper gate layer is electrically connected to the lower gate layer through the first plug, so that the second first plug that does not leak current is also electrically connected to the upper gate layer through the first plug. That is, the density of electrons in the gate layer electrically connected with the first leaky first plug is equal to the density of electrons in the gate layer electrically connected with the second non-leaky first plug. Therefore, in the detection result, the images of the first leaky first plug and the second non-leaky first plug are the same and are the first images.

When the images of the adjacent M first plugs in the detection result are the same, a first plug with electric leakage caused by etching punch-through exists in the adjacent M first plugs, so that the M first gate layers electrically connected with the M first plugs are electrically connected.

For example, in M stacked gate layers connected with M first plugs correspondingly, the M-1 first plugs connected with the upper M-1 gate layers are etched through, and the M-1 first plugs are leaked.

It can be understood that, if the first plug connected to the bottom gate layer of the M gate layers has etched through, it needs to be analyzed in conjunction with the image of the M +1 th first plug.

It is emphasized that, when the stacked structure is formed on a substrate, of two adjacent gate layers, the gate layer relatively far away from the substrate is an upper gate layer, the gate layer relatively close to the substrate is a lower gate layer, and the lower gate layer is located between the upper gate layer and the substrate.

In some embodiments, the performing leakage analysis based on the image displayed by the first plug in the detection result further includes:

the images presented by two adjacent first plugs in the detection result are different, the brightness of the image presented by one first plug is smaller than or equal to a first brightness threshold, and when the brightness of the image presented by the other first plug is larger than or equal to a second brightness threshold, the two adjacent first plugs are not electrified; wherein the first brightness threshold is less than the second brightness threshold.

Referring to fig. 6, when neither of the first plug and the second first plug is leaky, the upper gate layer and the lower gate layer are electrically isolated. After injecting negatively charged electrons into the second plug, since the upper gate layer is not electrically connected to the second plug and the lower gate layer is electrically connected to the second plug, the number of electrons in the lower gate layer is significantly greater than that in the upper gate layer, so that the density of electrons in the lower gate layer is significantly greater than that in the upper gate layer.

That is, the electron density in the upper gate layer electrically connected to the first plug is significantly less than the electron density in the lower gate layer electrically connected to the second first plug. The first plug in the detection result corresponds to the third image, and the second first plug corresponds to the second image. Wherein the brightness of the third image is much less than the brightness of the second image.

the first type of grid layer is contacted with a first plug which is not electrically leaked, and the first type of grid layer is not electrically connected with the second plug; the image brightness presented by the first electricity-tight plug electrically connected with the first grid layer is a first brightness threshold value;

the second type of grid layer is contacted with another first plug which is not electric leakage, and the second type of grid layer is electrically connected with the second plug; the image brightness represented by the first plug electrically connected with the second type grid layer is the second brightness threshold.

Illustratively, the first-type gate layer includes the first plug shown in fig. 6, and the first luminance threshold includes the luminance of the third image. The second type gate layer includes the second first plug shown in fig. 6, and the second luminance threshold includes the luminance of the second image.

The third image may be dark (e.g., black) and the second image may be light (e.g., white).

It is noted that the first image has a luminance greater than the luminance of the third image, and the luminance of the first image is less than the luminance of the second image. The first image may appear gray.

images displayed by two adjacent first plugs in the detection result are different, one first plug with the displayed image brightness larger than or equal to the second brightness threshold value is not leaked with electricity, and the other first plug with the displayed image brightness larger than the first brightness threshold value and smaller than the second brightness threshold value is leaked with electricity.

Referring to fig. 7, for the first plug and the second first plug adjacent to each other, the first gate layer and the second gate layer are electrically connected through the first plug due to the leakage caused by the etching punch-through of the first plug. Thus, in the detection result, the image presented by the first plug is the same as the image presented by the second first plug, and the images are the first images.

For the adjacent second first plug and the third first plug, because the electrons injected into the second gate layer through the second plug are uniformly distributed in the electrically connected first gate layer and the electrically connected second gate layer, and the electrons are not injected into the third gate layer through the second plug, the density of the electrons in the electrically connected gate layer through the second first plug is greater than that in the electrically connected gate layer through the third first plug. Correspondingly, the brightness of the first image presented by the second first plug in the detection result is greater than the brightness of the third image presented by the third first plug. The third first plug presents a third image having a brightness less than or equal to the first brightness threshold.

It should be noted that, when the first plug is etched through to cause leakage, it can be determined whether the second first plug is etched through or not by combining the images respectively presented by the first plug, the second first plug and the third first plug.

Specifically, in this embodiment, since the brightness of the third image displayed by the third first plug is less than or equal to the first brightness threshold, it is known that the third first plug is electrically connected to only one gate layer, and therefore, the second first plug does not penetrate to be electrically connected to the third first plug, i.e., the second first plug does not undergo etching penetration.

For the second first plug and the fourth first plug, since the electrons injected into the second gate layer by the second plug are uniformly distributed in the electrically connected first gate layer and the second gate layer, and the electrons injected into the fourth gate layer by the other second plug are distributed in the fourth gate layer, the sum of the volumes of the first gate layer and the second gate layer is much larger than that of the fourth gate layer, so that the electron density in the gate layer electrically connected with the second first plug is obviously smaller than that in the gate layer electrically connected with the fourth first plug. Correspondingly, the brightness of the first image presented by the second first plug in the detection result is smaller than the brightness of the second image presented by the fourth first plug. The fourth first plug presents a second image having a brightness greater than or equal to the second brightness threshold.

It is noted that the number of first particles implanted into each first plug may be the same and the number of second particles implanted into each second plug may be the same.

In the embodiment of the disclosure, the images displayed by the two adjacent first plugs are analyzed, so that the first plug with electric leakage can be visually determined, and the visibility analysis effect is good.

In some embodiments, the method further comprises:

When the first plugs subjected to etching punch-through are simultaneously and electrically connected with at least three gate layers, or two adjacent first plugs are subjected to etching punch-through, the patterns of the plurality of first plugs electrically connected with the plurality of short-circuited adjacent gate layers are the same. In this case, the plurality of first plugs electrically connected to the plurality of short-circuited adjacent gate layers may be detected by using a transmission electron microscope, so as to determine a specific position where leakage occurs in the first plug.

In a three-dimensional memory chip (die), a plurality of dummy blocks (dummy blocks) and a plurality of memory blocks may be included. The virtual memory block is not used to perform a memory function and the memory block is used to perform a memory function. The structure of the virtual memory block may be the same as the structure of the memory block. Also, the virtual memory block may be prepared simultaneously with the memory block. By monitoring the virtual memory blocks, the quality of the memory blocks can be detected.

The leakage analysis method provided by the present disclosure can be applied to any one or more virtual memory blocks. Alternatively, the leakage analysis methods provided by the present disclosure may be applied to any one or more memory blocks.

In other embodiments, the leakage analysis method provided by the present disclosure may also be applied to: virtual memory blocks and memory blocks. By forming the first conductive plug and the blocking structure in the virtual storage block and the storage block, the number of samples which can be used for conducting electric leakage analysis on the three-dimensional storage is increased, so that the electric leakage condition of the conductive plug on the whole wafer for preparing the three-dimensional storage can be comprehensively detected and analyzed, and the manufacturing research and development period of forming the electric-leakage-free conductive plug can be shortened.

Fig. 8 is a schematic diagram illustrating a three-dimensional memory 100 according to an example embodiment. Referring to fig. 8, the three-dimensional memory 100 includes:

a stacked structure 110, comprising: insulating layers 111 and conductive K gate layers 112 alternately stacked; wherein K is a positive integer, the first end of the stacked structure 110 has a first stepped region 110a, and the second end of the stacked structure 110 has a second stepped region 110 b;

k conductive first plugs 120 perpendicular to the gate layers 112 and in one-to-one contact with the K gate layers 112 in the first step region 110a, respectively, for transmitting control signals;

a plurality of conductive second plugs 130, perpendicular to the gate layer 112, and in one-to-one contact with the gate layers 112 in the second step regions 110 b; wherein, a gate layer not contacting with the second plug 130 exists between adjacent gate layers respectively contacting with different second plugs 130;

the first plug 120 and the second plug 130 are used for performing leakage analysis on the three-dimensional memory 100.

The first end and the second end of the stacked structure 110 may be two ends disposed oppositely. Alternatively, the first end and the second end of the stacked structure 110 may be two ends disposed adjacently.

The constituent material of the insulating layer 111 includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or the like. Illustratively, the constituent material of the insulating layer 111 includes silicon oxide (SiO)₂)。

The gate layer 112 may be made of a material including, but not limited to, metal, alloy, or polysilicon (poly). For example, the gate layer 112 may include: tungsten, nickel, tungsten-nickel alloy, or the like.

Note that the gate layer 112 in fig. 8 includes: a first gate layer 112a and a second gate layer 112 b. The first gate layer 112a is electrically connected to the first plug 120 in the first stepped region 110a, and is electrically connected to the second plug 130 in the second stepped region 110 b. The second gate layer 112b is electrically connected only to the first plug 120, and is not electrically connected to the second plug 130.

By using the three-dimensional memory 100 provided by the embodiment of the disclosure, the first particles can be injected into the first plug 120, the second particles can be injected into the second plug 130, then the first plug 120 is electrically detected, and based on the detection result, the leakage analysis is performed on the three-dimensional memory 100, so that the leakage analysis can be performed intuitively and efficiently, and the visual analysis effect is good.

In addition, carry out electric leakage analysis through the structure that this disclosed embodiment provided, can not carry out the physics to three-dimensional memory structure and destroy, need not to cause three-dimensional memory product extravagant, can directly monitor the electric leakage condition in the manufacturing shop, monitor on producing the line, compare in carrying out electric leakage analysis through transmission electron microscope, reduced the analysis cost, shortened analysis time, and then can accelerate technology research and development speed.

In some embodiments, the three-dimensional memory 100 further comprises: a substrate for supporting the gate stack 110. The substrate may include: silicon wafer, germanium wafer, or Silicon On Insulator (SOI), and the like.

In some embodiments, referring to fig. 8, the stacked structure 110 further includes a core region 110 c. The core region 110c, the first stepped region 110a and the second stepped region 110b are distributed parallel to the plane of the substrate.

A memory string that vertically penetrates the stack structure 100 may also be disposed in the core region 110 c. The control signal transmitted by the first plug 120 is used to control the operations of reading and erasing the charges in the memory string.

In some embodiments, the stack structure 110, the first plug 120, and the second plug 130 are located within a virtual memory block and/or a memory block of the three-dimensional memory 100; the storage block is used for storing electric charge.

Since the stacked structure 110 in the memory block needs to perform a memory function. Therefore, the first plug 120, which is located in the flash, is also used to transmit a control signal to the gate layer 112; the control signal is used for controlling the storage block to store the charges. Therefore, a conductive plug for transmitting the control signal is not required to be additionally formed, and the compatibility with the existing structure is strong.

Further, when the stack structure 110, the first plug 120, and the second plug 130 are disposed in both the dummy memory block and the memory block, the number of samples for performing leakage analysis on the three-dimensional memory is increased, which is beneficial to shortening the development cycle for forming the first plug 120 that is electrically leakage-free.

In the embodiments provided in the present disclosure, it should be understood that the disclosed apparatus, system, and method may be implemented in other ways. The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present disclosure, and all the changes or substitutions should be covered within the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. The leakage analysis method of the three-dimensional memory is characterized in that a stacked structure of the memory comprises insulating layers and K conductive gate layers which are alternately stacked, wherein K is a positive integer, a first end of the stacked structure is provided with a first step region, and a second end of the stacked structure is provided with a second step region;

the method comprises the following steps:

2. The method of claim 1, wherein said electrically testing said first plug and analyzing said leakage current based on said testing comprises:

3. The method of claim 2, wherein said performing a leakage analysis based on an image presented by said first plug in said detection result comprises:

4. The method of claim 3, wherein the gate layers comprise a first type gate layer and a second type gate layer; wherein the content of the first and second substances,

5. The method of claim 1, wherein said implanting first particles that are electrically conductive into said first plug and implanting second particles that are electrically conductive into said second plug comprises:

6. The method of claim 1,

the first particles are electrically positive;

the second particles have an electrical property of electronegativity.

7. The method of claim 1, further comprising:

8. The method of claim 1,

the stacking structure is located in a virtual storage block of the three-dimensional memory;

and/or the presence of a gas in the gas,

9. A three-dimensional memory, comprising:

10. The three-dimensional memory according to claim 9,

the stack structure, the first plug and the second plug are positioned in a virtual storage block and/or a storage block of the three-dimensional memory; wherein the memory block is used for storing electric charge.