CN114706860A - Wafer data processing method, device and storage medium - Google Patents
Wafer data processing method, device and storage medium Download PDFInfo
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Abstract
The application relates to a wafer data processing method, a device and a storage medium, wherein the wafer comprises an invalid bare chip and an effective bare chip, and the mark information of the wafer is information for uniquely identifying the wafer, so that the problem of low wafer yield calculation efficiency in the related technology is solved, and the calculation efficiency of the wafer yield is improved.
Description
Technical Field
The present application relates to the field of computer technologies, and in particular, to a wafer data processing method, apparatus, and storage medium.
Background
Wafer yield is a key parameter for measuring wafer quality by calculating the yield of die (die) within a wafer. Typically, the failure data of the die is stored in a database for easy reading at any time to calculate the yield of the wafer. However, as the integrated circuit manufacturing technology is continuously developed, the diameter of the wafer is continuously increased, the number of the dies is increased, the die failure data needs to occupy a larger storage space, and thus the data amount read during the yield calculation is larger, which results in the reduction of the yield calculation efficiency.
For the problem of low wafer yield calculation efficiency in the related art, no effective solution is provided at present.
Disclosure of Invention
The present embodiment provides a method, an apparatus and a storage medium for processing wafer data, so as to solve the problem of low wafer yield calculation efficiency in the related art.
In a first aspect, a wafer data processing method is provided in this embodiment, including:
the method comprises the steps of determining position information of one type of target die in a wafer, and storing the position information of the target die in association with mark information of the wafer, wherein the wafer comprises two types of invalid dies and valid dies.
In some of these embodiments, the type of the target die is a failed die.
In some of these embodiments, determining location information for a type of target die in a wafer includes: establishing a reference coordinate system on the wafer, and determining the position information of the target die according to the reference coordinate system, wherein the position information of the target die comprises the coordinate information of the target die in the wafer.
In some of these embodiments, the position information of the target dies further includes a die number, wherein the die number is set according to a position of each target die in the wafer.
In some of these embodiments, determining the die number of each target die in the wafer includes:
obtaining circumscribed rectangles of the wafer, and dividing the circumscribed rectangles according to the sizes of the bare chips in the wafer to obtain small rectangles with the sizes of NxM bare chips;
and sequentially numbering according to the positions of the small rectangles in the circumscribed rectangle, and determining the die number of each target die in the wafer according to the obtained number after sequential numbering, wherein N, M is a natural number.
In some of these embodiments, determining location information for a type of target die in a wafer includes:
and traversing to acquire the die number of the target die in the wafer.
In some of these embodiments, after storing the location information of the target die in association with the flag information of the wafer, the method further comprises:
and calculating the yield of the wafer.
In some of these embodiments, calculating the yield of the wafer comprises:
acquiring the total number of the bare chips in the wafer and the number of the target bare chips;
and calculating the yield according to the total number of the dies and the number of the target dies.
In some of these embodiments, calculating the yield of the wafer comprises: and calculating the yield of the interested area in the wafer.
In some of these embodiments, calculating the yield of the region of interest within the wafer comprises:
acquiring position information of a region of interest, and determining the total number of bare chips of the region of interest according to the position information of the region of interest;
determining the number of the target dies in the region of interest according to the position information of the target dies and the position information of the region of interest, and calculating the yield of the region of interest in the wafer according to the total number of the dies in the region of interest and the number of the target dies in the region of interest.
In a second aspect, the present embodiment provides an electronic apparatus, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the wafer data processing method according to the first aspect when executing the computer program.
In a third aspect, in the present embodiment, a storage medium is provided, on which a computer program is stored, which when executed by a processor, implements the wafer data processing method according to the first aspect.
Compared with the related art, the wafer data processing method, the device and the storage medium provided in the embodiment solve the problem of low wafer yield calculation efficiency of the related art and improve the wafer yield calculation efficiency by determining the position information of one type of target bare chip in the wafer and storing the position information of the target bare chip in association with the mark information of the wafer, wherein the type of the bare chip in the wafer is invalid or valid.
The details of one or more embodiments of the application are set forth in the accompanying drawings and the description below to provide a more thorough understanding of the application.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:
FIG. 1 is a schematic view of a wafer according to an embodiment of the present application;
FIG. 2 is a flowchart illustrating a wafer data processing method according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a wafer circumscribing rectangle division in accordance with an embodiment of the present application;
fig. 4 is a schematic view of an annular region of interest in a wafer according to an embodiment of the present application.
Detailed Description
For a clearer understanding of the objects, aspects and advantages of the present application, reference is made to the following description and accompanying drawings.
Unless defined otherwise, technical or scientific terms used herein shall have the same general meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The use of the terms "a" and "an" and "the" and similar referents in the context of this application do not denote a limitation of quantity, either in the singular or the plural. The terms "comprises," "comprising," "has," "having," and any variations thereof, as referred to in this application, are intended to cover non-exclusive inclusions; for example, a process, method, and system, article, or apparatus that comprises a list of steps or modules (elements) is not limited to the listed steps or modules, but may include other steps or modules (elements) not listed or inherent to such process, method, article, or apparatus. Reference throughout this application to "connected," "coupled," and the like is not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Reference to "a plurality" in this application means two or more. "and/or" describes an association relationship of associated objects, meaning that three relationships may exist, for example, "A and/or B" may mean: a exists alone, A and B exist simultaneously, and B exists alone. In general, the character "/" indicates a relationship in which the objects associated before and after are an "or". The terms "first," "second," "third," and the like in this application are used for distinguishing between similar items and not necessarily for describing a particular sequential or chronological order.
The wafer is a silicon die with an approximate circular shape, and as shown in fig. 1, the wafer is a schematic view of a wafer on which a plurality of rectangular dies are arranged. The following format is typically used in the related art to store die data:
Table wafer_yiled{
log _ id # wafer unique id
X coordinate of DieX # die
Y coordinate of DieY # die
Value # pass or fail
}
Assuming that 2000 die exist in 1 wafer, int (integer) data type is used for storing values corresponding to four fields of Log _ id, DieX, DieY and Value, and data of one wafer is stored in the same Table (Table) according to the format, one integer data occupies 4 bytes and has four fields in total, 4 × 2000 bytes are needed, it is seen that the occupied storage space is large, which causes the data volume of each request to be large, and further affects the calculation efficiency of yield.
In addition, it has been found that the yield value of a wafer is often strongly correlated with the yield value of a certain area. For example, the yield of wafer edge is reduced by stress, and the number of die failures in the edge area is greater than that in the middle. If the edge value and the middle value are mixed directly to calculate the yield, the problem of poor response is often solved. However, if values of different areas are calculated, a larger amount of calculation is often caused, and great challenges are brought to the throughput of the database and the memory of the computer.
To solve the above problem, the present embodiment provides a wafer data processing method, and fig. 2 is a flowchart of the wafer data processing method of the present embodiment, as shown in fig. 2, the flowchart includes the following steps:
step S201, determining the position information of a target bare chip of one type in a wafer;
step S202, the position information of the target bare chip and the mark information of the wafer are stored in a correlation mode, wherein the wafer comprises an invalid bare chip and an effective bare chip, and the mark information of the wafer is information for uniquely identifying the wafer.
The position information of the target bare chip is position information of an effective bare chip or position information of a failed bare chip, the mark information of the wafer is information for uniquely identifying the wafer (wafer), and the manner of storing the position information of the target bare chip and the mark information of the wafer in an associated manner is not limited, so as to realize the corresponding relationship between the wafer and the bare chip, for example: the data of the dies in the same wafer can be stored in the same data table, and the mark information of the wafer is used as the index of the corresponding data table, or the position information of one die and the mark information of the wafer to which the die belongs are stored as one piece of data. The position information may be two-dimensional coordinate information, or may be two-dimensional coordinate information that is converted into one-dimensional data that uniquely represents the die, for example, by giving each two-dimensional coordinate information a unique number. The wafer ID is a wafer ID that uniquely represents a certain wafer.
In practical applications, the same number of dies are contained in the same type of wafer. When the type of the target die is failure, the yield of the current wafer can be calculated by using the (the total number of the die-the number of the target die)/the total number of the die); when the type of the target die is valid, the yield of the current wafer can be calculated by using the number of the target die/the total number of the dies. When the type of the target bare chip is selected, the yield range can be estimated in advance according to experience and other modes, if the yield is lower than 50%, the effective bare chip is selected as the target bare chip, and the coordinate information of the effective bare chip and the mark information of the wafer are stored in an associated manner; if the die size is higher than 50%, selecting the failed die as a target die, and storing the coordinate information of the failed die and the mark information of the wafer in an associated manner. By selecting the proper type as the target bare chip in the above mode, the storage space can be further reduced, and the wafer yield calculation efficiency is improved.
In the above steps S201 to S202, the position information of one type of target die in the wafer is stored in association with the mark information of the wafer, so that when the yield of the wafer is calculated, the yield calculation is implemented by only searching and reading the position information of the corresponding target die according to the mark information of the wafer, the problem of low yield calculation efficiency due to slow reading speed caused by reading the position information of all the dies in the related art is solved, and the yield calculation efficiency is improved.
In some of these embodiments, determining location information for a type of target die in a wafer includes: establishing a reference coordinate system on the wafer, and determining the position information of the target die according to the reference coordinate system, wherein the position information of the target die comprises the coordinate information of the target die in the wafer.
The reference coordinate system can be a conventional rectangular coordinate system, can be set at any position according to requirements, and in practical application, the origin of coordinates is usually set at the center of a circle of a wafer or coordinate axes are set at circumscribed positions of the wafer.
Specifically, the horizontal and vertical coordinates of the target die are determined according to the reference coordinate system, and the horizontal and vertical coordinates of the target are determined as the position information of the target die.
In some of these embodiments, the position information of the target dies further includes die numbers, wherein the die numbers are set according to the positions of the target dies in the wafer.
The die number may be integer data that only occupies 4 bytes, and can uniquely represent the position of the target die in the wafer.
Specifically, respective bare chips can be distributed to the target bare chips according to a uniform rule, the bare chips include information such as a wafer to which the bare chips belong and positions in the wafer, and the method can be used for positioning the positions of the target bare chips only through the information included in the bare chips, for example, a bare chip "10323" in which "1" represents a first wafer, "03" represents a horizontal coordinate of 3, and "23" represents a vertical coordinate of 23, and meanwhile, the bare chips of the bare chips can be stored after being arranged in order based on the sizes of the bare chips. Alternatively, all the dies in the wafer may be subjected to sequential die arrangement according to the wafer horizontal and vertical arrangement order, such as: 01, 02, …, then only store the bare chip of the target bare chip that is invalid or valid, can carry out the storage after arranging the bare chip of target bare chip in order through the size order of bare chip simultaneously, this kind of mode has further saved storage space, can promote the computational efficiency of yield greatly.
In some of these embodiments, determining the die number of each target die in the wafer includes: obtaining circumscribed rectangles of the wafer, dividing the circumscribed rectangles according to the sizes of bare chips in the wafer to obtain small rectangles with the sizes of NxM bare chips; and carrying out sequential numbering according to the positions of the small rectangles in the cut-out rectangles, and determining the die number of each target die in the wafer according to the obtained serial numbers after the sequential numbering, wherein N, M is a natural number.
Fig. 3 is a schematic diagram of the divided circumscribed rectangles, in which the circle represents the wafer, the inside of the circle is divided into small rectangles, and the position of each small rectangle corresponds to the position of each die. In practical application, in order to facilitate the positioning of equipment, the shape of a wafer is not a complete circle, the wafer is provided with uniform notches and edges, when a circumscribed rectangle of the wafer is obtained, the positive direction of the wafer can be determined according to the position of the notch of the wafer, and then the circumscribed rectangle is determined according to the positive direction of the wafer, so that the direction of the circumscribed rectangle is uniform with the direction of the equipment during the positioning, and the position information of a bare chip is convenient to obtain. After the circumscribed rectangle is obtained, the circumscribed rectangle is divided into N multiplied by M small rectangles according to the size of the bare chip and the edge position of the bare chip, and each small rectangle corresponds to one bare chip. The size of the circumscribed rectangle can determine the number corresponding to the target bare chip according to the horizontal and vertical arrangement positions of the rectangle. In some of these embodiments, the small rectangles are numbered in order from left to right, from bottom to top, to determine the die number, and the number corresponding to one type of target die is stored. Further, in some of these embodiments, the die number of the target die in the wafer is obtained by traversing.
By acquiring the circumscribed rectangle with the same direction as the bare chip and numbering the bare chips according to a uniform sequence, the specific positions of the bare chips in the same wafer model can be obtained through rapid calculation of the bare chip numbers, and only the numbers of one type of target bare chips are stored, so that the storage space is greatly reduced, and the yield calculation efficiency is improved.
In practical application, after all the dies in the wafer are sequentially numbered according to the horizontal and vertical arrangement order of the wafer, when only the die number of the failed target die is stored, the specific storage format is as follows:
Table wafer yield{
log _ id # wafer unique id
Id # failure die Id
}
Wherein the flag information (Log _ id) of the wafer and the die number of the failed die within the wafer are stored in a table. Assuming that there are 2000 dies in 1 wafer, the number of failed dies accounts for 10% of the total number of dies in the wafer, if the storage method of storing the X coordinate and the Y coordinate of the failed die in the related art is used, the storage amount of 4 × 200 bytes is required, and if only the die number of the target die is stored, the actual storage amount can be reduced by 2 times, and the storage amount can be reduced to 8 × 200 bytes.
In practical applications, if the lower left corner of the circumscribed rectangle is not at the origin position of the coordinate system, if necessary, the coordinate information of the circumscribed rectangle and the size information of the wafer may also be recorded in the table of the wafer data, if the lower edge of the default circumscribed rectangle coincides with the X axis, the value of the lower left corner X and the Length of the circumscribed rectangle in the Y axis direction are recorded, and if X is-3 and Y _ Length is 100, the position of the target die with a die number (Id) of 1001 in the coordinate system may be calculated as follows: y =1000/100, X = 1001%100+ X, the actual corresponding coordinate of the target die in the coordinate system is (-2, 10).
Further, in some embodiments, after all the dies in the wafer are sequentially numbered according to the horizontal and vertical arrangement order of the wafer, a Cassandra (open source distributed NoSQL database system) database is used to store the die numbers of the target dies in a sequential storage manner. Specifically, when data of a certain wafer is stored, the die numbers of the failed dies of the wafer are all added to the list, and then the flag information of the wafer is stored in Cassandra together with the list.
In one embodiment, a storage format for storing wafer data using a Cassandra database in the wafer data processing method of the present application is provided:
CREATE TABLE IF NOT EXISTS cp_test(
log_id bigint,
value FROZEN<List<int>>,
primary key(log_id,)
)WITH campaction={‘class’:‘LeveledCampactionaStrategy’};
in the present embodiment, the frozen technology of the Cassandra database is utilized to store the location information of the target die within the wafer. The frozen technology of the Cassandra database has a good compression effect on pure data types, and the position information of the target bare chip is stored in the database in sequence, so that the throughput speed of reading data from a magnetic disk is increased.
In some embodiments, after storing the position information of the target die in association with the flag information of the wafer, the method further includes: and calculating the yield of the wafer.
Calculating the yield of the wafer comprises: acquiring the total number of bare chips in a wafer and the number of target bare chips; and calculating the yield according to the total number of the dies and the number of the target dies.
The total number of the dies in the wafer can be obtained according to the size of the wafer and the size of the dies, and when the type of the target die is failure, the yield of the current wafer can be calculated by using the (total number of the dies-the number of the target dies)/the total number of the dies "; when the type of the target die is valid, the yield of the current wafer can be calculated by using the number of the target die/the total number of the dies.
In some embodiments, after storing the position information of the target die in association with the flag information of the wafer, calculating the yield of the wafer further comprises: the yield of the interested area in the wafer is calculated.
The region of interest in the wafer may be a user-defined region, and the region of interest is assumed to be an annular region at the edge of the wafer, as shown in fig. 4, the annular region of interest is a schematic diagram, and a black filled region in the diagram is a position where the bare chip is located in the annular region at the edge of the wafer.
Further, calculating the yield of the region of interest in the wafer includes: acquiring the position information of the region of interest, and determining the total number of bare chips of the region of interest according to the position information of the region of interest; and determining the number of the target dies in the interested area according to the position information of the target dies and the position information of the interested area, and calculating the yield of the interested area in the wafer according to the total number of the dies in the interested area and the number of the target dies in the interested area.
The position information of the region of interest may be obtained by calculating relevant parameters (such as an inner circle diameter of the annular region) of the region of interest input by a user, and after the total number of the target dies of the region of interest is determined according to the position information of the region of interest, the target dies in the region of interest may be searched in the database and the number of the target dies in the region of interest may be obtained. When the type of the target die is failure, calculating the yield of the current wafer in the region of interest by using the (the total number of the dies in the region of interest-the number of the target dies in the region of interest)/the total number of the dies in the region of interest'; when the type of the target die is valid, the yield of the current wafer in the region of interest can be calculated by using the number of the target die in the region of interest/the total number of the dies in the region of interest.
The following are relevant experimental validation results obtained according to some examples of the present application to demonstrate the feasibility and effectiveness of the present application:
under the same 3 Cassandra performances, the throughput of the prior art is 700W per second, and the storage mode provided by the embodiment of the application can reach the speed of 4 hundred million per second, and the yield of the local interested region can be accurately calculated, so that the yield calculation of the local interested region of the wafer based on a Cassandra database is greatly accelerated, and the efficiency of the yield calculation is improved.
It should be noted that the steps illustrated in the above-described flow diagrams or in the flow diagrams of the figures may be performed in a computer system, such as a set of computer-executable instructions, and that, although a logical order is illustrated in the flow diagrams, in some cases, the steps illustrated or described may be performed in an order different than here.
There is also provided in this embodiment an electronic device comprising a memory having a computer program stored therein and a processor configured to execute the computer program to perform the steps of any of the wafer data processing method embodiments described above.
Optionally, the electronic apparatus may further include a transmission device and an input/output device, wherein the transmission device is connected to the processor, and the input/output device is connected to the processor.
Optionally, in this embodiment, the processor may be configured to execute the following steps by a computer program:
step S201, determining the position information of a target bare chip of one type in a wafer;
step S202, storing the position information of the target die and the mark information of the wafer in an associated manner, where the wafer includes two types, namely an invalid die and an valid die, and the mark information of the wafer is information for uniquely identifying the wafer.
It should be noted that, for specific examples in this embodiment, reference may be made to the examples described in the foregoing embodiments and optional implementations, and details are not described again in this embodiment.
In addition, in combination with the wafer data processing method provided in the foregoing embodiment, a storage medium may also be provided to implement the method in this embodiment. The storage medium having stored thereon a computer program; the computer program when executed by a processor implements the steps of:
step S201, determining the position information of a target bare chip of one type in a wafer;
step S202, the position information of the target bare chip and the mark information of the wafer are stored in a correlation mode, wherein the wafer comprises an invalid bare chip and an effective bare chip, and the mark information of the wafer is information for uniquely identifying the wafer.
In one embodiment, there is also provided a computer program product comprising a computer program which when executed by a processor performs the steps of:
step S201, determining the position information of a target bare chip of one type in a wafer;
step S202, the position information of the target bare chip and the mark information of the wafer are stored in a correlation mode, wherein the wafer comprises an invalid bare chip and an effective bare chip, and the mark information of the wafer is information for uniquely identifying the wafer.
It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to be limiting. All other embodiments, which can be derived by a person skilled in the art from the examples provided herein without any inventive step, shall fall within the scope of protection of the present application.
It is obvious that the drawings are only examples or embodiments of the present application, and it is obvious to those skilled in the art that the present application can be applied to other similar cases according to the drawings without creative efforts. Moreover, it should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another.
The term "embodiment" is used herein to mean that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the present application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is to be expressly or implicitly understood by one of ordinary skill in the art that the embodiments described in this application may be combined with other embodiments without conflict.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the patent protection. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present application shall be subject to the appended claims.
Claims (12)
1. A method of processing wafer data, comprising:
determining position information of a type of target bare chip in a wafer;
and storing the position information of the target bare chip and the mark information of the wafer in an associated manner, wherein the wafer comprises two types of invalid bare chips and valid bare chips, and the mark information of the wafer is information for uniquely identifying the wafer.
2. The wafer data processing method of claim 1, wherein the type of the target die is a failed die.
3. The wafer data processing method of claim 1, wherein determining the location information for a type of target die in the wafer comprises: establishing a reference coordinate system on the wafer, and determining the position information of the target die according to the reference coordinate system, wherein the position information of the target die comprises the coordinate information of the target die in the wafer.
4. The wafer data processing method of claim 1, wherein the position information of the target dies further comprises die numbers, wherein the die numbers are set according to positions of the target dies in the wafer.
5. The wafer data processing method of claim 4, wherein determining the die number of each target die in the wafer comprises:
obtaining circumscribed rectangles of the wafer, and dividing the circumscribed rectangles according to the sizes of the bare chips in the wafer to obtain small rectangles with the sizes of NxM bare chips;
and sequentially numbering according to the positions of the small rectangles in the circumscribed rectangle, and determining the die number of each target die in the wafer according to the obtained number after sequential numbering, wherein N, M is a natural number.
6. The wafer data processing method of claim 5, wherein determining the location information for a type of target die in the wafer comprises:
and traversing to acquire the die number of the target die in the wafer.
7. The wafer data processing method of claim 1, wherein after storing the location information of the target die in association with the flag information of the wafer, the method further comprises: and calculating the yield of the wafer.
8. The wafer data processing method of claim 7, wherein calculating the yield of the wafer comprises:
acquiring the total number of the bare chips in the wafer and the number of the target bare chips;
and calculating the yield according to the total number of the dies and the number of the target dies.
9. The wafer data processing method of claim 7, wherein calculating the yield of the wafer comprises: and calculating the yield of the interested area in the wafer.
10. The method as claimed in claim 9, wherein calculating the yield of the region of interest in the wafer comprises:
acquiring position information of a region of interest, and determining the total number of bare chips of the region of interest according to the position information of the region of interest;
determining the number of the target dies in the region of interest according to the position information of the target dies and the position information of the region of interest, and calculating the yield of the region of interest in the wafer according to the total number of the dies in the region of interest and the number of the target dies in the region of interest.
11. An electronic device comprising a memory and a processor, wherein the memory has stored therein a computer program, and the processor is configured to execute the computer program to perform the steps of the wafer data processing method according to any one of claims 1 to 10.
12. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the wafer data processing method according to any one of claims 1 to 10.
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| CN114300377A (en) * | 2022-03-10 | 2022-04-08 | 晶芯成(北京)科技有限公司 | Yield loss acquisition system and method for non-pattern wafer |
| CN114399508A (en) * | 2022-03-25 | 2022-04-26 | 杭州广立微电子股份有限公司 | Wafer data processing method and device, electronic device and storage medium |
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