CN104916559A - Bit Failure Detection Method Combined with Entity Coordinates - Google Patents

Abstract

The present invention discloses a bit failure detection method combined with physical coordinates. In this method, a wafer alignment detection data is first obtained, which includes an image of a defect in each layer of a wafer and the physical coordinates of the defect; then, a bit failure detection step is performed to obtain the digital coordinates of the failed bit in the wafer, and the digital coordinates are converted into a physical position, and the physical position is overlapped with the physical coordinates, so as to quickly obtain the correlation between the failed bit and the defect.

Description

Bit Failure Detection Method Combined with Entity Coordinates

technical field

The present invention relates to a failure analysis method (Failure Analysis Methodology), and in particular to a bit failure detection method combined with entity coordinates.

Background technique

As the line width of the IC process continues to shrink, the precise control and monitoring of components is also more important. From the perspective of nano-generation semiconductor technology, to increase the yield of components, it is necessary to carry out accurate detection and analysis.

The current method for chip failure analysis (failure analysis, FA) includes a technology called Bitmap failure, which can get failure bits and find out their physical location, and can (failure item) to predict which layer of the chip internal structure fails.

However, because the cause of the bit failure is unknown, if you want to get the exact cause of the bit failure, you must grind the entire chip under test from the surface to the layer structure that may cause the bit failure, and then scan it Electron microscopy (SEM) surface analysis. Therefore, current bit failure analysis is labor-intensive and time-consuming.

Contents of the invention

The invention provides a bit failure detection method combined with physical coordinates, which can greatly shorten the analysis time of bit failure.

The present invention also provides a bit failure detection method combined with physical coordinates, which can quickly obtain the physical location and failure cause of the failed bit.

The bit failure detection method combined with physical coordinates of the present invention includes first obtaining a wafer alignment detection data. The wafer alignment detection data includes images of multiple defects on each layer in a wafer and multiple physical coordinates of the defects in the wafer. In this method, a bit failure detection step is performed to obtain a digital coordinate of a plurality of failed bits in the wafer, and convert the digital coordinate into a plurality of physical locations of lines or polygons. Then, the physical position is superimposed on the physical coordinates in the wafer to obtain the correlation between the failure bit and the defect.

In an embodiment of the present invention, the above method further includes obtaining a scanning electron microscope (SEM) image of the defect according to the physical position of each failure position corresponding to the physical coordinate in the wafer , and then determine the cause of the failure according to the SEM image.

In an embodiment of the present invention, the step of superimposing the physical position on the physical coordinates in the wafer includes classifying the failure bits according to different defects in the wafer alignment detection data.

Another bit failure detection method combined with physical coordinates of the present invention includes performing a bit failure detection step to obtain digital coordinates of all failed bits in a wafer, and then converting the digital coordinates into coordinates of a graphic data system (GDS file coordinate) or an inspection result coordinate (inspection result file coordinate). Then, comparing the data of the coordinates of the graphic data system or the coordinates of the detection result with the database file of the wafer, so as to output a plurality of physical positions of the failure bits. By comparing the physical position with the detection result file of the wafer, the defect corresponding to the failure bit can be obtained.

In another embodiment of the present invention, the above method further includes classifying the failure bits according to the obtained defects.

In another embodiment of the present invention, if the above-mentioned digital coordinate conversion is the detection result coordinates, then in the step of comparing the data with the database file, the detection result coordinates are directly compared with the detection defect wafer map (defect Klarf map) Comparison.

In another embodiment of the present invention, if the above-mentioned digital coordinates are transformed into coordinates of the graphic data system, before comparing the data with the database file, the coordinates of the inspected defect wafer map are converted into the coordinates of the graphic data system file.

In various embodiments of the present invention, the digital coordinates obtained in the bit failure detection step include failures of a plurality of bit lines and failures of a plurality of word lines.

In various embodiments of the present invention, the aforementioned failure of the bit line or the failure of the word line may include open, short or close.

In various embodiments of the present invention, the location of the defect includes a word line, a bit line, a polysilicon layer or a contact window.

In each embodiment of the present invention, the above method further includes comparing the number of failed bits and the total number of defects to obtain the probability of defects caused by bit failures (also known as "the ratio of defects caused by source layers affecting yield") ).

In each embodiment of the present invention, the above-mentioned method further includes obtaining repeating systematic defects from detection results located in different dies in the wafer.

Based on the above, the present invention can obtain the analysis results of hundreds or even thousands of bit failures in a short period of time, and can obtain the source (layer) or defect type fatality of word line failure through the ratio between the number of defects and the failure bits. Rate. Moreover, the present invention can also directly obtain the image of the defect site that causes the bit failure through the chip image stored in the chip inspection system and determine its defect type.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.

Description of drawings

FIG. 1 is a step diagram of bit failure detection combined with physical coordinates according to the first embodiment of the present invention.

FIG. 2 is a diagram of the wafer alignment detection results in the first embodiment.

FIG. 3A is a bar chart for classifying failed bits according to wafer alignment inspection data in the first embodiment.

FIG. 3B is a wafer map obtained through FIG. 3A.

FIG. 4 is a step diagram of bit failure detection combined with entity coordinates according to the second embodiment of the present invention.

Fig. 5 is a schematic diagram of coordinates obtained in the second embodiment.

FIG. 6 is a SEM image of the defect location in FIG. 5 .

【Symbol Description】

100~130, 400~430: steps

301～309: type

500: coordinates

502: straight line

504: area

506: defect

Detailed ways

FIG. 1 is a step diagram of bit failure detection combined with physical coordinates according to the first embodiment of the present invention.

Please refer to FIG. 1 , the method of this embodiment first performs step 100 to obtain a wafer alignment detection (wafer mapping) data. The so-called wafer alignment detection is to obtain an image by aligning the inspection machine with the actual wafer according to the wafer map, so that each die in the wafer can be detected in real time, and the die in the die can be detected Various defects in the wafer map are marked with different color codes, as shown in Figure 2 (although Figure 2 is shown in black and white, it is actually in color). The above-mentioned images are generally obtained by scanning electron microscopy (SEM), so they can be saved and named according to the grain location or defect type. In this embodiment, the wafer alignment detection data includes defect images in each layer structure in a single wafer, and physical coordinates of each defect in the wafer. The locations of the above-mentioned defects are, for example, structures in the wafer such as word lines, bit lines, polysilicon layers, and contact windows.

Then, in step 110, a bit map failure detection (Bitmap failure) step is performed to obtain the digital coordinates of the failure bits in the wafer. The so-called bit failure detection technology is to use the detection instrument to measure the failed bit and output the result in digital coordinates. The digital coordinates obtained from the above bit failure detection step may include different types of bit failures, such as bit line failures, word line failures or failures caused by other circuits. Moreover, the failure of the bit line or the failure of the word line can also be classified into failures caused by different reasons, such as open, short or close.

Next, in step 120, convert the above-mentioned digital coordinates into physical positions of lines or polygons. Since the data obtained in the current bit failure detection step shows the physical layout of the failure bit in the form of GDSII coordinates, the digital coordinates can be converted to correspond to step 100 through specific software or other appropriate equipment in the above-mentioned detection instrument. A file of entity coordinates for wafer alignment inspection.

Then, in step 130 , the above-mentioned physical position is superimposed on the physical coordinates in the wafer, so as to obtain the correlation between the failure bit and the defect. For example, after step 130 is performed, data including defect ID, x and y coordinates, defect classification, source layer, and corresponding SEM image (if any) can be obtained. As mentioned above, step 130 of this embodiment can further classify the failed bits according to different defects in the wafer alignment detection data. Please refer to the bar graph 3A obtained after classification, which shows 9 different types of defects 301-309 and their corresponding numbers, and the number of all defects is 1647. If it is necessary to analyze the distribution of different defects on the wafer, the wafer map in Figure 3B can be obtained by software inversion (although Figure 3B is displayed in black and white, it is actually in color).

In addition, since the physical position of each failure bit corresponds to the physical coordinates in the wafer, the SEM image of each defect can be obtained, and the cause of the failure bit can be determined based on the SEM image. The SEM image here is the image obtained during the above-mentioned wafer alignment inspection, so no extra time is needed to obtain the images of these defects. Of course, the present invention is not limited thereto, as long as the physical position of the failure position corresponds to the physical coordinate in the wafer, the position of the defect can be obtained, and then the signature and the failure position are compared.

In addition, the method according to the first embodiment can also obtain the probability of defects caused by bit failures (also known as "source killing ratio of defects generated by source layers) by comparing the number of failed bits with the total number of defects." ratio)"). In other words, when the wafer alignment detection data obtained in step 100 shows that there are m defects in total, and the number of defects corresponding to the failure bits obtained from step 130 is n, then it can be obtained by (n/m×100%) The probability of a defect resulting from a bit failure.

Furthermore, since the first embodiment detects the entire wafer, repeating systematic defects can be obtained through the detection results of different dies in the wafer. For example, if the allowable error is set to 1 μm, a defect of ±1 μm at the same position in different grains can be identified as a repeating defect.

FIG. 4 is a step diagram of bit failure detection combined with entity coordinates according to the second embodiment of the present invention.

Please refer to FIG. 4 , the method of this embodiment firstly performs a bit failure detection step in step 400 to obtain the digital coordinates of all failure bits in a wafer. The digital coordinates obtained from the bit failure detection step above may include different types of bit failures, such as bit line failures, word line failures or failures caused by other lines. Moreover, the failure of the bit line or the failure of the word line can also be classified into failures caused by different reasons, such as open, short or close.

In step 410, the above digital coordinates are converted into GDS coordinates or inspection result coordinates (such as Klarf file coordinates). GDS files are generally layout circuit design files, so the physical coordinates of the wafer are attached. In addition, the results of the current wafer inspection system can also be converted into GDS coordinates via specific software. As for the detection result coordinates, for example, the result file (also known as Klarf) obtained through the detection equipment of KLA Company. In detail, the numerical coordinates (such as the coordinates of the bitmap file) can be converted into GDS coordinates or Klarf coordinates of the entity.

Next, in step 420 , compare the data of the coordinates of the graphic data system or the coordinates of the detection result with the database file of the above-mentioned wafer, so as to output the physical position of the failure bit. Specifically, if it is converted into Klarf coordinates in the previous step 410, it is directly compared with the detected defect wafer map (defect Klarf map). In addition, if converting to GDS coordinates in the previous step 410, the coordinates (Klarf coordinates) of the detected defect wafer map need to be converted to GDS coordinates first, and then compared between the two.

Then, in step 430, comparing the physical position with the inspection result file of the wafer, the defect corresponding to each failure bit can be obtained. For example, FIG. 5 shows a schematic diagram of coordinates obtained after step 430 is performed. In FIG. 5 , the straight line 502 in the coordinates 500 is the physical position of the failure position converted into GDS coordinates through step 410 , and the area 504 is the position of the defect 506 corresponding to the failure position obtained through step 403 . Although FIG. 5 only shows a straight line 502 (that is, one failure bit), in practice, there may be thousands or tens of thousands of failure bits in a single wafer, so the present invention is not limited thereto. Moreover, since the so-called "inspection result file" is a wafer inspection performed with each step during the wafer process, such as wafer alignment inspection (wafer mapping), the actual wafer can be obtained at the same time. The images of each layer are circled, so the corresponding scanning electron microscope (SEM) image of FIG. 6 can be found according to the coordinates of the area 504 in FIG. 5 , and the cause of the failure (502) can be determined based on the SEM image. If no defects are found in the predicted SEM images of a certain layer, defects can be found by inspecting the SEM images of the same location in other layers.

Furthermore, the failed bits can also be classified according to the obtained defects. For example, because the defect may be a word line, a bit line, a polysilicon layer, a contact window, or more than two structures above, the measured failure bit can also be classified as (1) caused by the defect of the word line itself. (2) failure bits caused by defects in the bit line itself, (3) failure bits caused by defects in the polysilicon layer (such as gate structure), (4) failure bits caused by defects in the contact window... …wait.

In addition, in the second embodiment, by comparing the number of failed bits and the total number of defects, the probability of defects caused by bit failures (also known as "source killing ratio caused by defects in the source layer") can be obtained. )”). In the second embodiment, repeated systematic defects (repeating systematic defects) can also be obtained through detection results at different die IDs in the wafer.

To sum up, the present invention can obtain the analysis results of hundreds or even thousands of bit failures in a short period of time, and by obtaining the precise position of the defect relative to the failed bits, it is beneficial to detect the failed bits and find out the cause. The present invention can also obtain the source (layer) lethal rate of the word line failure through the ratio between the number of defects and the failure bits. Since the present invention uses the chip image stored by the chip inspection system, the image of the defective part that causes bit failure can also be obtained directly. Furthermore, the method according to the invention can also capture repeated systematic defects.

Although the present invention has been disclosed as above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the appended claims.

Claims (12)

1. a position inefficacy method for detecting for binding entity coordinate, comprising:

Obtain a Wafer alignment and detect data, described Wafer alignment detects image and the multiple entities coordinate of described defect in described wafer that datagram draws together multiple defects of every one deck in a wafer;

Carry out the detecting step that lost efficacy, to obtain a digital coordinates of multiple fail bit in described wafer;

Change described digital coordinates into line or polygonal multiple provider location; And

Described provider location is overlapped in the described entities coordinate in described wafer, to obtain the relevance between described fail bit and described defect.

2. the position inefficacy method for detecting of binding entity coordinate according to claim 1, more comprises:

According to the described entities coordinate in the corresponding described wafer of the described provider location of each this fail bit, obtain multiple scanning electrons micro-(SEM) image of described defect; And

The reason of described fail bit is caused according to described SEM scope interpretation.

3. the position inefficacy method for detecting of binding entity coordinate according to claim 1, the step of the described entities coordinate that wherein said provider location is overlapped in described wafer comprises: detect described defects different in data according to described Wafer alignment, classified by described fail bit.

4. a position inefficacy method for detecting for binding entity coordinate, comprising:

Carry out the detecting step that lost efficacy, to obtain a digital coordinates of all fail bits in a wafer;

Described digital coordinates is converted to a graphic data system coordinate or a testing result coordinate;

One data of graphic data system coordinate described in comparison or described testing result coordinate and a Data Base Pile of described wafer, to export multiple provider locations of described fail bit; And

One testing result shelves of provider location described in comparison and described wafer, to obtain the multiple defects corresponding to described fail bit.

5. the position inefficacy method for detecting of binding entity coordinate according to claim 4, more comprises and classifying to described fail bit according to described defect.

6. the position inefficacy method for detecting of binding entity coordinate according to claim 4, the conversion of wherein said digital coordinates be the words of described testing result coordinate, then in the step of data described in comparison and described Data Base Pile, by described testing result coordinate directly with detect defective wafer figure and compare.

7. the position inefficacy method for detecting of binding entity coordinate according to claim 4, the conversion of wherein said digital coordinates be described graphic data system coordinate, then more comprise before than the step to described data and described Data Base Pile: will defective wafer figure coordinate be detected transfer to the coordinate of a graphic data system file.

8. the position inefficacy method for detecting of the binding entity coordinate according to claim 1 or 4, the described digital coordinates of wherein said position inefficacy detecting step gained comprises the inefficacy of multiple bit line and the inefficacy of multiple wordline.

9. the position inefficacy method for detecting of binding entity coordinate according to claim 8, the inefficacy of wherein said bit line or the inefficacy of described wordline comprise open circuit (open), short circuit (short) or path (close).

10. the position inefficacy method for detecting of the binding entity coordinate according to claim 1 or 4, the position of wherein said defect comprises wordline, bit line, polysilicon layer or contact hole.

The position inefficacy method for detecting of 11. binding entity coordinates according to claim 1 or 4, more comprises and obtains leading the probability because of the defect lost efficacy in position by the quantity of more described fail bit and the sum of described defect.

The position inefficacy method for detecting of 12. binding entity coordinates according to claim 1 or 4, the testing result more comprised by being positioned at different crystal grain in described wafer obtains the system defect of repetition.