CN104062305A - Defect analysis method for integrated circuit - Google Patents
Defect analysis method for integrated circuit Download PDFInfo
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- CN104062305A CN104062305A CN201410163560.9A CN201410163560A CN104062305A CN 104062305 A CN104062305 A CN 104062305A CN 201410163560 A CN201410163560 A CN 201410163560A CN 104062305 A CN104062305 A CN 104062305A
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Abstract
The invention discloses a defect analysis method for an integrated circuit. The method comprises the following steps of obtaining a wafer defect distribution file and a general wafer defect distribution diagram by using optical defect detection equipment, sampling different types of defect characteristic signals to generate a defect pre-analysis distribution diagram, rapidly analyzing real and pseudo defects in the defect pre-analysis distribution diagram by using an electronic microscope, and pertinently selecting the microstructure analysis number of all the defects on a wafer on such a basis to finally obtain a practical defect type distribution diagram.
Description
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to a kind of analytical approach of integrated circuit defect.
Background technology
In prior art, comparatively advanced integrated circuit fabrication process generally all comprises the operation of hundreds of step, the small mistake of any link all will cause the inefficacy of whole chip, constantly dwindling along with circuit critical size particularly, it is just stricter to the requirement of technology controlling and process, so all need to configure high sensitivity optical defect checkout equipment for finding in time and deal with problems in actual production run, product is detected online.
The basic functional principle of defects detection is that the optical imagery conversion on chip is turned to the data image being represented by the bright dull gray of difference rank, Fig. 1 is the schematic diagram that circuit optical imagery transforms into data gray scale image, the image obtaining under an optical microscope is converted into the process of data image feature, then by the abnormal defect position of relatively detecting of the datagraphic feature in adjacent chips; The characteristic signal that equipment is caught defect is a very complicated algorithm, and the expression of each defect is not quite similar again, and bright dark, passage of catching defect of the position on its concrete defect place chip, the size of defect, defect etc. is closely related.
At present, when the defective locations obtaining for checkout facility in process of production carries out concrete morphology analysis, what adopt is the position to 50～100 defects of the random sampling observation of defects count total on wafer, and be transferred to the observation and analysis that carries out concrete pattern under electron microscope, finally obtain the distribution plan of a defect kind in wafer statistical significance, Fig. 2 is the distribution plan that has the final defect kind of 1000 defects, but the method is relatively difficult to embody the defect distribution that defect detection equipment obtains according to the different characteristic signal of defect, if there is 60% defect to be generated by noise signal on a wafer, so according to existing defect analysis method, when selecting 100 defects to observe, with regard to there being 60% time, be finally for analyzing noise signal, certainly will cause like this waste of resource and the increase of manufacturing cost.
Chinese patent (CN101996855B) discloses a kind of wafer defect analysis method, comprise: complete after specific process step, detect described wafer, crystal grain on it is divided into defect crystal grain and non-defect crystal grain, and by the number of defects in defect crystal grain described in each, described defect crystal grain is classified, obtain the first testing result; After all technique all completes, above-mentioned wafer is carried out to performance test, the crystal grain on it is divided into work crystal grain and inoperative crystal grain, obtain the second testing result; According to described the first testing result and described the second testing result, the crystal grain of described wafer is carried out to subseries again; Calculate the defect that every kind of defect causes and lead to crash rate and yield loss, wafer defect analysis method of the present invention is accurately feasible, has solved the inaccurate defect of prior art defect analysis.
Although this patent mentions wafer defect classified, do not relate to the preanalysis of sampling of the characteristic signal of various defects, cannot solve the problem of the above-mentioned wasting of resources.
Chinese patent (CN101738400B) discloses a kind of method that judges repeated defects on surface of wafer, comprises the steps: that (a) obtains the surface topography data of the some crystal grain of crystal column surface to be measured, and the design data of grain morphology; (b), according to the design data of the grain morphology of wafer to be measured, determine the division rule of sub-crystal grain; (c), according to sub-crystal grain division rule, utilize the surface topography data of crystal grain that each crystal grain is divided into some sub-crystal grain; (d) take sub-crystal grain as basic detecting unit, form at least one and detect sequence; (e), in same detection sequence, select each sub-crystal grain to compare with at least two other sub-crystal grain, to judge repeated defects.The present invention also provides a kind of device that judges repeated defects on surface of wafer.The invention has the advantages that, the sub-crystal grain repeating in each crystal grain of usining is tested crystal column surface as basic test cell.Therefore the present invention can test the region at grain surface repetitive place, to find grain surface to be positioned at the repeated defects of above-mentioned zone.
Although the method by this patent has carried out dividing planning to defect,, do not relate to the preanalysis of sampling of the characteristic signal of various defects, cannot solve the problem of the above-mentioned wasting of resources.
Summary of the invention
The invention discloses a kind of analytical approach of integrated circuit defect, by optical defect checkout equipment, draw wafer defect distribution file and wafer defect total points Butut, and different types of defect characteristic signal sampling is generated to defect preanalysis distribution plan, and by electron microscope, defect preanalysis distribution plan is carried out to the express-analysis of true and false defect, then on this basis the morphology analysis quantity of all defect on wafer is carried out to specific aim and choose, finally obtain a more realistic defect kind distribution plan.
The present invention has recorded a kind of analytical approach of integrated circuit defect, and wherein, described method comprises:
S1 a: wafer that comprises some defects is provided;
S2: detect described wafer and identify the defect characteristic signal in defect described in each by an optical defect checkout equipment and obtain a wafer defect distribution file, thereby draw a wafer defect total points Butut in described wafer defect distribution file;
S3: described optical defect checkout equipment is classified to all described defects by described defect characteristic signal, and in every class defect, choose the prediction defect of some, thus draw a wafer defect preanalysis distribution plan;
S4: described wafer defect total points Butut and described wafer defect preanalysis distribution plan are transferred in an Observation of Defects equipment;
S5: described Observation of Defects equipment draws the weight of true and false signal in every class prediction defect according to described wafer defect preanalysis distribution plan;
S6: described Observation of Defects equipment is chosen some different classes of defects according to the weight of true and false signal in prediction defect and observed in described wafer all defect, to obtain the distribution plan of all defect complexion kind;
Wherein, in prediction defect, the weight of true signal is larger, and the quantity that such defect is chosen is more.
Said method, wherein, is written to described wafer defect distribution file by described wafer defect checkout equipment by identifying the defect characteristic signal in defect described in each.
Said method, wherein, the quantitative range of every class prediction defect is 1～5.
Said method, wherein, described defect characteristic signal comprises defective locations signal, defect size signal, the bright dark signal of defect, catches defect channel signal.
Said method, wherein, described glitch is for disturbing the noise signal of defect characteristic signal.
Said method, wherein, described true signal is defect characteristic signal.
Said method, wherein, in described S6, the quantity of choosing the defect of different defect characteristic signals accounts for 10% of all described defects count.
Said method, wherein, in described S6, observes the defect of choosing different defect characteristic signals, first show that the complexion classification of the defect of choosing different defect characteristic signals distributes, thereby according to quantity, calculates in proportion and draw the distribution plan of all defect complexion kind.
Technique scheme tool has the following advantages or beneficial effect:
By defect preanalysis distribution plan is carried out to the express-analysis of true and false defect, the morphology analysis quantity of all defect on wafer is carried out to specific aim and choose, reduced and chosen at random the waste of resource and the increase of production cost that rear defect analysis brings.
Accompanying drawing explanation
With reference to appended accompanying drawing, to describe more fully embodiments of the invention.Yet appended accompanying drawing only, for explanation and elaboration, does not form limitation of the scope of the invention.
Fig. 1 is the schematic diagram that circuit optical imagery transforms into data gray scale image;
Fig. 2 is the distribution plan that has the final defect kind of 1000 defects;
Fig. 3 is the inventive method process flow diagram;
Fig. 4 is overall defect distributed number figure on wafer of the present invention;
Fig. 5 is wafer defect preanalysis distribution plan of the present invention;
Fig. 6 is the true and false signal weight subdivision of the every class prediction defect of the present invention Butut;
Fig. 7 is the complexion kind distribution plan of all defect of the present invention.
Embodiment
The invention discloses a kind of analytical approach of integrated circuit defect, Fig. 3 is the inventive method process flow diagram, as shown in Figure 3, and S1 a: wafer is provided, has some defects on this wafer, S2: detect wafer and the defect characteristic signal that identifies in each defect obtains a wafer defect distribution file by an optical defect checkout equipment (not shown), by wafer defect checkout equipment, the defect characteristic signal identifying in each defect is written to wafer defect distribution file, this defect characteristic signal is a kind of algorithm, concrete, by the microscopic examination wafer in optical defect checkout equipment and obtain the optical imagery on wafer, afterwards, optical imagery conversion on wafer is changed into the data image (shown in Fig. 1) that the different bright dull grays rank of serving as reasons represent, by defect characteristic signal adjacent on wafer, relatively draw defect position again, thereby obtain wafer defect distribution file, thereby in wafer defect distribution file, draw a wafer defect total points Butut, as shown in Figure 4.
S3: optical defect checkout equipment is classified to all defect by defect characteristic signal, and choose the prediction defect of some in every class defect, the quantity of every class prediction defect can be identical also can be different, and form a wafer defect preanalysis distribution plan, the classification of the defect characteristic signal that different wafer defect checkout equipments can be identified is different with quantity, preferably, in the present embodiment, each defect has defect characteristic signal, this defect characteristic signal comprises defective locations signal, defect size signal, the bright dark signal of defect, catch defect channel signal and noise signal, the classification of the defect characteristic signal that different wafer defect checkout equipments can be identified is different with quantity, preferably, optical defect checkout equipment is classified to all defect by defective locations signal, the present embodiment is divided into optical channel 1, optical channel 2, logic area and memory block, Fig. 5 is wafer defect preanalysis distribution plan of the present invention, as shown in Figure 5, the prediction defect that optical defect checkout equipment is chosen in every class defect, the quantitative range of every class prediction defect is 1～5, draw wafer defect preanalysis distribution plan.
S4: wafer defect total points Butut and wafer defect preanalysis distribution plan are transferred to an Observation of Defects equipment (not shown); S5: Observation of Defects equipment draws the weight of true and false signal in every class prediction defect according to wafer defect preanalysis distribution plan; Concrete, by Observation of Defects equipment, the prediction defect in optical channel 1, optical channel 2, logic area and memory block is carried out to the express-analysis of true and false signal, preferably, true signal is defect characteristic signal, glitch is for disturbing the noise signal of defect characteristic signal, and Fig. 6 is the true and false signal weight subdivision of the every class prediction defect of the present invention Butut, as shown in Figure 6, draw the weight of the true and false signal of every class prediction defect, i.e. true and false signal shared ratio in every class prediction defect.
S6: Observation of Defects equipment is chosen some different classes of defects according to the weight of true and false signal in prediction defect and observed in wafer all defect, in all defect, choose the defect of different defective locations signals, in prediction defect, the weight of true signal is larger, the quantity that such defect is chosen is more, preferably, the quantity of choosing the defect of different defect characteristic signals accounts for 10% of all defect quantity, the complexion classification that first draws the defect of choosing different defect characteristic signals distributes, thereby according to quantity, calculate in proportion and draw the distribution plan of all defect complexion kind, concrete, in the present embodiment, in all 1000 defects, choose the defect of 100 different defect characteristic signals, and by Observation of Defects equipment, these 100 defects are carried out to observation analysis, show that noise signal is 50, bulky grain defect is 24, granule defect is 13, disconnection defect is 7, scratch defect is 6, thereby according to this quantity, calculate in proportion and draw the distribution plan of all defect complexion kind, Fig. 7 is the complexion kind distribution plan of all defect of the present invention.
To sum up, the present invention draws wafer defect distribution file and wafer defect total points Butut by optical defect checkout equipment, and different types of defect characteristic signal sampling is generated to defect preanalysis distribution plan, and by electron microscope, defect preanalysis distribution plan is carried out to the express-analysis of true and false defect, then on this basis the morphology analysis quantity of all defect on wafer is carried out to specific aim and choose, finally obtain a more realistic defect kind distribution plan
For a person skilled in the art, read after above-mentioned explanation, various changes and modifications undoubtedly will be apparent.Therefore, appending claims should be regarded whole variations and the correction of containing true intention of the present invention and scope as.Within the scope of claims, scope and the content of any and all equivalences, all should think and still belong to the intent and scope of the invention.
Claims (8)
1. an analytical approach for integrated circuit defect, is characterized in that, described method comprises:
S1 a: wafer that comprises some defects is provided;
S2: detect described wafer and identify the defect characteristic signal in defect described in each by an optical defect checkout equipment and obtain a wafer defect distribution file, thereby draw a wafer defect total points Butut in described wafer defect distribution file;
S3: described optical defect checkout equipment is classified to all described defects by described defect characteristic signal, and in every class defect, choose the prediction defect of some, thus draw a wafer defect preanalysis distribution plan;
S4: described wafer defect total points Butut and described wafer defect preanalysis distribution plan are transferred in an Observation of Defects equipment;
S5: described Observation of Defects equipment draws the weight of true and false signal in every class prediction defect according to described wafer defect preanalysis distribution plan;
S6: described Observation of Defects equipment is chosen some different classes of defects according to the weight of true and false signal in prediction defect and observed in described wafer all defect, to obtain the distribution plan of all defect complexion kind;
Wherein, in prediction defect, the weight of true signal is larger, and the quantity that such defect is chosen is more.
2. a kind of analytical approach of integrated circuit defect as claimed in claim 1, is characterized in that, by described wafer defect checkout equipment, by identifying the defect characteristic signal in defect described in each, is written to described wafer defect distribution file.
3. a kind of analytical approach of integrated circuit defect as claimed in claim 1, is characterized in that, the quantitative range of every class prediction defect is 1～5.
4. a kind of analytical approach of integrated circuit defect as claimed in claim 1, is characterized in that, described defect characteristic signal comprises defective locations signal, defect size signal, the bright dark signal of defect, catches defect channel signal.
5. a kind of analytical approach of integrated circuit defect as claimed in claim 1, is characterized in that, described glitch is for disturbing the noise signal of defect characteristic signal.
6. a kind of analytical approach of integrated circuit defect as claimed in claim 1, is characterized in that, described true signal is defect characteristic signal.
7. a kind of analytical approach of integrated circuit defect as claimed in claim 1, is characterized in that, in described S6, the quantity of choosing the defect of different defect characteristic signals accounts for 10% of all described defects count.
8. a kind of analytical approach of integrated circuit defect as claimed in claim 7, it is characterized in that, in described S6, the defect of different defect characteristic signals is chosen in observation, the complexion classification that first draws the defect of choosing different defect characteristic signals distributes, thereby according to quantity, calculates in proportion and draw the distribution plan of all defect complexion kind.
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108269748A (en) * | 2018-01-23 | 2018-07-10 | 德淮半导体有限公司 | The detection method of wafer surface defects after a kind of CMP |
| CN109065468A (en) * | 2018-09-12 | 2018-12-21 | 上海华力微电子有限公司 | Defect filtration system and filter method and computer storage medium |
| CN109493311A (en) * | 2017-09-08 | 2019-03-19 | 上海宝信软件股份有限公司 | A kind of random defect picture mode identification and matching process and system |
| CN109712136A (en) * | 2018-12-29 | 2019-05-03 | 上海华力微电子有限公司 | A kind of method and device for analyzing semiconductor crystal wafer |
| CN110969175A (en) * | 2018-09-29 | 2020-04-07 | 长鑫存储技术有限公司 | Wafer processing method and device, storage medium and electronic equipment |
| CN113095438A (en) * | 2021-04-30 | 2021-07-09 | 上海众壹云计算科技有限公司 | Wafer defect classification method and device, system, electronic equipment and storage medium thereof |
| CN113424107A (en) * | 2019-02-25 | 2021-09-21 | 应用材料以色列公司 | System and method for detecting rare random defects |
| WO2021249361A1 (en) * | 2020-06-08 | 2021-12-16 | 长鑫存储技术有限公司 | Wafer defect analyzing method, system, device and medium |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05232033A (en) * | 1992-02-26 | 1993-09-07 | Hitachi Ltd | Pattern defect inspecting method and device thereof |
| CN1670938A (en) * | 2004-03-16 | 2005-09-21 | 旺宏电子股份有限公司 | Method and device for analyzing defects of an integrated circuit wafer |
| JP2007003459A (en) * | 2005-06-27 | 2007-01-11 | Tokyo Seimitsu Co Ltd | Flaw inspection device of image, visual examination device and flaw inspection method of image |
| US20070053580A1 (en) * | 2005-09-05 | 2007-03-08 | Akio Ishikawa | Image defect inspection apparatus, image defect inspection system, defect classifying apparatus, and image defect inspection method |
| CN102610541A (en) * | 2012-04-20 | 2012-07-25 | 郑海鹏 | Location method for defect points of integrated circuit |
| CN102931116A (en) * | 2012-11-12 | 2013-02-13 | 上海华力微电子有限公司 | Synchronous defect detecting method for memorizer |
| CN103606529A (en) * | 2013-10-23 | 2014-02-26 | 上海华力微电子有限公司 | Method and device for improving defect classification accuracy |
-
2014
- 2014-07-28 CN CN201410163560.9A patent/CN104062305B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05232033A (en) * | 1992-02-26 | 1993-09-07 | Hitachi Ltd | Pattern defect inspecting method and device thereof |
| CN1670938A (en) * | 2004-03-16 | 2005-09-21 | 旺宏电子股份有限公司 | Method and device for analyzing defects of an integrated circuit wafer |
| JP2007003459A (en) * | 2005-06-27 | 2007-01-11 | Tokyo Seimitsu Co Ltd | Flaw inspection device of image, visual examination device and flaw inspection method of image |
| US20070053580A1 (en) * | 2005-09-05 | 2007-03-08 | Akio Ishikawa | Image defect inspection apparatus, image defect inspection system, defect classifying apparatus, and image defect inspection method |
| CN102610541A (en) * | 2012-04-20 | 2012-07-25 | 郑海鹏 | Location method for defect points of integrated circuit |
| CN102931116A (en) * | 2012-11-12 | 2013-02-13 | 上海华力微电子有限公司 | Synchronous defect detecting method for memorizer |
| CN103606529A (en) * | 2013-10-23 | 2014-02-26 | 上海华力微电子有限公司 | Method and device for improving defect classification accuracy |
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109493311A (en) * | 2017-09-08 | 2019-03-19 | 上海宝信软件股份有限公司 | A kind of random defect picture mode identification and matching process and system |
| CN108269748A (en) * | 2018-01-23 | 2018-07-10 | 德淮半导体有限公司 | The detection method of wafer surface defects after a kind of CMP |
| CN109065468A (en) * | 2018-09-12 | 2018-12-21 | 上海华力微电子有限公司 | Defect filtration system and filter method and computer storage medium |
| CN109065468B (en) * | 2018-09-12 | 2020-12-04 | 上海华力微电子有限公司 | Defect filtering system, defect filtering method and computer storage medium |
| CN110969175B (en) * | 2018-09-29 | 2022-04-12 | 长鑫存储技术有限公司 | Wafer processing method and device, storage medium and electronic equipment |
| CN110969175A (en) * | 2018-09-29 | 2020-04-07 | 长鑫存储技术有限公司 | Wafer processing method and device, storage medium and electronic equipment |
| CN109712136A (en) * | 2018-12-29 | 2019-05-03 | 上海华力微电子有限公司 | A kind of method and device for analyzing semiconductor crystal wafer |
| CN109712136B (en) * | 2018-12-29 | 2023-07-28 | 上海华力微电子有限公司 | Method and device for analyzing semiconductor wafer |
| CN113424107A (en) * | 2019-02-25 | 2021-09-21 | 应用材料以色列公司 | System and method for detecting rare random defects |
| CN113424107B (en) * | 2019-02-25 | 2023-09-19 | 应用材料以色列公司 | System and method for detecting rare random defects |
| US11860551B2 (en) | 2019-02-25 | 2024-01-02 | Applied Materials Israel Ltd. | System and method for detecting rare stochastic defects |
| WO2021249361A1 (en) * | 2020-06-08 | 2021-12-16 | 长鑫存储技术有限公司 | Wafer defect analyzing method, system, device and medium |
| CN113095438A (en) * | 2021-04-30 | 2021-07-09 | 上海众壹云计算科技有限公司 | Wafer defect classification method and device, system, electronic equipment and storage medium thereof |
| CN113095438B (en) * | 2021-04-30 | 2024-03-15 | 上海众壹云计算科技有限公司 | Wafer defect classification method, device and system thereof, electronic equipment and storage medium |
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