CN105742200B - A method of promoting time breakdown test validity - Google Patents
A method of promoting time breakdown test validity Download PDFInfo
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- CN105742200B CN105742200B CN201610107358.3A CN201610107358A CN105742200B CN 105742200 B CN105742200 B CN 105742200B CN 201610107358 A CN201610107358 A CN 201610107358A CN 105742200 B CN105742200 B CN 105742200B
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- chip
- leakage current
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- numberical range
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
Abstract
The present invention provides a kind of method promoting time breakdown test validity, sets the numberical range of chip leakage current, if the leakage current for measuring obtained chip is located within the numberical range, the test of time breakdown is carried out to the chip；If the leakage current for measuring obtained chip is located at except the numberical range, the test of time breakdown is not carried out to the chip.Method provided by the invention only needs to carry out electric leakage current test to chip, can screen out can generate dysgenic chip to TDDB tests, therefore when carrying out TDDB tests, it not will produce and measure the time even if test to maximum, also the phenomenon that being unable to get test result, to avoid the testing time for delaying time breakdown, the test device of damage time breakdown is also avoided.
Description
Technical field
The present invention relates to semiconductor test field, more particularly to a kind of method promoting time breakdown test validity.
Background technology
Wafer scale reliability test project through when dielectric breakdown (TDDB, time dependent dielectric
Breakdown), also cry with time correlation dielectric breakdown, refer to applying constant voltage on the grid of chip, by one timing
Between post tensioned unbonded prestressed concrete oxide layer can puncture, this period of process is exactly the out-of-service time of chip.Since wafer maker is being made
When making chip, the location of each chips are different, and after manufacturing process, full wafer wafer deforms upon, and leads to crystalline substance
Segment chip on circle generates the case where performance is different from other chips.Such as the mistake of chip not all on wafer
The effect time is all consistent, considers that the out-of-service time of segment chip is long and test is sent out in long testing time section in order to prevent
It is raw abnormal, maximum being set in test program and measuring the time, the time is measured when reaching maximum, no matter whether the chip fails,
The test that will stop the chip, carries out next step operation.It can not but there are intrinsic differences, out-of-service time between chip
It accurately estimates, therefore the maximum setting for measuring the time is well-to-do, if the proper testing time is 6000s, sets maximum and measure the time
For 10000s.
Nowadays TDDB tests frequently encounter the phenomenon that wafer out-of-flatness or expansion of silicon chip heat, even if by adjusting test
Method, such as the instrument probes card that will be tested thermally contact in advance for a long time with silicon chip progress, but due to the defect of chip itself, still
The test devices such as probe card skids off metal pad, probe card and chip welding spot or bump contact is bad, which can occur, to be perceived
Situation, due to the testing time do not reach it is maximum measure the time, if do not occur in the test system of test chip it is any as a result,
No manpower is discovered, then will necessarily test continue up to it is maximum measure the time and finish, not only delay the testing time in this way, can also
It causes probe card needle point impaired, or even influences the validity of test data.
It is therefore desirable to improve above-mentioned test method, avoid delaying testing time or damage test device.
Invention content
The present invention provides a kind of method promoting time breakdown test validity, between doing time breakdown test, to core
Piece carries out the test of leakage current, if the value of electric leakage current test is within normal numberical range, time breakdown is carried out to it
Test, if the value of electric leakage current test is not within normal numberical range, then time breakdown test is not carried out to it, this
Kind method can also avoid the test device of damage time breakdown to avoid the testing time of time breakdown is delayed.
In order to achieve the above objectives, the present invention provides a kind of method promoting time breakdown test validity, setting chip leakage
The numberical range of electric current is located at if measuring the obtained leakage current of chip within the numberical range, to the chip into passing through
When the test that punctures；It is located at except the numberical range if measuring the obtained leakage current of chip, not to the chip into passing through
When the test that punctures.
Preferably, setting the method for the numberical range of chip leakage current as the leakage current of each chip on statistics wafer
Numerical value takes being averaged for leakage current numerical value that all tests obtain to be worth to the first median, by the maximum value in leakage current numerical value
It is averaged to obtain the first average value with the first median, the minimum value in leakage current numerical value is averaged with the first median
The second average value is obtained, then the minimum value of the numberical range is the second average value, and the maximum value of the numberical range is
First average value.
Preferably, setting the method for the numberical range of chip leakage current by the chip uniform sampling on wafer and to test
The leakage current numerical value of each sampling chip takes being averaged for leakage current numerical value that all tests obtain to be worth to the second median, will
Maximum value in leakage current numerical value is averaged to obtain third average value with the second median, by the minimum value in leakage current numerical value
It is averaged to obtain the 4th average value with the second median, then the minimum value of the numberical range is the 4th average value, described
The maximum value of numberical range is third average value.
Preferably, the method for the leakage current of measuring chip is the weld pad of the probe card and chip that will be connected to test power supply
Or bump contact.
Preferably, probe card is also connect with survey current device, surveys current device and connect with test machine, used in test machine
C Plus Plus programming setting is located at when the leakage current for the chip that probe card measures within the numberical range, then in test machine
" qualification " is shown on screen；When the leakage current for the chip that probe card measures is located at except the numberical range, then testing
" unqualified " is shown on machine screen.
Preferably, the leakage current of the chip measured when probe card is less than the numberical range, then test machine screen
On also show that first reports an error code；When the leakage current for the chip that probe card measures is more than the numberical range, then test machine
Also show that second reports an error code on screen.
Preferably, collected the chip that obtained leakage current numerical value is located at except the numberical range is measured, and again
Leakage current is measured, if the leakage current of the chip measured again is located within the numberical range, to the chip into passing through
When the test that punctures；If the leakage current of the chip measured again is located at except the numberical range, not to the chip into
The test of row time breakdown.
Preferably, when measuring leakage current again, probe card enters the weld pad of chip or the depth of convex block different from for the first time
Probe card enters the weld pad of chip or the depth of convex block when the leakage current of measuring chip.
Compared with prior art, the beneficial effects of the invention are as follows：It is effective that the present invention provides a kind of promotion time breakdown test
Property method, set the numberical range of chip leakage current, if measure the obtained leakage current of chip be located at the numberical range it
It is interior, then the test of time breakdown is carried out to the chip；If the leakage current for measuring obtained chip is located at except the numberical range,
The test of time breakdown is not carried out to the chip then.Method provided by the invention only needs to carry out electric leakage current test to chip, you can
Dysgenic chip can be generated to TDDB tests by screening out, therefore when carrying out TDDB tests, not will produce even if test to most
The phenomenon that measuring the time greatly, being also unable to get test result, to avoid the testing time for delaying time breakdown, also avoids damaging
The test device of time breakdown.
Description of the drawings
Fig. 1 is the flow chart provided by the invention for promoting time breakdown test validity method.
Specific implementation mode
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, below in conjunction with the accompanying drawings to the present invention
Specific implementation mode be described in detail.
Fig. 1 is please referred to, the present invention provides a kind of method promoting time breakdown test validity, specifically includes following step
Suddenly：
Step 1：There is provided a piece of wafer to be tested, this kind of chip leakage is calculated in the leakage current of chip on test wafer
The numberical range of electric current, specific there are two types of computational methods：
Method 1：The leakage current numerical value for measuring and counting each chip on wafer takes all electric leakage fluxions tested and obtained
Being averaged for value is worth to the first median m, by leakage current numerical value peak and the first median m be averaged to obtain first
Average value a, by leakage current numerical value minimum and the first median m be averaged to obtain the second average value b, then this kind of chip
The numberical range of leakage current is [a, b].
Method 2：By the chip uniform sampling on wafer and the leakage current numerical value of each sampling chip of test, such as in wafer
On, a chips all are taken every five chips in horizontally-arranged and tandem, the leakage current numerical value of the chip of above-mentioned acquirement is measured, takes institute
There is being averaged for leakage current numerical value that test obtains to be worth to the second median n, it will be in the peak and second in leakage current numerical value
Between value n be averaged to obtain third average value c, the minimum in leakage current numerical value is averaged to obtain with the second median n
4th average value d, then the numberical range of this kind of chip leakage current is [c, d].
Step 2：It is not that each chips all need to receive according to the difference of technique during wafer manufactures
TDDB is tested, therefore the chip for receiving TDDB tests will be needed to pick out, and the test of leakage current, the method for test are carried out to it
For：The probe card that will be connected to test machine penetrates the weld pad or convex block of chip, and test machine includes a computer and a power supply, electricity
Source is connect with probe card circuitry, and power supply provides electric energy for probe card, then carry electric energy probe card penetrate on chip two can
When the weld pad or convex block of forming circuit, electric current is produced in circuit, and the electric signal in circuit, which is fed back to, can test electricity
In the device for flowing size, which feeds back to computer by the result measured, is arranged using C Plus Plus programming in computer, will
Measured in step 1 leakage current numberical range input program in, when device feedback current value be located in the numberical range,
" qualification " printed words are then shown on the computer screen；When device feedback current value be located at except the numberical range, then counting
" unqualified " printed words are shown on calculation machine screen, and carry out the test of next chips.
Preferably, if the current value of device feedback is less than a or c, " do not conform in addition to showing on the computer screen
Other than lattice " printed words, also showing that first reports an error code, short circuit has occurred in the first code representative chip that reports an error, if device feedback
Current value is more than b or d, then other than showing " unqualified " printed words on the computer screen, also shows that second reports an error code,
Second reports an error code representative probe card and chip poor contact or mistake occurs for test setting.
When will measure leakage current, the chip of display " qualification " printed words is collected on computer screen, and TDDB tests are carried out to it,
In this way, even if test to maximum measure the time, the phenomenon that being unable to get test result will not be generated, to avoid delaying through when
The testing time of breakdown also avoids the test device of damage time breakdown.
Preferably, being collected the chip that obtained leakage current numerical value is located at except the numberical range is measured, and measure again
Leak hunting electric current, when measuring leakage current again, is analyzed in conjunction with the code that reports an error that occurs when measuring for the first time, such as occurs that the
Two report an error code, then increase probe card and penetrate the depth of chip and carry out the measurement of leakage current, such as occur that first reports an error code,
The measurement that probe card penetrates the depth progress leakage current of chip is then reduced, or whether the setting of detection test device mistake occurs
It is measured again afterwards.
If the leakage current of the chip measured again is located within the numberical range, still to the chip into when passing through
The test of breakdown；If the leakage current of the chip measured again is located at except the numberical range, which is not carried out
The test of time breakdown.In this way can to avoid make the chip that script leakage current is located within the numberical range due to measuring for the first time
Generation is wrong and is " unqualified " by computer-made decision, improves the utilization rate of chip testing.
Obviously, those skilled in the art can carry out invention spirit of the various modification and variations without departing from the present invention
And range.If these modifications and changes of the present invention is within the scope of the claims of the present invention and its equivalent technology, then
The present invention is also intended to including these modification and variations.
Claims (6)
1. a kind of method promoting time breakdown test validity, which is characterized in that the numberical range of chip leakage current is set, if
The method for determining the numberical range of chip leakage current is to count the leakage current numerical value of each chip on wafer, and all tests is taken to obtain
Being averaged for leakage current numerical value be worth to the first median, the maximum value in leakage current numerical value is averaged with the first median
The first average value is obtained, the minimum value in leakage current numerical value is averaged to obtain the second average value with the first median, then institute
The minimum value for stating numberical range is the second average value, and the maximum value of the numberical range is the first average value；Or, by wafer
On chip uniform sampling and test the leakage current numerical value of each sampling chip, take the flat of all leakage current numerical value tested and obtained
It is worth to the second median, the maximum value in leakage current numerical value is averaged to obtain third average value with the second median,
Minimum value in leakage current numerical value is averaged to obtain the 4th average value with the second median, then the minimum of the numberical range
Value is the 4th average value, and the maximum value of the numberical range is third average value；
If the leakage current for measuring obtained chip is located within the numberical range, the survey of time breakdown is carried out to the chip
Examination；If the leakage current for measuring obtained chip is located at except the numberical range, the survey of time breakdown is not carried out to the chip
Examination.
2. the method for promoting time breakdown test validity as described in claim 1, which is characterized in that the electric leakage of measuring chip
The method of stream is the weld pad or bump contact of the probe card and chip that will be connected to test power supply.
3. the method for promoting time breakdown test validity as claimed in claim 2, which is characterized in that probe card is also electric with survey
Device connection is flowed, current device is surveyed and is connect with test machine, using C Plus Plus programming setting when probe card measures to obtain in test machine
The leakage current of chip be located within the numberical range, then show " qualification " on test machine screen；When probe card measures
The leakage current of the chip arrived is located at except the numberical range, then shows " unqualified " on test machine screen.
4. the method for promoting time breakdown test validity as claimed in claim 3, which is characterized in that when probe card measures
The leakage current of the chip arrived is less than the minimum value of the numberical range, then also shows that first reports an error code on test machine screen；When
The leakage current for the chip that probe card measures is more than the maximum value of the numberical range, then also shows second on test machine screen
Report an error code.
5. the method for promoting time breakdown test validity as described in claim 1, which is characterized in that the leakage for obtaining measurement
Current values are located at the collection of the chip except the numberical range, and measure leakage current again, if the chip measured again
Leakage current be located within the numberical range, then to the chip carry out time breakdown test；If the core measured again
The leakage current of piece is located at except the numberical range, then the test of time breakdown is not carried out to the chip.
6. the method for promoting time breakdown test validity as claimed in claim 5, which is characterized in that measure leakage current again
When, probe card enter chip weld pad or convex block depth different from measuring chip for the first time leakage current when probe card enter chip
Weld pad or convex block depth.
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| CN201610107358.3A CN105742200B (en) | 2016-02-26 | 2016-02-26 | A method of promoting time breakdown test validity |
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| CN108231619B (en) * | 2018-01-22 | 2020-05-19 | 无锡昌德微电子股份有限公司 | Detection method for power semiconductor chip |
| CN113009321B (en) * | 2021-03-04 | 2022-04-08 | 深圳市金泰克半导体有限公司 | Wafer leakage current testing method and device, wafer-level tester and storage medium |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104078343A (en) * | 2014-07-02 | 2014-10-01 | 武汉新芯集成电路制造有限公司 | Failure analysis method for gate oxide defect original appearance |
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| JPH06201761A (en) * | 1992-12-28 | 1994-07-22 | Kawasaki Steel Corp | Aging dielectric breakdown characteristic measuring method for insulating film |
| US6602729B2 (en) * | 2001-07-13 | 2003-08-05 | Infineon Technologies Ag | Pulse voltage breakdown (VBD) technique for inline gate oxide reliability monitoring |
| JP4640834B2 (en) * | 2006-04-27 | 2011-03-02 | 新電元工業株式会社 | Reliability test equipment |
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| CN104078343A (en) * | 2014-07-02 | 2014-10-01 | 武汉新芯集成电路制造有限公司 | Failure analysis method for gate oxide defect original appearance |
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