CN105742200A - Method for improving effectiveness of time dependent breakdown test - Google Patents
Method for improving effectiveness of time dependent breakdown test Download PDFInfo
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- CN105742200A CN105742200A CN201610107358.3A CN201610107358A CN105742200A CN 105742200 A CN105742200 A CN 105742200A CN 201610107358 A CN201610107358 A CN 201610107358A CN 105742200 A CN105742200 A CN 105742200A
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- leakage current
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
Abstract
The invention provides a method for improving effectiveness of time dependent breakdown test. The method comprises the following steps of setting a numerical value range of leakage current of a chip; carrying out time dependent breakdown test on the chip if the leakage current, obtained through measurement, of the chip is within the numerical value range; and not carrying out time dependent breakdown test on the chip if the leakage current, obtained through measurement, of the chip is beyond the numerical value range. According to the method provided by the invention, leakage current test is only needed to be carried out on the chip, chips which have unfavorable influence on time dependent dielectric breakdown (TDDB) test can be screened out, thus, a phenomenon that a test result cannot be acquired even the test is carried out to maximum measurement time during TDDB test is avoided, the time dependent breakdown test time is prevented from being delayed, and a time dependent breakdown test device is also prevented from being damaged.
Description
Technical field
The present invention relates to semiconductor test field, particularly to a kind of method promoting time breakdown test validity.
Background technology
Wafer scale reliability testing project through time dielectric breakdown (TDDB, timedependentdielectricbreakdown), also cry and time correlation dielectric breakdown, refer to applying constant voltage on the grid of chip, puncturing through certain time post tensioned unbonded prestressed concrete oxide layer, process is exactly out-of-service time of chip during this period of time.Owing to wafer maker is when manufacturing chip, each chips location is different, and after manufacturing process, full wafer wafer deforms upon, and causes that the segment chip on wafer produces performance and is different from the situation of other chip.As all consistent in the out-of-service time of chip not all on wafer, consider that the out-of-service time of segment chip is long and abnormal in order to prevent in this long testing time section build-in test generation, the maximum measurement time can be set in test program, when reaching the maximum measurement time, no matter whether this chip lost efficacy, capital stops the test of this chip, carries out next step operation.But there is intrinsic difference between chip, its out-of-service time cannot accurately be estimated, therefore the setting of maximum measurement time is well-to-do, if the proper testing time is 6000s, sets the maximum measurement time as 10000s.
Nowadays TDDB test is frequently encountered by wafer out-of-flatness or the phenomenon of silicon chip heat expansion, even if by adjusting method of testing, as the instrument probes card of test carried out thermally contact in advance for a long time with silicon chip, but the defect due to chip self, probe card still can be occurred to skid off metal pad, probe card and chip welding spot or bump contact bad wait test device cannot the situation of perception, owing to the testing time does not arrive the maximum measurement time, any result does not occur in the test system test chip, if discovering without manpower, then will necessarily test and continue up to the maximum measurement time and finish, so not only delay the testing time, probe card needle point also can be caused impaired, the even effectiveness of impact test data.
It is therefore desirable to above-mentioned method of testing is improved, it is to avoid delay the testing time or damage test device.
Summary of the invention
The present invention provides a kind of method promoting time breakdown test validity, doing between time breakdown test, chip is carried out the test of leakage current, if the value of leakage current test is within normal numerical range, then it is carried out time breakdown test, if the value of leakage current test is not within normal numerical range, then then it is not carried out time breakdown test, this method can avoid delaying the testing time of time breakdown, also avoids damaging the test device of time breakdown.
For reaching above-mentioned purpose, the present invention provides a kind of method promoting time breakdown test validity, the numerical range of setting chip leakage current, if the leakage current measuring the chip obtained is positioned within described numerical range, then this chip carries out the test of time breakdown；If the leakage current measuring the chip obtained is positioned at outside described numerical range, then this chip is not carried out the test of time breakdown.
As preferably, the method of the numerical range of setting chip leakage current is the leakage current numerical value of each chip on statistics wafer, the meansigma methods taking the leakage current numerical value that all tests obtain obtains the first intermediate value, maximum in leakage current numerical value and the first intermediate value are averaged and obtains the first meansigma methods, minima in leakage current numerical value and the first intermediate value are averaged and obtains the second meansigma methods, then the minima of described numerical range is the second meansigma methods, and the maximum of described numerical range is the first meansigma methods.
As preferably, the method of the numerical range of setting chip leakage current is by the chip uniform sampling on wafer the leakage current numerical value testing each sampling chip, the meansigma methods taking the leakage current numerical value that all tests obtain obtains the second intermediate value, maximum in leakage current numerical value and the second intermediate value are averaged and obtains the 3rd meansigma methods, minima in leakage current numerical value and the second intermediate value are averaged and obtains the 4th meansigma methods, then the minima of described numerical range is the 4th meansigma methods, and the maximum of described numerical range is the 3rd meansigma methods.
As preferably, the method for the leakage current of measuring chip is will be connected to the probe card of test power supply and the weld pad of chip or bump contact.
As preferably, probe card is also connected with survey current device, survey current device to be connected with test machine, test machine uses the leakage current that C Plus Plus programming setting measures, when probe card, the chip obtained be positioned within described numerical range, then on test machine screen, show " qualified "；When probe card measures outside the leakage current of chip obtained is positioned at described numerical range, then on test machine screen, show " defective ".
As preferably, when probe card measures the leakage current of the chip obtained less than described numerical range, then test machine screen also showing, first reports an error code；When probe card measures the leakage current of chip obtained more than described numerical range, then test machine screen also showing, second reports an error code.
As preferably, the leakage current numerical value that measurement obtains being positioned at the chip outside described numerical range and collects, and again measure leakage current, if the leakage current again measuring the chip obtained is positioned within described numerical range, then this chip is carried out the test of time breakdown；If the leakage current again measuring the chip obtained is positioned at outside described numerical range, then this chip is not carried out the test of time breakdown.
As preferably, when again measuring leakage current, when the degree of depth of weld pad or projection that probe card enters chip differs from the leakage current of measuring chip first, probe card enters the weld pad of chip or the degree of depth of projection.
Compared with prior art, the invention has the beneficial effects as follows: the present invention provides a kind of method promoting time breakdown test validity, the numerical range of setting chip leakage current, if the leakage current measuring the chip obtained is positioned within described numerical range, then carries out the test of time breakdown to this chip；If the leakage current measuring the chip obtained is positioned at outside described numerical range, then this chip is not carried out the test of time breakdown.Method provided by the invention only needs chip is carried out leakage current test, can screen out and TDDB test can be produced dysgenic chip, therefore when carrying out TDDB test, even if the test extremely maximum measurement time will not be produced, also the phenomenon of test result cannot be obtained, thus avoiding delaying the testing time of time breakdown, also avoid damaging the test device of time breakdown.
Accompanying drawing explanation
Fig. 1 is the flow chart of lifting time breakdown test validity method provided by the invention.
Detailed description of the invention
Understandable for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
Refer to Fig. 1, the present invention provides a kind of method promoting time breakdown test validity, specifically includes following steps:
Step one: a piece of wafer to be tested is provided, the leakage current of chip on test wafer, calculate the numerical range obtaining this kind of chip leakage current, specifically have two kinds of computational methods:
Method 1: measure and add up the leakage current numerical value of each chip on wafer, the meansigma methods taking the leakage current numerical value that all tests obtain obtains the first intermediate value m, peak in leakage current numerical value and the first intermediate value m are averaged and obtained the first meansigma methods a, minimum in leakage current numerical value and the first intermediate value m are averaged and obtained the second meansigma methods b, then the numerical range of this kind of chip leakage current is [a, b].
Method 2: by the chip uniform sampling on wafer the leakage current numerical value testing each sampling chip, as on wafer, horizontally-arranged with tandem on all take a chips every five chips, measure the leakage current numerical value of the chip of above-mentioned acquirement, the meansigma methods taking the leakage current numerical value that all tests obtain obtains the second intermediate value n, peak in leakage current numerical value and the second intermediate value n are averaged and obtained the 3rd meansigma methods c, minimum in leakage current numerical value and the second intermediate value n are averaged and obtained the 4th meansigma methods d, then the numerical range of this kind of chip leakage current is [c, d].
nullStep 2: in the process that wafer manufactures，Difference according to technique，It is not that each chips all needs to accept TDDB test，Therefore the chip accepting TDDB test will be needed to pick out，It is carried out the test of leakage current，The method of test is: will be connected to the probe card of test machine and penetrates weld pad or the projection of chip，Test machine includes a computer and a power supply，Power supply is connected with probe card circuitry，Power supply provides electric energy for probe card，When then penetrating two weld pads that can form loop or projection on chip with the probe card of electric energy，Create electric current in circuit，The signal of telecommunication in circuit is fed back in the device that can test size of current，The result recorded is fed back to computer by this device，Computer use C Plus Plus programming arrange，By in the numerical range input program recording leakage current in step one，When the current value of device feedback is positioned at described numerical range，Then show " qualified " printed words on the computer screen；Outside the current value of device feedback is positioned at described numerical range, then shows " defective " printed words on the computer screen, and carry out the test of next chips.
Preferably, if the current value of device feedback is less than a or c, then except showing " defective " printed words on the computer screen, also display first reports an error code, the first code representative chip that reports an error there occurs short circuit, if the current value of device feedback is more than b or d, then except display " defective " printed words on the computer screen, also display second reports an error code, and the second code representative probe card that reports an error makes a mistake with chip loose contact or test setting.
When will measure leakage current, computer screen showing, the chip of " qualified " printed words is collected, it is carried out TDDB test, so, even if test is the maximum measurement time extremely, without producing to obtain the phenomenon of test result, thus avoiding delaying the testing time of time breakdown, also avoid damaging the test device of time breakdown.
Preferably, the leakage current numerical value that measurement obtains is positioned at the chip outside described numerical range collect, and again measure leakage current, when again measuring leakage current, it is analyzed in conjunction with the code that reports an error occurred when measuring first, as occurred that, second reports an error code, then increase probe card to penetrate the degree of depth of chip and carry out the measurement of leakage current, as occurred that, first reports an error code, then reduce probe card to penetrate the degree of depth of chip and carry out the measurement of leakage current, or the setting of detection test device whether mistake occurs after measure again.
If the leakage current again measuring the chip obtained is positioned within described numerical range, then still this chip is carried out the test of time breakdown；If the leakage current again measuring the chip obtained is positioned at outside described numerical range, then this chip is not carried out the test of time breakdown.So can avoid making leakage current originally be positioned at the chip within described numerical range is " defective " owing to measurement first makes a mistake by computer-made decision, improves the utilization rate of chip testing.
Obviously, invention can be carried out various change and modification without deviating from the spirit and scope of the present invention by those skilled in the art.If these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to include these change and modification.
Claims (8)
1. the method promoting time breakdown test validity, it is characterised in that the numerical range of setting chip leakage current, if the leakage current measuring the chip obtained is positioned within described numerical range, then carries out the test of time breakdown to this chip；If the leakage current measuring the chip obtained is positioned at outside described numerical range, then this chip is not carried out the test of time breakdown.
2. the method promoting time breakdown test validity as claimed in claim 1, it is characterized in that, the method of the numerical range of setting chip leakage current is the leakage current numerical value of each chip on statistics wafer, the meansigma methods taking the leakage current numerical value that all tests obtain obtains the first intermediate value, maximum in leakage current numerical value and the first intermediate value are averaged and obtains the first meansigma methods, minima in leakage current numerical value and the first intermediate value are averaged and obtains the second meansigma methods, then the minima of described numerical range is the second meansigma methods, the maximum of described numerical range is the first meansigma methods.
3. the method promoting time breakdown test validity as claimed in claim 1, it is characterized in that, the method of the numerical range of setting chip leakage current is by the chip uniform sampling on wafer the leakage current numerical value testing each sampling chip, the meansigma methods taking the leakage current numerical value that all tests obtain obtains the second intermediate value, maximum in leakage current numerical value and the second intermediate value are averaged and obtains the 3rd meansigma methods, minima in leakage current numerical value and the second intermediate value are averaged and obtains the 4th meansigma methods, then the minima of described numerical range is the 4th meansigma methods, the maximum of described numerical range is the 3rd meansigma methods.
4. the method promoting time breakdown test validity as claimed in claim 1, it is characterised in that the method for the leakage current of measuring chip is will be connected to the probe card of test power supply and the weld pad of chip or bump contact.
5. the method promoting time breakdown test validity as claimed in claim 4, it is characterized in that, probe card is also connected with survey current device, survey current device to be connected with test machine, test machine uses C Plus Plus programming the leakage current working as the chip that probe card measurement obtains is set and be positioned within described numerical range, then on test machine screen, show " qualified "；When probe card measures outside the leakage current of chip obtained is positioned at described numerical range, then on test machine screen, show " defective ".
6. the as claimed in claim 5 method promoting time breakdown test validity, it is characterised in that when probe card measures the leakage current minima less than described numerical range of the chip obtained, then also show on test machine screen that first reports an error code；When probe card measures the leakage current of chip the obtained maximum more than described numerical range, then test machine screen also showing, second reports an error code.
7. the method promoting time breakdown test validity as claimed in claim 1, it is characterized in that, the leakage current numerical value that measurement obtains is positioned at the chip outside described numerical range collect, and again measure leakage current, if the leakage current again measuring the chip obtained is positioned within described numerical range, then this chip is carried out the test of time breakdown；If the leakage current again measuring the chip obtained is positioned at outside described numerical range, then this chip is not carried out the test of time breakdown.
8. the method promoting time breakdown test validity as claimed in claim 7, it is characterized in that, when again measuring leakage current, when the degree of depth of weld pad or projection that probe card enters chip differs from the leakage current of measuring chip first, probe card enters the weld pad of chip or the degree of depth of projection.
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| CN201610107358.3A CN105742200B (en) | 2016-02-26 | 2016-02-26 | A method of promoting time breakdown test validity |
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| CN201610107358.3A CN105742200B (en) | 2016-02-26 | 2016-02-26 | A method of promoting time breakdown test validity |
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| CN105742200B CN105742200B (en) | 2018-07-20 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108231619A (en) * | 2018-01-22 | 2018-06-29 | 无锡昌德微电子股份有限公司 | For the detection method of power semiconductor chip |
| CN113009321A (en) * | 2021-03-04 | 2021-06-22 | 深圳市金泰克半导体有限公司 | Wafer leakage current testing method and device, wafer-level tester and storage medium |
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| JPH06201761A (en) * | 1992-12-28 | 1994-07-22 | Kawasaki Steel Corp | Aging dielectric breakdown characteristic measuring method for insulating film |
| US20030013214A1 (en) * | 2001-07-13 | 2003-01-16 | Infineon Technologies North America Corp. | Pulse voltage breakdown (VBD) technique for inline gate oxide reliability monitoring |
| JP2007292675A (en) * | 2006-04-27 | 2007-11-08 | Shindengen Electric Mfg Co Ltd | Reliability testing device |
| CN104078343A (en) * | 2014-07-02 | 2014-10-01 | 武汉新芯集成电路制造有限公司 | Failure analysis method for gate oxide defect original appearance |
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2016
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JPH06201761A (en) * | 1992-12-28 | 1994-07-22 | Kawasaki Steel Corp | Aging dielectric breakdown characteristic measuring method for insulating film |
| US20030013214A1 (en) * | 2001-07-13 | 2003-01-16 | Infineon Technologies North America Corp. | Pulse voltage breakdown (VBD) technique for inline gate oxide reliability monitoring |
| JP2007292675A (en) * | 2006-04-27 | 2007-11-08 | Shindengen Electric Mfg Co Ltd | Reliability testing device |
| CN104078343A (en) * | 2014-07-02 | 2014-10-01 | 武汉新芯集成电路制造有限公司 | Failure analysis method for gate oxide defect original appearance |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108231619A (en) * | 2018-01-22 | 2018-06-29 | 无锡昌德微电子股份有限公司 | For the detection method of power semiconductor chip |
| CN108231619B (en) * | 2018-01-22 | 2020-05-19 | 无锡昌德微电子股份有限公司 | Detection method for power semiconductor chip |
| CN113009321A (en) * | 2021-03-04 | 2021-06-22 | 深圳市金泰克半导体有限公司 | Wafer leakage current testing method and device, wafer-level tester and storage medium |
| CN113009321B (en) * | 2021-03-04 | 2022-04-08 | 深圳市金泰克半导体有限公司 | Wafer leakage current testing method and device, wafer-level tester and storage medium |
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| CN105742200B (en) | 2018-07-20 |
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