JP2009289767A - Manufacturing method of semiconductor device, and the semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a means for easily improving an adhesion strength of wire bonding or bump connection after a probe inspection step to reduce failures in connection, so as to improve reliability. <P>SOLUTION: Before a wire bonding ball or a bump is formed, a probing chip flattening probe 5b is brought into contact so that the probe slides reversely to a sliding direction of a measuring probe and through a probe trace terminal point of the measuring probe. Thus, probing chips 3a and 3b generated during a probe inspection step can be flattened. Since the adhesion strength of the wire bonding ball or the bump is improved as a result, failures in connection can be easily reduced and reliability can be improved. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method of manufacturing a semiconductor device and a semiconductor device in which wire bonding balls or bumps are formed on the electric pad after electrical inspection is performed by contacting a probe needle with an electrode pad.

  In recent years, with the progress of the digital society, there is an increasing demand for higher functionality, smaller size, and lower cost of semiconductor devices. In order to reduce the cost of a semiconductor device, it is effective to increase the number of semiconductor chips collected per wafer. For this reason, the chip area is reduced as the diffusion process is miniaturized. Along with the reduction in the chip area and the increase in the number of pins accompanying the increase in functionality, it has become necessary to reduce the external connection electrode pads existing on the outer peripheral portion of the semiconductor chip and to arrange them at high density. For this reason, it is necessary to further reduce the size of wire bonding balls and bumps used for external connection.

    FIG. 16 is a schematic view showing a conventional method of manufacturing a semiconductor device. After conducting electrical inspection by bringing a probe needle into contact with an electrode pad, a step of forming wire bonding balls or bumps on the electric pad is performed. Show.

Usually, after the semiconductor wafer is diffused, a probe inspection process is performed in which the probe needle 5 is brought into contact with the electrode pad 14 for external connection as shown in FIG. Thereafter, a wire bonding ball 17 is formed on the electrode pad 14 (FIG. 16C), and the semiconductor device is manufactured by wire bonding to the wire bonding ball 17.
Japanese Patent Laid-Open No. 6-267884

  However, according to the conventional method for manufacturing a semiconductor device, when the probe needle 5 is brought into contact with the electrode pad 14, the probe needle 5 slides in the direction of the arrow shown in FIG. Contacted. FIG. 16B shows the state of the electrode pad immediately after the probe inspection process. As described above, since the electrode pad 14 is scraped off by the probe needle 5, the probe trace 2 which is a scraped trace remains on the electrode pad 14. Further, at the end point portion of the probe trace 2, there is probing waste 3 in which electrode pad shavings are accumulated. As described above, the area of the electrode pad 14 has recently been reduced in order to cope with the reduction in chip size and the increase in the number of pins, and the wire bonding ball 17 is placed on the probe trace 2 and the probing waste 3 as shown in FIG. It is necessary to form and connect. Furthermore, it is necessary to reduce the size of the wire bonding ball 17 itself by reducing the area of the electrode pad 14. However, as shown in FIG. 16 (c), since the probing scrap 3 generated in the probe inspection process pushes up the wire bonding ball 17, the bonding between the wire bonding ball 17 and the electrode pad 14 is hindered. Has been a problem, resulting in poor connection and reduced reliability. This problem occurs not only for the wire bond connection method after the probe inspection process but also for the bump connection method such as solder bumps and Au bumps.

  In response to this problem, a technique for resetting the probe trace 2 and the probing waste 3 using a laser has been devised (see, for example, Patent Document 1). In addition, it takes time for the resetting process such as wafer replacement, transfer, and wafer loading.

  In view of the above, an object of the present invention is to easily improve the adhesion strength of wire bonding and bump connection after the probe inspection process, thereby reducing connection failure and improving reliability.

  In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes a method of manufacturing a semiconductor device by contacting a probe needle for measurement with an electrode pad formed on a semiconductor chip in a wafer state and performing an electrical inspection. A step of forming a wire bonding ball or bump on the probe, and before the step of forming the wire bonding ball or bump, the probe of the measurement probe needle has a sliding direction opposite to that of the measurement probe needle. It has a probing waste flattening step in which the probe needle for probing waste flattening is brought into contact so that the probe needle slides in a state of passing through the trace end point.

In addition, a probe card including both the measurement probe needle and the probing dust flattening probe needle is used.
In addition, the probe needle for measurement and the probe needle for flattening the probing waste are formed adjacent to the probe card, and after performing the electrical inspection with the probe needle for measurement on each semiconductor chip, The probing waste flattening step is performed simultaneously with the adjacent probing waste flattening probe needle and the electrical inspection of the adjacent semiconductor chip is performed simultaneously with the measurement probe needle.

  Further, a probe card provided with a measuring and probing waste flattening probe needle having both functions of the measurement probe needle and the probing waste flattening probe needle is used.

  Also, a plurality of the measurement / probing waste flattening probe needles are formed adjacent to each other on the probe card, and the electrical measurement is performed by one measurement / probing waste flattening probe needle for each semiconductor chip. After performing a physical inspection, a probing waste flattening step with the adjacent probe needle for measuring and probing waste flattening and the electrical of the semiconductor chip adjacent with the one probe needle for measuring and probing waste flattening. It is characterized by carrying out inspection simultaneously.

  Also, a plurality of the measurement / probing waste flattening probe needles are formed adjacent to each other on the probe card, and the electrical measurement is performed by one measurement / probing waste flattening probe needle for each semiconductor chip. After the physical inspection, the electrical inspection is performed again with the adjacent probe needle for measuring and probing waste flattening and the semiconductor chip adjacent to the adjacent probe needle for measuring and probing waste flattening It is characterized by conducting an electrical inspection.

Furthermore, the semiconductor device of the present invention is manufactured by the method for manufacturing a semiconductor device.
As described above, it is possible to easily improve the adhesion strength of wire bonding and bump connection, reduce connection failures, and improve reliability.

  As described above, before forming the wire bonding ball or bump, the probe needle slides in a state in which the sliding direction is opposite to that of the measurement probe needle and the probe trace end point of the measurement probe needle is passed. In this way, it is possible to flatten the probing waste generated in the probe inspection process by contacting the probe needle for flattening the probing waste, and as a result, the adhesion strength of the wire bonding ball or bump can be improved easily. It is possible to reduce connection failures and improve reliability.

Hereinafter, as a premise for explaining an embodiment of the present invention, definitions of terms used in the present invention will be described with reference to FIGS.
FIG. 1 is a plan view showing a configuration of a semiconductor wafer, FIG. 2 is a diagram for explaining a state in which a semiconductor wafer is inspected using a probe card in a probe inspection process, and FIG. 3 is a diagram for explaining probe marks and probing debris.

  FIG. 1A shows a general semiconductor wafer. A plurality of semiconductor chips 12 are formed on the semiconductor wafer 11, and are diced along a scribe line 13, and a semiconductor device is manufactured through an assembly process. FIG. 1B is an enlarged view of a portion A in FIG. Thus, the electrode pads 14 for external connection exist on the outer peripheral portion of each semiconductor chip 12. In the present invention, an input / output terminal for exchanging signals and power inside the chip and signals and power outside the chip is defined as an “electrode pad”. Further, the region 15 inside the electrode pad 14 as viewed from the scribe line 13 side is defined as a “chip internal region”.

  FIG. 2 shows a so-called probe inspection process in which the semiconductor chip 12 formed on the semiconductor wafer 11 is inspected in the wafer state. The semiconductor wafer 11 is placed on the chuck table 16 and the probe needle 5 formed on the probe card 4 is brought into contact with the electrode pad 14 in the semiconductor chip 12 for electrical inspection. In general, an automatic control device (not shown) called a prober is used, and the probe needle 5 and the electrode pad 14 are connected by pulling up the chuck table 16 in the direction of the arrow. Also, electrical inspection is performed by inputting / outputting signals and power from / to a semiconductor chip 12 through a probe card 4, probe needle 5 and electrode pad 14 from an inspection device (not shown) generally called a tester. Is going. The probe card 4 and the probe needle 5 are integrated, and the state in which the probe needle 5 is attached to the probe card 4 is expressed as “the probe needle is provided in the probe card”. In order to classify the role of the probe needle here, the probe needle used for electrical inspection is the “probe for measurement”, and the probe needle used for flattening probing waste is not used for the electrical inspection. The probe needle used for the flattening of the waste flattening probe and the electrical inspection as well as the flattening of the probing waste is defined as the “probe for measuring and probing waste flattening”. The probe needle for measuring and probing waste flattening may or may not realize electrical inspection and flattening of probing waste at the same contact timing. In other words, a probe needle that plays the role of electrical inspection at the contact timing of the same probe needle and of flattening of the probing dust at another contact timing is also defined as “probe for measuring and probing dust flattening”. Also, in order to distinguish between probe needles with probe cards, probe cards with only measurement probe needles are “measurement probe cards”, and probe cards with only probe needles for probing dust flattening are “probing”. "Probe card for waste flattening", a probe card equipped with both a probe needle for measurement and a probe needle for flattening waste probing, or a probe card with a probe needle for measurement and probing waste flattening "for measurement and probing waste flattening" It is defined as “probe card”. By this definition, “Measurement probe card” can be used only for probe inspection process, and “Probing waste flattening probe card” can be used only for probing waste flattening process, whereas “Measurement and probing waste flattening” The “probe card” can be realized by a single probe card for both the probe inspection process and the probing waste flattening process.

  FIG. 3A shows a state where the probe needle contacts the electrode pad. As described above, when the chuck table 16 of FIG. 2 is pulled upward, the probe needle 5 and the electrode pad 14 come into contact with each other. When the chuck table 16 is further lifted, the probe needle 5 slides in the direction of the arrow and scrapes the electrode pad 14. While being contacted. FIG. 3B shows the state of the electrode pad immediately after the probe inspection process. As described above, the electrode pad 14 is scraped off by the probe needle 5. Here, a scar removed by the probe needle 5 when the electrode pad 14 is in contact is defined as a “probe mark”. Since the probe trace 2 is different from the original surface state of the electrode pad 14 as shown in FIG. 3B, it can be easily identified by observation with a metal microscope or cross-sectional analysis. Further, as shown in FIG. 3B, the probe trace 2 has a shape that spreads and deepens in the direction of sliding from the approach direction of the probe needle 5, so that the probe sliding direction is determined from the probe trace 2. It is also possible. Most of the electrode pad 14 scraped by the probe needle 5 is deposited on the end point of the probe mark 2. Here, this deposit is defined as “probing waste”. As shown in FIG. 3B, the probing scraps 3 may rise by 1 μm or more from the position of the surface of the electrode pad 14, so that the bonding between the wire bonding ball or bump and the electrode pad 14 is inhibited as described above.

Embodiments of a method for manufacturing a semiconductor device according to the present invention will be described below with reference to the drawings.
(First embodiment)
FIG. 4 is a diagram showing a process of contacting the measurement probe needle with the electrode pad in the first embodiment, and FIG. 5 is a diagram showing a process of flattening the electrode pad with the probe needle for probing dust flattening in the first embodiment. FIG. 6 is a view showing a state in which wire bonding balls are formed on the electrode pads in the first embodiment.

  As shown in FIG. 4A, first, in the probe inspection process, the measurement probe needle 5a is brought into contact with the electrode pad 14, and an electrical inspection is performed. After this step, as shown in FIG. 4 (b), the probe pad 2a and the probing waste 3a exist on the electrode pad 14 as described above. Next, as shown in FIG. 5 (a), the probe needle 5b for probing dust flattening is contacted from the opposite direction to the probe needle 5a for measurement, which is contacted at the time of the probe inspection process. In this case, the probe needle 5b slides in the direction indicated by the arrow. At this time, as shown in FIG. 5B, the probe needle 5b for probing dust flattening is slidably contacted while passing through the end point of the probe mark 2a after the inspection process. That is, the probe trace 2a after the inspection process and the probe trace 2b after the probing dust flattening are in a positional relationship where they overlap each other. By this probing waste flattening step, the probing waste 3a deposited after the inspection step is scraped off by the probing waste flattening probe needle 5b. Further, the probing waste 3b is newly generated by the probe needle 5b for probing waste flattening, but as shown in FIG. 5B, it is deposited so as to be embedded in the shaved portion of the probe trace 2a after the inspection process. Compared with the state before the probing waste flattening step shown in FIG. 4B, the state after the probing waste flattening step shown in FIG. Yes. FIG. 6 is a diagram showing a state where the wire bonding balls 17 are formed after the probing waste flattening step. Compared with FIG. 16 (c) showing the conventional problem, FIG. 6 is not obstructed by pushing up the wire bonding balls 17 by the probing scraps 3, so that the adhesion strength is enhanced as compared with the conventional case. In this embodiment, the wire bonding method is taken as an example, but the same applies to the connection method using bumps.

  FIG. 7 is a diagram showing a contact state of the probe needle for measurement with respect to the semiconductor chip in the first embodiment, and FIG. FIG. 9 is a diagram showing a state of contact of the probe needle for probing dust flattening to the upper side of the semiconductor chip in the first embodiment, and FIG. 10 is a diagram of the left side of the semiconductor chip in the first embodiment. FIG. 11 is a diagram illustrating a contact state of a probe needle for probing dust flattening with respect to a side, and FIG. 11 is a diagram illustrating a contact state of the probe needle for probing dust flattening to a lower side of the semiconductor chip according to the first embodiment. The probe card contacts the semiconductor chip and the probe card is seen through the probe card. Is a diagram showing a state viewed al.

  As shown in FIG. 7A, the measurement probe card 4 a includes the measurement probe needle 5 a via the probe needle support portion 18. When the probe inspection process is performed using the measurement probe card 4a, the probe needle 5a slides in the direction from the scribe line indicated by the arrow in FIG. Next, as shown in FIG. 8A, a probe card 4b for probing waste flattening provided with a probe needle 5b for probing waste flattening is prepared. As shown in FIG. 8A, when the probe card 4b for probing waste flattening is used only on the right side of the semiconductor chip 12, only the right side of the semiconductor chip 12 is shown as indicated by the arrow in FIG. The probe needle 5b for probing dust flattening is contacted while sliding in the direction of the scribe line from the inside of the chip. In this figure, the arrow indicating the sliding direction of the probe for measurement and the arrow indicating the sliding direction of the probe needle for probing waste flattening are intentionally shown so that they are easy to understand visually. As shown in FIGS. 4 to 6, the sliding directions are opposite to each other and the probe marks are contacted in an overlapping state. The same applies to the description of the following embodiments. Next, as shown in FIG. 9A, the probe card 4b for probing waste flattening is rotated by 90 ° C. to contact the probe needle 5b for probing waste flattening. In this case, as shown by the arrow in FIG. 9B, the probe needle 5b for probing dust flattening is brought into contact with only the upper side of the semiconductor chip 12 sliding from the inside of the chip toward the scribe line. Further, as shown in FIG. 10 (a), the probe card 4b for probing waste flattening is further rotated by 90 ° C. to make contact with the probe needle 5b for probing waste flattening. In this case, as shown by an arrow in FIG. 10B, the probe needle 5b for probing dust flattening is brought into contact with only the left side of the semiconductor chip 12 sliding from the inside of the chip toward the scribe line. Similarly, as shown in FIG. 11 (a), the probe card 4b for probing dust flattening is further rotated by 90 ° C. to make contact with the probe needle 5b for probing waste flattening. In this case, as shown by the arrow in FIG. 11B, the probe needle 5b for probing dust flattening is brought into contact with only the left side of the semiconductor chip 12 sliding from the inside of the chip toward the scribe line. As shown in FIG. 5B, the probing waste is flattened by the electrode pad 14 on each side of the semiconductor chip 12 through the above steps.

  As described above, after making contact with the measurement probe needle, the probe needle for probing waste flattening is in the direction opposite to the direction of travel of the probe needle for measurement, and the probe marks overlap. By making contact, it is possible to flatten the probing waste generated in the probe inspection process. As a result, the adhesion strength of the wire bonding balls or bumps can be improved to easily reduce connection failures and reliability. It is possible to improve. Furthermore, in this embodiment, since it can be realized by using a probe card, a probe needle, and a prober that are conventionally used, there is an advantage that a special dedicated device is unnecessary and the facility cost can be reduced.

In the present embodiment, the case where there are electrode pads on the four sides of the outer periphery of the semiconductor chip and all the pads are inspected has been described. However, even when the arrangement and number of electrode pads are different, In the case where the probe needle holder can be realized in the sliding direction opposite to that at the time of inspection, the same effect can be obtained. In this embodiment, one type of probe card for leveling probing waste is realized, but may be realized by using two or more types of probe card for leveling probing waste. In the present embodiment, the probe card for flattening the probing waste is rotated four times, but the probe card for leveling the probing waste may be realized in three or less times. A probe card for flattening probing waste that can be used may be used. In addition, although the present example realized the probe inspection process and the flattening of the probing dust on all the electrode pads in the semiconductor chip, the effect of preventing the yield reduction due to the bonding failure can be obtained only by realizing only a part of the electrode pads. It is done.
(Modification of the first embodiment)
FIG. 12 is a diagram for explaining an inspection process using a measurement / probing waste flattening probe card, and FIG. 13 is a view for explaining a probe waste flattening process using a measurement / probing waste flattening probe card.

  In this modification, as shown in FIG. 12A, a measuring / probing waste flattening probe card 4c provided with a measuring probe needle 5a and a probing waste flattening probe needle 5b via a probe needle support 18 is provided. An example in which the electrode pads on the left and right sides are inspected is shown using FIG. First, FIG. 12B is a diagram in which a probe inspection process is performed using the measurement / probing waste flattening probe card 4c of FIG. The measurement probe needle 5a is in contact with the semiconductor chip 2 in the center, and an electrical inspection is performed. The sliding direction of the probe needle is as shown by the arrow. Next, as shown in FIG. 13A, when the same contact is made by shifting the chuck table to the left by one chip, the measurement probe needle 5a is formed on the right semiconductor chip 2 as shown in FIG. 13B. Are contacted and an electrical inspection is performed. Further, at the same timing, the probe needle 5b for probing dust flattening is contacted with the semiconductor chip 2 in the center in the direction opposite to the probe direction. As a result, as shown in FIG. 5B (d), the semiconductor chip 2 in the central portion can be flattened as shown in FIG. Here, when measuring the leftmost semiconductor chip 2 on the semiconductor wafer, the probe needle 5b for probing dust flattening protrudes from the semiconductor chip outside the effective shot or the semiconductor wafer. 5b does not function, and there is no particular problem. Similarly, when measuring the rightmost semiconductor chip 2 on the semiconductor wafer, the measurement probe needle 5a protrudes from the semiconductor chip 2 outside the effective shot or the semiconductor wafer, but in any case, the measurement probe needle 5a does not function. There is no particular problem. Actually, a large number of semiconductor chips 12 exist on the semiconductor wafer 11 as shown in FIG. 1A, but by repeating the above-described flow, the probing waste 3 of all the semiconductor chips 2 can be flattened.

  As described above, the measurement / probing waste flattening probe card is used to inspect with one measurement / probing waste flattening probe card by performing the inspection by shifting the semiconductor wafer on every semiconductor chip. Since the flattening of the probing waste can be performed sequentially, the probe card manufacturing cost can be reduced while realizing the flattening of the probing waste generated in the probe inspection process. Furthermore, the prober can be realized with a single product file, which not only simplifies the operation procedure and operation, but also requires time for probe card replacement, product file, alignment, etc. newly generated by the probing waste flattening process. Can be greatly reduced.

  FIG. 14 is a diagram for explaining the first inspection process by the measurement / probing waste flattening probe card, and FIG. 15 is a diagram for explaining the second inspection process by the measurement / probing waste flattening probe card.

  12 to 13 is different from the modification of FIG. 12 to FIG. 14 in that the measurement / probing waste flattening probe card 4c is provided with the measurement / probing waste flattening probe needle 5c as shown in FIG. 14 (a). It is. In the case of FIG. 14B, both the left semiconductor chip and the central semiconductor chip are contacted with the probe needle 5c for measuring and probing waste flattening, and the probe inspection process is performed. Next, as shown in FIG. 15A, when the same contact is made by shifting the chuck table by one chip to the left, as shown in FIG. The probe needle 5c for probing waste flattening is contacted and electrical inspection is performed. Further, at the same timing, the probe needle 5c for probing dust flattening is contacted with the semiconductor chip 2 in the central part, so that the probing scraps are flattened in the semiconductor chip 2 in the central part and at the same time an electrical inspection is performed. The

  As described above, the probe for measuring and probing debris flattening with the probe needle for measuring and probing debris flattening is performed by shifting the inspection on the semiconductor wafer for each semiconductor chip. The probe needle for measuring and probing scraps flattening in the opposite direction of the sliding direction of the needle will be contacted once each, reducing the probe card manufacturing cost and flattening the probing scrap generated in the probe inspection process. realizable. In addition, each semiconductor chip can be inspected twice in total. For example, for semiconductor chips that require two or more types of inspections such as logic and memory, the probing waste is flattened in the same time as the conventional inspection time. Can be realized. In addition, even when there is only one type of inspection, by performing the same inspection twice, it is possible to remedy a failure due to a contact failure, and it is possible to improve the yield at the time of shipment.

  In the above modification example, the semiconductor chip in which the electrode pads are formed on the left and right sides has been described as an example. However, the measuring and probing waste having the probe needles for measuring and probing waste flattening provided on four sides or any side is described. By using a flattening probe card, it is possible to realize a semiconductor chip on which four sides or arbitrary side electrode pads are formed.

  The present invention improves the adhesion strength of wire bonding and bump connection to reduce connection failure and improve reliability. After conducting electrical inspection by contacting a probe needle to an electrode pad, the above-mentioned electrical This is useful for a semiconductor device manufacturing method and a semiconductor device in which wire bonding balls or bumps are formed on pads.

Plan view showing the structure of a semiconductor wafer The figure explaining the state which test | inspects a semiconductor wafer using the probe card in a probe test process Diagram explaining probe marks and probing waste The figure which shows the process of contacting the probe needle for a measurement in 1st Embodiment to an electrode pad The figure which shows the planarization process of the electrode pad by the probe needle for probing waste planarization in 1st Embodiment. The figure which shows the state which formed the ball for wire bonding in the electrode pad in 1st Embodiment The figure which shows the mode of the contact of the probe needle for a measurement with respect to the semiconductor chip in 1st Embodiment The figure which shows the mode of the contact of the probe needle for probing waste planarization with respect to the right side of the semiconductor chip in 1st Embodiment. The figure which shows the mode of the contact of the probe needle for probing waste flattening with respect to the upper side of the semiconductor chip in 1st Embodiment. The figure which shows the mode of the contact of the probe needle for probing waste flattening with respect to the left side of the semiconductor chip in 1st Embodiment The figure which shows the mode of the contact of the probe needle | hook for probing waste flattening with respect to the lower side of the semiconductor chip in 1st Embodiment. The figure explaining the inspection process by the probe card for measurement and probing waste flattening The figure explaining the probe waste flattening process by the probe card for measurement and probing waste flattening The figure explaining the 1st inspection process by the probe card for measurement and probing waste flattening The figure explaining the 2nd inspection process by the probe card for measurement and probing waste flattening Schematic showing a conventional method of manufacturing a semiconductor device

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 Semiconductor wafer 12 Semiconductor chip 13 Scribe line 14 Electrode pad 15 Area | region 16 Chuck table 17 Ball for ball bonding 18 Probe needle support part 2 Probe trace 2a Probe trace after a probe test process 2b Probe trace after a probing waste flattening process 3 Probing Scrap 3a Probing Scrap 3b Probing Scrap 4 Probe Card 4a Measuring Probe Card 4b Probing Scrap Flattening Probe Card 4c Measuring / Probing Scrap Flattening Probe Card 5 Probe Needle 5a Measuring Probe Needle 5b Probing Scrap Flattening Probe Needle 5c Probe needle for measuring and probing waste flattening

Claims (7)

In the wafer state, after performing an electrical inspection by contacting a measurement probe needle to the electrode pad formed on the semiconductor chip, it comprises a step of forming a wire bonding ball or bump on the electrode pad,
Before the step of forming the wire bonding ball or bump,
A probing dust flattening step of contacting the probe needle for probing dust flattening so that the probe needle slides in a state in which the sliding direction is diametrically opposite to that of the measurement probe needle and passes through the probe trace end point of the measurement probe needle. A method for manufacturing a semiconductor device, comprising:   The method of manufacturing a semiconductor device according to claim 1, wherein a probe card including both the measurement probe needle and the probing dust flattening probe needle is used.   The measurement probe needle and the probe needle for probing dust flattening are formed adjacent to the probe card, and the semiconductor chip is adjacent after the electrical inspection is performed with the measurement probe needle. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the probing waste flattening step and the electrical inspection of the semiconductor chip adjacent to each other with the measurement probe needle are performed simultaneously with the probing waste flattening probe needle. .   2. The semiconductor device according to claim 1, wherein a probe card provided with a measuring and probing waste flattening probe needle having both functions of the measurement probe needle and the probing waste flattening probe needle is used. Manufacturing method.   A plurality of the measuring and probing waste flattening probe needles are formed adjacent to each other on the probe card, and the electrical inspection is performed by one measuring and probing waste flattening probe needle for each semiconductor chip. After performing the probing debris flattening step with the adjacent measuring and probing debris flattening probe needle and the electrical inspection of the adjacent semiconductor chip with the one measuring and probing debris flattening probe needle. 5. The method of manufacturing a semiconductor device according to claim 4, wherein the method is performed simultaneously.   A plurality of the measuring and probing waste flattening probe needles are formed adjacent to each other on the probe card, and the electrical inspection is performed by one measuring and probing waste flattening probe needle for each semiconductor chip. Then, the electrical inspection is performed again with the adjacent probe needle for flattening measurement and probing waste, and the electrical of the semiconductor chip adjacent to the probe needle for flattening waste with one measurement and probing is performed. The method of manufacturing a semiconductor device according to claim 4, wherein an inspection is performed.   A semiconductor device manufactured by the method for manufacturing a semiconductor device according to claim 1.

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