CN112117268A - Chip integrated module - Google Patents
Chip integrated module Download PDFInfo
- Publication number
- CN112117268A CN112117268A CN202011022295.4A CN202011022295A CN112117268A CN 112117268 A CN112117268 A CN 112117268A CN 202011022295 A CN202011022295 A CN 202011022295A CN 112117268 A CN112117268 A CN 112117268A
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- bonding pad
- integrated module
- bonding
- pad
- chip integrated
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0501—Shape
- H01L2224/05011—Shape comprising apertures or cavities
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0501—Shape
- H01L2224/05016—Shape in side view
- H01L2224/05017—Shape in side view comprising protrusions or indentations
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48471—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
Abstract
The invention discloses a chip integrated module which comprises an amplifying tube core, a switch tube core, a substrate and a bonding lead, wherein the amplifying tube core, the switch tube core, the substrate and the bonding lead are sequentially stacked from top to bottom, the switch tube core and the substrate respectively comprise an upper bonding pad and a lower bonding pad, the upper bonding pad and the lower bonding pad are respectively in one-to-one correspondence, grooves are respectively arranged on the upper bonding pad and the lower bonding pad, and two ends of the bonding lead are welded in the grooves. According to the invention, the connection strength of the end part of the bonding lead is improved by an embedded welding mode, and meanwhile, the auxiliary groove body is arranged, so that the auxiliary embedding section close to the main embedding section is supported by the left side wall and the right side wall of the auxiliary groove body when the auxiliary embedding section is subjected to an acting force in a direction parallel to the end face of the substrate, and the connection stability of the bonding lead is improved.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to a chip integrated module.
Background
The advanced electronic system in the future has the characteristics of multifunction, self-adaption, miniaturization and the like, the technical implementation approach of the multifunctional integrated electronic system is being greatly explored at home and abroad at present, and the miniaturization of a chip is further required to be realized on the basis of the existing digital channel software definition technology. At present, the existing chip packaging technology usually adopts a plane packaging mode, and the area of a chip is greatly occupied. For this reason, a stacked package type chip has been derived, but the stacked package requires bonding wires to be connected between the substrate of the re-staggered layer and the upper end surface of the die, and the existing bonding wires have low connection strength and are easily broken, especially when a force parallel to the end surface of the substrate is applied.
Disclosure of Invention
The invention aims to provide a chip integrated module with high integration and stable connection.
In order to solve the technical problems, the invention adopts the following technical scheme: a chip integrated module comprises an amplifying tube core, a switch tube core, a substrate and a bonding lead, wherein the amplifying tube core, the switch tube core, the substrate and the bonding lead are sequentially stacked from top to bottom, the switch tube core and the substrate respectively comprise an upper bonding pad and a lower bonding pad, the upper bonding pad and the lower bonding pad are in one-to-one correspondence respectively, grooves are formed in the upper bonding pad and the lower bonding pad respectively, and two ends of the bonding lead are welded in the grooves.
Another kind of optimization scheme, the recess is including being hemispherical main cell body and being rectangular form vice cell body, the tip position of bonding lead weld in the main cell body, this part is the main section of burying, bonding lead with the main adjacent part of section of burying weld in the vice cell body, this part is vice section of burying.
In another preferred embodiment, the projections of the grooves on the upper bonding pad and the corresponding sub-grooves of the grooves on the lower bonding pad on the substrate extend in opposite directions.
In another optimized scheme, the auxiliary groove body extends along the radial direction of the main groove body.
In another optimized scheme, the depth of the auxiliary groove body decreases progressively along the direction of outward divergence of the center of the main groove body.
In another preferred embodiment, the upper bonding pad and the lower bonding pad are made of metal.
In another preferred embodiment, the main bodies of the upper bonding pad and the lower bonding pad are made of aluminum, copper or an alloy of the aluminum and the copper.
In another preferred embodiment, the bonding wire is made of any one of gold, silver, copper, titanium, nickel and aluminum, or an alloy of any two or more of the above metals.
In another optimized scheme, the bonding wire is made of beryllium and any one of gold, silver, copper, titanium, nickel and aluminum.
In another preferred embodiment, the bonding wires are connected to the grooves on the upper bonding pad and the grooves on the lower bonding pad by ultrasonic welding or thermocompression bonding.
The invention has the beneficial effects that: according to the invention, the connection strength of the end part of the bonding lead is improved by an embedded welding mode, and meanwhile, the auxiliary groove body is arranged, so that the auxiliary embedding section close to the main embedding section is supported by the left side wall and the right side wall of the auxiliary groove body when the auxiliary embedding section is subjected to an acting force in a direction parallel to the end face of the substrate, and the connection stability of the bonding lead is improved.
Drawings
Fig. 1 is a front view of a chip integrated module (only one bonding wire is shown);
FIG. 2 is a top view of a chip integrated module;
FIG. 3 is a schematic diagram of a structure in which a set of upper and lower pads are connected;
FIG. 4 is a top view of a lower bond pad;
FIG. 5 is a cross-sectional view A-A of FIG. 4;
FIG. 6 is a schematic view of a bonding wire and lower pad connection structure;
fig. 7 is a top view of the upper bonding pad.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, embodiments accompanying the present application are described in detail below with reference to the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. This application is capable of embodiments in many different forms than those described herein and that modifications may be made by one skilled in the art without departing from the spirit and scope of the application and it is therefore not intended to be limited to the specific embodiments disclosed below.
In the description of the present application, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and for simplicity in description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and are therefore not to be considered limiting of the present application.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present application, "plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
In this application, unless expressly stated or limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can include, for example, fixed connections, removable connections, or integral parts; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through intervening media. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature. It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "upper," "lower," "left," "right," and the like as used herein are for illustrative purposes only and do not denote a unique embodiment.
As shown in fig. 1, the chip integrated module includes an amplifier die 1, a switch die 2, a substrate 3, and bonding wires 4 stacked in this order from top to bottom.
The switch die 2 and the substrate 3 respectively comprise an upper pad 5 and a lower pad 6, the upper pad 5 and the lower pad 6 respectively correspond to each other one by one, the upper pad 5 and the lower pad 6 are made of sheet metal, and preferably, the upper pad 5 and the lower pad 6 are made of aluminum (Al) or copper (Cu) or an alloy thereof. The upper pad 5 and the lower pad 6 may be formed on the surfaces of the switch die 2 and the substrate 3 by plating, sputtering, Chemical Vapor Deposition (CVD), and the like, and the specific formation thereof is not described herein again.
The invention has the beneficial effects that: the main embedded section is connected in the main groove body in a welding mode, the connection strength of the end portion of the bonding lead 4 can be improved, when the auxiliary embedded section receives acting force parallel to the end face direction of the substrate 3, the left side wall and the right side wall of the auxiliary groove body are supported, and the connection stability of the bonding lead 4 is improved.
The above embodiments are merely illustrative of the technical ideas and features of the present invention, and the purpose thereof is to enable those skilled in the art to understand the contents of the present invention and implement the present invention, and not to limit the protection scope of the present invention. All equivalent changes or modifications made according to the spirit of the present invention should be covered within the protection scope of the present invention.
Claims (10)
1. The utility model provides a chip integrated module, its includes from last to stacking up amplifier die, switch die, base plate and the bonding lead who sets up down in proper order, switch die and base plate include upper portion pad and lower part pad respectively, upper portion pad and lower part pad one-to-one respectively, its characterized in that: grooves are respectively formed in the upper bonding pad and the lower bonding pad, and two ends of the bonding lead are welded in the grooves.
2. The chip integrated module according to claim 1, wherein: the groove comprises a main groove body which is hemispherical and an auxiliary groove body which is long-strip-shaped, the end position of the bonding lead is welded in the main groove body, the main part is a main embedded section, and the bonding lead and the part adjacent to the main embedded section are welded in the auxiliary groove body.
3. The chip integrated module according to claim 2, wherein: the projection of the groove on the upper bonding pad and the projection of the auxiliary groove body of the groove on the lower bonding pad corresponding to the groove on the upper bonding pad on the substrate extend oppositely.
4. The chip integrated module according to claim 2, wherein: the auxiliary groove body extends along the radial direction of the main groove body.
5. The chip integrated module according to claim 2, wherein: the depth of the auxiliary groove body decreases progressively along the direction of the outward divergence of the center of the main groove body.
6. The chip integrated module according to claim 1, wherein: the upper bonding pad and the lower bonding pad are made of metal.
7. The chip integrated module according to claim 6, wherein: the main bodies of the upper bonding pad and the lower bonding pad are made of aluminum, copper or an alloy of the aluminum and the copper.
8. The chip integrated module according to claim 1, wherein: the bonding wire is made of any one of gold, silver, copper, titanium, nickel and aluminum or an alloy of any two or more of the metals.
9. The chip integrated module according to claim 1, wherein: the bonding lead is made of beryllium alloy and any one of gold, silver, copper, titanium, nickel and aluminum.
10. The chip integrated module according to claim 9, wherein: and the bonding lead is connected to the groove of the upper bonding pad and the groove on the lower bonding pad by ultrasonic welding or hot pressing.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011022295.4A CN112117268B (en) | 2020-09-25 | 2020-09-25 | Chip integrated module |
| PCT/CN2021/089878 WO2022062387A1 (en) | 2020-09-25 | 2021-04-26 | Chip integrated module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011022295.4A CN112117268B (en) | 2020-09-25 | 2020-09-25 | Chip integrated module |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112117268A true CN112117268A (en) | 2020-12-22 |
| CN112117268B CN112117268B (en) | 2023-02-10 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011022295.4A Active CN112117268B (en) | 2020-09-25 | 2020-09-25 | Chip integrated module |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN112117268B (en) |
| WO (1) | WO2022062387A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022062387A1 (en) * | 2020-09-25 | 2022-03-31 | 中科芯(苏州)微电子科技有限公司 | Chip integrated module |
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| JPH10189637A (en) * | 1996-12-25 | 1998-07-21 | Hitachi Ltd | Semiconductor device |
| JPH11260855A (en) * | 1998-03-11 | 1999-09-24 | Ricoh Co Ltd | Semiconductor device |
| FR2790141A1 (en) * | 1999-02-22 | 2000-08-25 | St Microelectronics Sa | Integrated circuit used for chip cards and smart cards comprises electronic components integrated on silicon chip and connectors providing metal wire welding areas |
| US20020070450A1 (en) * | 2000-12-07 | 2002-06-13 | Mcknight Samuel | Bond pad structure for integrated circuits |
| US6478212B1 (en) * | 2001-01-16 | 2002-11-12 | International Business Machines Corporation | Bond pad structure and method for reduced downward force wirebonding |
| US20050073056A1 (en) * | 2003-10-07 | 2005-04-07 | Renesas Technology Corp. | Semiconductor device with electrode pad having probe mark |
| US20060175711A1 (en) * | 2005-02-08 | 2006-08-10 | Hannstar Display Corporation | Structure and method for bonding an IC chip |
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| JP2009289767A (en) * | 2008-05-27 | 2009-12-10 | Panasonic Corp | Manufacturing method of semiconductor device, and the semiconductor device |
| JP2010192493A (en) * | 2009-02-16 | 2010-09-02 | Sony Corp | Semiconductor device and method of manufacturing thereof |
| JP2012195328A (en) * | 2011-03-15 | 2012-10-11 | Panasonic Corp | Semiconductor device and manufacturing method of the same |
| US20160086921A1 (en) * | 2014-09-19 | 2016-03-24 | Samsung Electronics Co., Ltd. | Semiconductor package having cascaded chip stack |
| CN207637784U (en) * | 2017-08-09 | 2018-07-20 | 江门市迪司利光电股份有限公司 | A kind of bonding wire fixed engagement semiconductor package |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105591010B (en) * | 2014-10-24 | 2018-12-21 | 比亚迪股份有限公司 | The packaging method of LED chip, LED support and LED chip |
| CN206789540U (en) * | 2017-02-23 | 2017-12-22 | 江苏盐芯微电子有限公司 | The semiconductor devices of SOT encapsulating structures |
| CN112117268B (en) * | 2020-09-25 | 2023-02-10 | 中科芯(苏州)微电子科技有限公司 | Chip integrated module |
-
2020
- 2020-09-25 CN CN202011022295.4A patent/CN112117268B/en active Active
-
2021
- 2021-04-26 WO PCT/CN2021/089878 patent/WO2022062387A1/en active Application Filing
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10189637A (en) * | 1996-12-25 | 1998-07-21 | Hitachi Ltd | Semiconductor device |
| JPH11260855A (en) * | 1998-03-11 | 1999-09-24 | Ricoh Co Ltd | Semiconductor device |
| FR2790141A1 (en) * | 1999-02-22 | 2000-08-25 | St Microelectronics Sa | Integrated circuit used for chip cards and smart cards comprises electronic components integrated on silicon chip and connectors providing metal wire welding areas |
| US20020070450A1 (en) * | 2000-12-07 | 2002-06-13 | Mcknight Samuel | Bond pad structure for integrated circuits |
| US6478212B1 (en) * | 2001-01-16 | 2002-11-12 | International Business Machines Corporation | Bond pad structure and method for reduced downward force wirebonding |
| US20050073056A1 (en) * | 2003-10-07 | 2005-04-07 | Renesas Technology Corp. | Semiconductor device with electrode pad having probe mark |
| US20060175711A1 (en) * | 2005-02-08 | 2006-08-10 | Hannstar Display Corporation | Structure and method for bonding an IC chip |
| US20090243118A1 (en) * | 2008-03-31 | 2009-10-01 | Renesas Technology Corp. | Semiconductor device and manufacturing method of the same |
| JP2009289767A (en) * | 2008-05-27 | 2009-12-10 | Panasonic Corp | Manufacturing method of semiconductor device, and the semiconductor device |
| JP2010192493A (en) * | 2009-02-16 | 2010-09-02 | Sony Corp | Semiconductor device and method of manufacturing thereof |
| JP2012195328A (en) * | 2011-03-15 | 2012-10-11 | Panasonic Corp | Semiconductor device and manufacturing method of the same |
| US20160086921A1 (en) * | 2014-09-19 | 2016-03-24 | Samsung Electronics Co., Ltd. | Semiconductor package having cascaded chip stack |
| CN207637784U (en) * | 2017-08-09 | 2018-07-20 | 江门市迪司利光电股份有限公司 | A kind of bonding wire fixed engagement semiconductor package |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022062387A1 (en) * | 2020-09-25 | 2022-03-31 | 中科芯(苏州)微电子科技有限公司 | Chip integrated module |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2022062387A1 (en) | 2022-03-31 |
| CN112117268B (en) | 2023-02-10 |
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