CN211295085U

CN211295085U - Multi-chip series connection packaging structure

Info

Publication number: CN211295085U
Application number: CN202020297952.5U
Authority: CN
Inventors: 王海滨; 孙林弟; 林旭帆; 金燕
Original assignee: Zhejiang Mingde Microelectronics Co ltd
Current assignee: Zhejiang Mingde Microelectronics Co ltd
Priority date: 2020-03-11
Filing date: 2020-03-11
Publication date: 2020-08-18
Anticipated expiration: 2030-03-11

Abstract

The utility model discloses a multi-chip series packaging structure, which comprises a chip, a packaging shell and two copper frames, wherein at least two chips are arranged, and the copper frames are positioned outside the packaging shell to form leading-out pins; the parts of the two copper frames in the packaging shell are respectively bent up and down to form an upper frame and a lower frame, the upper frame and the lower frame are arranged in parallel, a plurality of chips are stacked between the upper frame and the lower frame in the same direction of a cathode and an anode, and the adjacent two chips, the upper frame and the chips and the lower frame and the chips are electrically connected. The structure of adoption stack formula is integrated a plurality of chips in vertical space, can the effectual area occupied that reduces whole device.

Description

Multi-chip series connection packaging structure

Technical Field

The utility model relates to a technical field of chip package, in particular to multi-chip series connection packaging structure.

Background

In electronic circuits, series and parallel connections are common connection methods, wherein due to the popularization of integrated circuit boards, the integration degree of the existing circuits is higher and higher, and therefore, in order to realize higher integration degree, various integrated chips are adopted. However, in some cases, the parameter change of the whole device is realized by using the serial connection of a plurality of chips, for example, in the semiconductor field, the serial connection of a plurality of chips can be used for realizing the adjustment of the volt-ampere characteristic curve and also can be used for adjusting the voltage. Based on this, the chip can be further integrated, thereby reducing the volume thereof.

SUMMERY OF THE UTILITY MODEL

Not enough to prior art exists, the utility model aims at providing a multichip series connection packaging structure has and further integrates a plurality of chips, has the effect of reducing whole device overall dimension.

The above technical purpose of the present invention can be achieved by the following technical solutions:

a multi-chip series packaging structure comprises chips, a packaging shell and two copper frames, wherein at least two chips are arranged, and the parts of the copper frames, which are positioned outside the packaging shell, form leading-out pins;

the parts of the two copper frames in the packaging shell are respectively bent up and down to form an upper frame and a lower frame, the upper frame and the lower frame are arranged in parallel, a plurality of chips are stacked between the upper frame and the lower frame in the same direction of a cathode and an anode, and the adjacent two chips, the upper frame and the chips and the lower frame and the chips are electrically connected.

So set up, adopt the structure of stack formula, with a plurality of chips integration in vertical space, area occupied that can effectual reduction whole device.

More preferably: and the adjacent two chips, the upper frame and the chip, and the lower frame and the chip are connected through soldering tin and soldering tin.

So set up, welded connection earlier during production, then carry out the encapsulating encapsulation and form the encapsulation casing, the production of being convenient for effectively improves production efficiency.

More preferably: the leading-out pin is a gull wing pin, a flat pin or a plug-in pin.

Due to the design of the gull-wing pin, the lead-out pin is led out from the middle position of the side surface of the packaging shell, and the structure strength is better; and the design of the flat leg and the plug-in leg can be used for some specific occasions.

Not enough to prior art exists, the utility model discloses a second purpose provides a multi-chip series connection packaging structure, has and further integrates a plurality of chips, has the effect of reducing whole device overall dimension.

the two copper frames are positioned in the packaging shell to form bonding pads, all the chips are arranged on the same horizontal plane at linear intervals, the two chips positioned at the two ends are respectively electrically connected with the two bonding pads, the adjacent two chips are electrically connected through a connecting sheet, and the cathodes and the anodes of the adjacent two chips are oppositely arranged.

So set up, adopt linear arrangement's bridging formula to connect, the chip is longer relatively, nevertheless does not occupy vertical space, also can reduce the area occupied of whole device.

More preferably: and the bonding pad is connected with the chip and the chip is connected with the connecting sheet through soldering tin and brazing.

More preferably: when the chip is in a double number, the two bonding pads are arranged in a coplanar manner.

More preferably: when the chip is in the singular number, the two bonding pads are arranged in parallel one on top of the other.

To sum up, the utility model discloses following beneficial effect has: the multiple chips are further integrated, and the effect of reducing the whole size of the whole device is achieved.

Drawings

FIG. 1 is an overall outline view of the first embodiment;

FIG. 2 is a schematic view of the internal structure of the first embodiment;

FIG. 3 is a schematic view showing the internal structure of the second embodiment;

FIG. 4 is an overall external view of the third embodiment;

FIG. 5 is an overall external view of the fourth embodiment;

FIG. 6 is a schematic view showing the internal structure of the fourth embodiment;

FIG. 7 is a schematic view showing the internal structure of the fifth embodiment.

In the figure, 100, a package housing; 200. a chip; 300. a copper frame; 310. a lead-out pin; 320. an upper frame; 330. a lower frame; 340. a pad; 400. soldering tin; 500. and (7) connecting the sheets.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings.

Example 1: a multi-chip serial package structure, as shown in fig. 1 and fig. 2, includes a package housing 100, a plurality of chips 200, and two copper frames 300, wherein, in this embodiment, two chips 200 are taken as an example, two chips 200 are both located in the package housing 100, one end of each of the two copper frames 300 is located in the package housing 100 and connected to the chip 200, and the other end thereof extends out of the package housing 100 to form a pin 310.

Referring to fig. 2, the two copper frames 300 are respectively bent upward and downward to form an upper frame 320 and a lower frame 330, the upper frame 320 and the lower frame 330 are disposed in parallel, the upper frame 320 and the lower frame 330 are disposed along the same center line, and the distance between the upper frame 320 and the lower frame 330 is greater than the sum of the thicknesses of the two chips 200.

The two chips 200 are located between the upper frame 320 and the lower frame 330, and the two chips 200 are stacked in the same direction. The two chips 200, the upper frame 320 and the chip 200, and the lower frame 330 and the chip 200 are connected by soldering 400, and after the connection is completed, electrical connections are formed between the two adjacent chips 200, between the upper frame 320 and the chip 200, and between the lower frame 330 and the chip 200.

Referring to fig. 1 and 2, the two leading-out legs 310 are gull-wing legs, that is, the two leading-out legs 310 respectively extend out from the middle of the two side surfaces of the package housing 100, and then bend in the same direction after extending out, so that the leading-out legs 310 form a gull-wing structure.

Example 2: as shown in fig. 3, the difference from embodiment 1 is that both the two lead-out legs 310 are flat legs.

Compared with the design of the comparative example 1, the pin setting of the embodiment is simpler in production and less in process. But is reduced in structural strength of the finished product, welding temperature conduction, and the like.

Example 3: as shown in fig. 4, the difference from embodiment 1 is that both the lead-out pins 310 are plug-in pins.

Compared with the design of embodiment 1, the pin setting of the embodiment is simpler in production and less in process, but has larger limitation in use.

Example 4: a multi-chip serial package structure, as shown in fig. 5 and 6, includes a package housing 100, a plurality of chips 200 and two copper frames 300, wherein the number of the chips 200 is two, and in this embodiment, two chips 200 are taken as an example.

The two chips 200 are both located in the package housing 100, and the two copper frames 300 have one end located in the package housing 100 and connected to the chips 200 and the other end extending out of the package housing 100 to form the lead pins 310.

The two copper frames 300 are located in the package housing 100 to form a bonding pad 340, wherein the two leads 310 are gull-wing pins, the end surface of the bonding pad 340 is located between the upper and lower ends of the leads 310 and near the lower end, and the two bonding pads 340 are coplanar.

All the chips 200 are arranged at linear intervals on the same horizontal plane, two chips 200 at two ends are respectively connected with two bonding pads 340 through soldering tin 400 in a soldering manner, two adjacent chips 200 are electrically connected through a connecting sheet 500, the chips 200 are connected with the connecting sheet 500 through soldering tin 400 in a soldering manner, and the cathodes and the anodes of the two adjacent chips 200 are arranged oppositely.

Example 5: as shown in fig. 7, the difference from embodiment 4 is that the number of the chips 200 is greater than two, and the number is singular, and at this time, the two bonding pads 340 are arranged in parallel one on top of the other, the end surface where one bonding pad 340 is located between the upper end and the lower end of the lead-out pin 310 and is close to the lower end, and the end surface where the other bonding pad 340 is located is higher than the position where the lead-out pin 310 is located.

The embodiments of the present invention are preferred embodiments of the present invention, and the scope of the present invention is not limited by these embodiments, so: all equivalent changes made according to the structure, shape and principle of the invention are covered by the protection scope of the invention.

Claims

1. A multi-chip series packaging structure comprises a chip (200), a packaging shell (100) and two copper frames (300), and is characterized in that: the number of the chips (200) is at least two, and the part of the copper frame (300) outside the packaging shell (100) forms a pin-out (310);

the parts of the two copper frames (300) in the packaging shell (100) are respectively bent up and down to form an upper frame (320) and a lower frame (330), the upper frame (320) and the lower frame (330) are arranged in parallel, a plurality of chips (200) are stacked between the upper frame (320) and the lower frame (330) in the same direction of negative and positive poles, and the adjacent two chips (200), the upper frame (320) and the chips (200) and the lower frame (330) and the chips (200) are electrically connected.

2. The multi-chip series package structure of claim 1, wherein: the two adjacent chips (200), the upper frame (320) and the chip (200), and the lower frame (330) and the chip (200) are connected by soldering tin (400).

3. The multi-chip series package structure of claim 1, wherein: the leading-out pin (310) is a gull wing pin, a flat pin or a plug-in pin.

4. A multi-chip series packaging structure comprises a chip (200), a packaging shell (100) and two copper frames (300), and is characterized in that: the number of the chips (200) is at least two, and the part of the copper frame (300) outside the packaging shell (100) forms a pin-out (310);

the two copper frames (300) are positioned in the packaging shell (100) to form bonding pads (340), all the chips (200) are arranged on the same horizontal plane at linear intervals, the two chips (200) positioned at two ends are respectively electrically connected with the two bonding pads (340), two adjacent chips (200) are electrically connected through a connecting sheet (500), and the cathodes and the anodes of the two adjacent chips (200) are oppositely arranged.

5. The multi-chip series package structure of claim 4, wherein: the bonding pad (340) and the chip (200) and the connecting sheet (500) are connected through soldering tin (400) in a soldering mode.

6. The multi-chip series package structure of claim 4, wherein: the leading-out pin (310) is a gull wing pin, a flat pin or a plug-in pin.

7. The multi-chip series package structure of claim 6, wherein: when the chip (200) is in a double number, the two bonding pads (340) are arranged in a coplanar manner.

8. The multi-chip series package structure of claim 6, wherein: when the chip (200) is singular, the two bonding pads (340) are arranged in parallel one above the other.