CN216354203U - Semiconductor device and chip parallel module - Google Patents

Abstract

The utility model relates to a semiconductor device and a chip parallel module, wherein the chip parallel module comprises a substrate, a first power terminal, a second power terminal and at least two power chips. The substrate is provided with a first end and a second end which are opposite to each other, and a first conducting layer and a second conducting layer which are spaced and arranged along the direction from the first end to the second end are arranged on one side face of the substrate. For any two adjacent power chips, the length of the first bonding wire of the power chip close to the second end is larger than that of the other power chip, namely, the resistance and the inductance of the first bonding wire of the power chip close to the second end are both larger than those of the other power chip, namely, the length of the first bonding wire of the power chip far away from the first end is larger, so that the parasitic parameters of the power chip far away from the first end can be increased, the parasitic parameters from all the power chips to the second end tend to be consistent, and the product performance of the chip parallel module can be improved.

Description

Semiconductor device and chip parallel module

Technical Field

The present invention relates to the field of semiconductor technology, and more particularly, to a semiconductor device and chip parallel module.

Background

In the conventional technology, limited by manufacturing process and cost, a single power chip has small current capacity, and a multi-chip parallel module is often used in high-power application occasions such as electric transmission and new energy. After at least two power chips are connected in parallel to form a chip parallel module, the problem of uneven distribution of parasitic parameters is inevitably encountered. When the parasitic parameters are unevenly distributed, unbalanced current can be generated, so that unequal loss and voltage and current stress are caused, the short plate effect forces the whole chip parallel module to operate in a derating way, and the failure rate and the service life of the whole chip parallel module are also reduced.

SUMMERY OF THE UTILITY MODEL

Accordingly, there is a need to overcome the drawbacks of the prior art and to provide a semiconductor device and chip parallel module, which can make the distribution of parasitic parameters uniform and improve the product performance.

The technical scheme is as follows: a chip parallel module, comprising: the substrate is provided with a first end and a second end which are opposite to each other, and a first conducting layer and a second conducting layer which are spaced and arranged along the direction from the first end to the second end are arranged on one side surface of the substrate; the first power terminal is positioned at the first end of the substrate and electrically connected with the first conductive layer, and the second power terminal is positioned at the second end of the substrate and electrically connected with the second conductive layer; at least two power chips, all of which are arranged on the first conductive layer in parallel and are sequentially arranged along the direction from the first end to the second end; each power chip is electrically connected with the second conductive layer through at least one first bonding wire; for any two adjacent power chips, the first bonding wire length of the power chip close to the second end is larger than that of the other power chip.

For any two adjacent power chips, the length of the first bonding wire of the power chip close to the second end is greater than that of the first bonding wire of the other power chip, that is, the resistance and the inductance of the first bonding wire of the power chip close to the second end are both greater than those of the first bonding wire of the other power chip, that is, the length of the first bonding wire of the power chip far away from the first end is greater, so that the parasitic parameters of the power chip far away from the first end can be increased, the parasitic parameters from all the power chips to the second end tend to be consistent, and the product performance of the chip parallel module can be improved.

In one embodiment, the first bond wire is arc-shaped; for any two adjacent power chips, the first bond wire span of the power chip close to the second end is larger than that of the other power chip, and/or the first bond wire bump height of the power chip close to the second end is larger than that of the other power chip.

In one embodiment, for any two adjacent power chips, the number of the first bonding wires of the power chip close to the second end is less than or equal to the number of the first bonding wires of the other power chip; and/or for any two adjacent power chips, the first bonding wire diameter of the power chip close to the second end is smaller than or equal to the first bonding wire diameter of the other power chip.

In one embodiment, the chip parallel module further comprises a signal terminal; a third conducting layer is arranged on one side face of the substrate and positioned on one side of the second conducting layer, and the third conducting layer is respectively provided with intervals with the first conducting layer and the second conducting layer; the signal terminal is electrically connected with the third conductive layer; each power chip is also electrically connected with the third conductive layer through a second bonding wire.

In one embodiment, for any two adjacent power chips, the second bonding wire length of the power chip close to the second end is greater than that of the other power chip.

In one embodiment, the second bond wire is arc-shaped; for any two adjacent power chips, the second bond wire span of the power chip close to the second end is larger than that of the other power chip, and/or the second bond wire bump height of the power chip close to the second end is larger than that of the other power chip.

In one embodiment, the number of the third conducting layers is at least two, and at least two third conducting layers are arranged at intervals; the number of the signal terminals is at least two, and the at least two signal terminals are correspondingly connected with the at least two third conductive layers one to one; the number of the second bonding wires of the power chip is at least two, and the at least two second bonding wires of the power chip are respectively and electrically connected to the at least two third conductive layers.

In one embodiment, the chip parallel module further includes at least two metal blocks, and the at least two metal blocks are arranged in one-to-one correspondence with the at least two power chips; the metal block is positioned between the power chip and the first conducting layer; the projection of the metal block on the substrate is a first projection, the projection of the power chip corresponding to the metal block on the substrate is a second projection, and the first projection completely covers the second projection.

In one embodiment, for any two adjacent power chips, the area of the metal block corresponding to the power chip close to the second end is smaller than the area of the metal block corresponding to the other power chip; and/or for any two adjacent power chips, the thickness of the metal block corresponding to the power chip close to the second end is smaller than that of the metal block corresponding to the other power chip.

A semiconductor device comprises the chip parallel module.

In the semiconductor device, for any two adjacent power chips, the length of the first bonding wire of the power chip close to the second end is greater than that of the other power chip, that is, the resistance and the inductance of the first bonding wire of the power chip close to the second end are both greater than those of the other power chip, that is, the length of the first bonding wire of the power chip farther away from the first end is greater, so that the parasitic parameters of the power chip farther away from the first end can be increased, the parasitic parameters of all the power chips to the second end tend to be consistent, and the product performance of the chip parallel module can be improved.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the utility model and, together with the description, serve to explain the utility model and not to limit the utility model.

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a chip parallel module according to an embodiment of the present invention;

FIG. 2 is a schematic view of the structure of FIG. 1 from another perspective;

fig. 3 is an enlarged schematic view of fig. 2 at a.

10. A substrate; 11. a first end; 12. a second end; 13. a first conductive layer; 14. a second conductive layer; 15. a third conductive layer; 20. a first power terminal; 30. a second power terminal; 40. a power chip; 51. a first bonding wire; 52. a second bonding wire; 60. a signal terminal; 70. a metal block; 71. a first tie layer; 72. a second connection layer.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

Referring to fig. 1 to 3, fig. 1 is a schematic structural diagram illustrating a chip parallel module according to an embodiment of the utility model; FIG. 2 shows another perspective view of the structural schematic of FIG. 1; fig. 3 shows an enlarged schematic view of fig. 2 at a. An embodiment of the present invention provides a chip parallel module, including: the power module comprises a substrate 10, a first power terminal 20, a second power terminal 30 and at least two power chips 40. The substrate 10 has a first end 11 and a second end 12 opposite to each other, and a first conductive layer 13 and a second conductive layer 14 are disposed on one side of the substrate 10 and spaced from each other along a direction from the first end 11 to the second end 12. The first power terminal 20 is located at the first end 11 of the substrate 10 and electrically connected to the first conductive layer 13, and the second power terminal 30 is located at the second end 12 of the substrate 10 and electrically connected to the second conductive layer 14. All the power chips 40 are disposed in parallel on the first conductive layer 13 and are sequentially disposed along the direction from the first end 11 to the second end 12. Each power chip 40 is electrically connected to the second conductive layer 14 through at least one first bonding wire 51. For any two adjacent power chips 40, the length of the first bonding wire 51 of the power chip 40 close to the second end 12 is greater than the length of the first bonding wire 51 of the other power chip 40.

For any two adjacent power chips 40, the length of the first bonding wire 51 of the power chip 40 close to the second end 12 is greater than the length of the first bonding wire 51 of another power chip 40, that is, the resistance and inductance of the first bonding wire 51 of the power chip 40 close to the second end 12 are both greater than the resistance and inductance of the first bonding wire 51 of another power chip 40, that is, the length of the first bonding wire 51 of the power chip 40 farther from the first end 11 is greater, so that the parasitic parameter of the power chip 40 farther from the first end 11 can be increased, the parasitic parameters of all the power chips 40 to the second end 12 (the second power terminal 30) tend to be consistent, and the product performance of the chip parallel module can be improved.

It should be noted that the first power terminal 20 and the second power terminal 30 extend outward and are electrically connected to the bus bar, the capacitor, and other structures according to actual requirements.

Referring to fig. 1 to 3, in one embodiment, the first bonding wire 51 has an arc shape. Of course, as an alternative, the first bonding wire 51 is not limited to an arc shape, and may also be a folded wire shape or a shape combining the folded wire shape and the arc shape, etc., which is not limited herein and may be set according to the actual situation.

Further, for any two adjacent power chips 40, the first bond wire 51 span of the power chip 40 close to the second end 12 is larger than the first bond wire 51 span of another power chip 40, and/or the first bond wire 51 bump height of the power chip 40 close to the second end 12 is larger than the first bond wire 51 bump height of another power chip 40.

Note that the span of the first bonding wire 51 refers to a distance from a position where the first bonding wire 51 is connected to the power chip 40 to a position where the first bonding wire 51 is connected to the second conductive layer 14, and the span is indicated by S in fig. 1. The span S ranges, for example, from 0.1mm to 20 mm.

Note that, the bump height of the first bonding wire 51 refers to a distance from a position on the first bonding wire 51 farthest from the substrate 10 to the substrate 10, and the bump height is indicated by h in fig. 3. The ridge height h ranges, for example, from 0.1mm to 7 mm.

In one embodiment, for any two adjacent power chips 40, the number of the first bonding wires 51 of the power chip 40 close to the second end 12 is less than or equal to the number of the first bonding wires 51 of the other power chip 40; and/or, for any two adjacent power chips 40, the wire diameter of the first bonding wire 51 of the power chip 40 close to the second end 12 is smaller than or equal to the wire diameter of the first bonding wire 51 of the other power chip 40. Therefore, the parasitic parameters of the power chips 40 far away from the first end 11 can be increased, so that the parasitic parameters from all the power chips 40 to the first end 11 tend to be consistent, and the product performance of the chip parallel module can be improved.

Referring to fig. 1 to 3, of course, as an alternative, for any two adjacent power chips 40, the number of the first bonding wires 51 of the power chip 40 close to the second end 12 is equal to the number of the first bonding wires 51 of the other power chip 40; for any two adjacent power chips 40, the first wire bond 51 of the power chip 40 close to the second end 12 has a wire diameter equal to that of the first wire bond 51 of the other power chip 40.

Referring to fig. 1-3, in one embodiment, the die parallel module further includes a signal terminal 60. The substrate 10 is further provided with a third conductive layer 15 on one side of the second conductive layer 14, specifically, the third conductive layer 15 is located between the first conductive layer 13 and the second conductive layer 14. The third conductive layer 15 is spaced apart from the first conductive layer 13 and the second conductive layer 14. The signal terminal 60 is electrically connected to the third conductive layer 15. Each power chip 40 is also electrically connected to the third conductive layer 15 by a second bonding wire 52. In this way, the signal terminal 60 is electrically connected to the power chip 40 through the third conductive layer 15 and the second bonding wire 52, so as to transmit the control signal.

In one embodiment, for any two adjacent power chips 40, the length of the second bonding wire 52 of the power chip 40 close to the second end 12 is greater than the length of the second bonding wire 52 of the other power chip 40. Therefore, the parasitic parameters of the power chips 40 far away from the first end 11 can be increased, so that the parasitic parameters from all the power chips 40 to the first end 11 tend to be consistent, and the product performance of the chip parallel module can be improved.

As an alternative, for any two adjacent power chips 40, the length of the second bonding wire 52 of the power chip 40 close to the second end 12 may also be less than or equal to the length of the second bonding wire 52 of another power chip 40, which is not limited herein and is set according to actual requirements.

Referring to fig. 1-3, in one embodiment, the second bond wire 52 is arc-shaped. As an alternative, the second bonding wire 52 is not limited to an arc shape, and may also be a folded wire shape or a shape in which the folded wire shape is combined with the arc shape, etc., which is not limited herein and may be set according to practical situations.

Further, for any two adjacent power chips 40, the span of the second bonding wire 52 of the power chip 40 close to the second end 12 is larger than the span of the second bonding wire 52 of another power chip 40, and/or the bump height of the second bonding wire 52 of the power chip 40 close to the second end 12 is larger than the bump height of the second bonding wire 52 of another power chip 40. Therefore, the parasitic parameters of the power chips 40 far away from the first end 11 can be increased, so that the parasitic parameters from all the power chips 40 to the first end 11 tend to be consistent, and the product performance of the chip parallel module can be improved.

Note that the span of the second bonding wire 52 refers to a distance from a position where the second bonding wire 52 is connected to the power chip 40 to a position where the first bonding wire 51 is connected to the second conductive layer 14.

Note that the bump height of the second bonding wire 52 refers to a distance from a position on the second bonding wire 52 farthest from the substrate 10 to the substrate 10.

Referring to fig. 1 to 3, in one embodiment, the number of the third conductive layers 15 is at least two, and at least two third conductive layers 15 are disposed at intervals. At least two signal terminals 60 are provided, and at least two signal terminals 60 are connected to at least two third conductive layers 15 in a one-to-one correspondence. At least two second bonding wires 52 of the power chip 40 are provided, and the at least two second bonding wires 52 of the power chip 40 are electrically connected to the at least two third conductive layers 15, respectively.

It should be noted that the number of the second bonding wires 52 of the power chip 40 may be the same as the number of the third conductive layers 15, or the number of the second bonding wires 52 of the power chip 40 may be greater than the number of the third conductive layers 15. When the number of the second bonding wires 52 of the power chip 40 is the same as that of the third conductive layer 15, the second bonding wires 52 of the power chip 40 are electrically connected to the third conductive layer 15 in a one-to-one correspondence manner; when the number of the second bonding wires 52 of the power chip 40 is greater than the number of the third conductive layers 15, at least one third conductive layer 15 is electrically connected to at least two second bonding wires 52 of the power chip 40. In addition, as an alternative, one of the third conductive layer 15, the signal terminal 60, and the second bonding wire 52 may be provided.

Referring to fig. 1 to 3, further, for any two adjacent power chips 40, the number of the second bonding wires 52 of the power chip 40 close to the second end 12 is less than or equal to the number of the second bonding wires 52 of another power chip 40; and/or, for any two adjacent power chips 40, the wire diameter of the second bonding wire 52 of the power chip 40 close to the second end 12 is smaller than or equal to the wire diameter of the second bonding wire 52 of the other power chip 40.

In one embodiment, the first bonding wire 51 and the second bonding wire 52 are each made of metal, such as copper, gold, aluminum, silver, etc., and are not limited herein.

Referring to fig. 1 to 3, in an embodiment, the chip parallel module further includes at least two metal blocks 70, and the at least two metal blocks 70 are disposed in one-to-one correspondence with the at least two power chips 40. The metal block 70 is located between the power chip 40 and the first conductive layer 13. The projection of the metal block 70 on the substrate 10 is a first projection, the projection of the power chip 40 corresponding to the metal block 70 on the substrate 10 is a second projection, and the first projection completely covers the second projection. As such, by disposing the metal block 70 between the power chip 40 and the first conductive layer 13, on one hand, the heat of the power chip 40 can be easily diffused outward through the metal block 70, and the heat dissipation performance is good; on the other hand, the parasitic parameters of the power chips 40 can be increased, so that the parasitic parameters of different power chips 40 on the substrate 10 are kept consistent.

In this embodiment, the power chip 40 is connected to the metal block 70 through one side surface thereof, and the other side surface of the metal block 70 is also connected to the first conductive layer 13 through the second connection layer 72. The first connection layer 71 includes, but is not limited to, solder, sintered silver. Likewise, the second connection layer 72 includes, but is not limited to, solder, sintered silver.

In one embodiment, for any two adjacent power chips 40, the area of the metal block 70 corresponding to the power chip 40 close to the second end 12 is smaller than the area of the metal block 70 corresponding to another power chip 40; and/or, for any two adjacent power chips 40, the thickness of the metal block 70 corresponding to the power chip 40 close to the second end 12 is smaller than the thickness of the metal block 70 corresponding to another power chip 40. Therefore, the parasitic parameters of the power chips 40 far away from the first end 11 can be increased, so that the parasitic parameters from all the power chips 40 to the first end 11 tend to be consistent, and the product performance of the chip parallel module can be improved.

As an alternative, all the metal blocks 70 have the same length, width and thickness.

As an alternative, the lengths and the wire diameters of all the second bonding wires 52 are the same. In addition, the number of the second bonding wires 52 of each power chip 40 is the same.

In one embodiment, the substrate 10 is provided with a fourth conductive layer (not shown) on a side facing away from the first conductive layer 13. Therefore, the fourth conducting layer can play a role in heat dissipation.

Specifically, the first conductive layer 13, the second conductive layer 14, and the third conductive layer 15 are formed on one side of the substrate 10 by, for example, etching, plating, sputtering. Similarly, a fourth conductive layer is formed on the other side surface of the substrate 10 by, for example, plating, sputtering, or the like. In addition, the first conductive layer 13, the second conductive layer 14, the third conductive layer 15 and the fourth conductive layer are, for example, copper, aluminum, silver, gold, or the like.

In one embodiment, a semiconductor device includes the die attach module of any of the above embodiments.

For any two adjacent power chips 40, the length of the first bonding wire 51 of the power chip 40 close to the second end 12 is greater than the length of the first bonding wire 51 of another power chip 40, that is, the resistance and inductance of the first bonding wire 51 of the power chip 40 close to the second end 12 are both greater than the resistance and inductance of the first bonding wire 51 of another power chip 40, that is, the length of the first bonding wire 51 of the power chip 40 farther from the first end 11 is greater, so that the parasitic parameters of the power chip 40 farther from the second end 12 can be increased, the parasitic parameters of all the power chips 40 to the second end 12 tend to be consistent, and the product performance of the chip parallel module can be improved.

The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the utility model. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the utility model and to simplify the description, and are not intended to indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and are not to be considered limiting of the utility model.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.

In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.

In the present invention, unless otherwise expressly stated or limited, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through an intermediate. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.

It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "upper," "lower," "left," "right," and the like as used herein are for illustrative purposes only and do not denote a unique embodiment.

Claims (10)

1. A chip parallel module, comprising:

the substrate is provided with a first end and a second end which are opposite to each other, and a first conducting layer and a second conducting layer which are spaced and arranged along the direction from the first end to the second end are arranged on one side surface of the substrate;

the first power terminal is positioned at the first end of the substrate and electrically connected with the first conductive layer, and the second power terminal is positioned at the second end of the substrate and electrically connected with the second conductive layer;

at least two power chips, all of which are arranged on the first conductive layer in parallel and are sequentially arranged along the direction from the first end to the second end; each power chip is electrically connected with the second conductive layer through at least one first bonding wire; for any two adjacent power chips, the first bonding wire length of the power chip close to the second end is larger than that of the other power chip.

2. The die paddle module of claim 1, wherein the first bond wire is arc-shaped; for any two adjacent power chips, the first bond wire span of the power chip close to the second end is larger than that of the other power chip, and/or the first bond wire bump height of the power chip close to the second end is larger than that of the other power chip.

3. The die paddle module of claim 1, wherein for any two adjacent power dies, the first number of bond wires of the power die near the second end is less than or equal to the first number of bond wires of the other power die; and/or for any two adjacent power chips, the first bonding wire diameter of the power chip close to the second end is smaller than or equal to the first bonding wire diameter of the other power chip.

4. The chip parallel module according to claim 1, wherein the chip parallel module further comprises a signal terminal; a third conducting layer is arranged on one side face of the substrate and positioned on one side of the second conducting layer, and the third conducting layer is respectively provided with intervals with the first conducting layer and the second conducting layer; the signal terminal is electrically connected with the third conductive layer; each power chip is also electrically connected with the third conductive layer through a second bonding wire.

5. The die attach module of claim 4 wherein for any two adjacent power dies, the second bond wire length of the power die proximate the second end is greater than the second bond wire length of the other power die.

6. The die paddle module of claim 4, wherein the second bond wire is arc-shaped; for any two adjacent power chips, the second bond wire span of the power chip close to the second end is larger than that of the other power chip, and/or the second bond wire bump height of the power chip close to the second end is larger than that of the other power chip.

7. The chip parallel module according to claim 4, wherein the number of the third conductive layers is at least two, and at least two of the third conductive layers are arranged at intervals; the number of the signal terminals is at least two, and the at least two signal terminals are correspondingly connected with the at least two third conductive layers one to one; the number of the second bonding wires of the power chip is at least two, and the at least two second bonding wires of the power chip are respectively and electrically connected to the at least two third conductive layers.

8. The chip parallel module according to claim 1, further comprising at least two metal blocks, wherein the at least two metal blocks are disposed in one-to-one correspondence with the at least two power chips; the metal block is positioned between the power chip and the first conducting layer; the projection of the metal block on the substrate is a first projection, the projection of the power chip corresponding to the metal block on the substrate is a second projection, and the first projection completely covers the second projection.

9. The die parallel module according to claim 8, wherein for any two adjacent power dies, the area of the metal block corresponding to the power die close to the second end is smaller than the area of the metal block corresponding to the other power die; and/or for any two adjacent power chips, the thickness of the metal block corresponding to the power chip close to the second end is smaller than that of the metal block corresponding to the other power chip.

10. A semiconductor device characterized in that it comprises a chip parallel module according to any one of claims 1 to 9.

Images