CN210245488U - Non-contact type upper and lower chip packaging structure - Google Patents
Non-contact type upper and lower chip packaging structure Download PDFInfo
- Publication number
- CN210245488U CN210245488U CN201921189793.0U CN201921189793U CN210245488U CN 210245488 U CN210245488 U CN 210245488U CN 201921189793 U CN201921189793 U CN 201921189793U CN 210245488 U CN210245488 U CN 210245488U
- Authority
- CN
- China
- Prior art keywords
- chip
- frame
- pin
- sub
- pins
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The utility model discloses a chip package structure about non-contact, include: the lead frame comprises a first sub frame and a second sub frame, wherein one side of the first sub frame, which is opposite to the second sub frame, is provided with a first pin, a second pin and a third pin, the second pin is positioned below the first pin, the lower surface of the first chip is respectively and electrically connected with the first pins on the first sub frame and the second sub frame, the lower surface of the second chip is respectively and fixedly connected with the second pins on the first sub frame and the second sub frame through an insulating glue layer, the upper surface of the second chip is respectively and electrically connected with the third pins on the first sub frame and the second sub frame through bonding wires, the plastic package body encapsulates the first chip, the second chip, the first pin, the second pin and the third pin, and the utilization rate of the lead frame structure space is improved by embedding the small chip at the bottom of the large chip, the packaging volume is reduced, and the heat dissipation efficiency is improved.
Description
Technical Field
The utility model relates to a microelectronic packaging technology field, concretely relates to chip packaging structure about non-contact.
Background
Chip packaging, a technique for packaging integrated circuits with insulating plastic or ceramic materials, not only serves to place, secure, seal, protect the chip and enhance thermal conductivity, but also serves as a bridge to the internal world of the chip and external circuitry. As smart products and wearable devices are developed to be smaller, thinner and lighter, chip manufacturing processes are also continuously developed from micrometer to nanometer, but the process size of chip manufacturing is more difficult to develop downwards.
As shown in fig. 1 of the specification, the conventional multi-chip package mainly adopts a mode that a large chip 20 is stacked on the upper surface of a lead frame 10, and a small chip 30 is stacked on the upper surface of the large chip 20, so that the small chip 30 and the large chip 20 are in a very close structure, the distance from the lower surface of the large chip 20 to the lower surface of a plastic package body 40 and the distance from the small chip 30 to the upper surface of the plastic package body 40 are both large, heat dissipation between the chips is not utilized, the plastic package body 40 after plastic package molding is large in thickness, and the overall volume of a product is large.
SUMMERY OF THE UTILITY MODEL
The utility model discloses to the disappearance that prior art exists, provide a chip packaging structure about non-contact, its encapsulation space that can save the chip reduces the thickness of the plastic-sealed body, improves chip radiating efficiency.
In order to achieve the above purpose, the utility model adopts the following technical scheme:
a non-contact top and bottom chip package structure, comprising:
the lead frame comprises a first sub frame and a second sub frame, wherein one opposite side of the first sub frame and one opposite side of the second sub frame are respectively provided with a first pin, a second pin and a third pin, the first pin and the second pin are arranged in a vertically staggered mode and are positioned below the first pin, a first opening is formed between the first pins on the first sub frame and the second sub frame, a second opening is formed between the second pins on the first sub frame and the second sub frame, and the width of the first opening is larger than that of the second opening;
the lower surface of the first chip is electrically connected with the first pins on the first sub-frame and the second sub-frame respectively, and a part of the lower surface of the first chip is exposed by the first opening;
the lower surface of the second chip is fixedly connected with the second pins on the first sub-frame and the second sub-frame through an insulating glue layer, part of the lower surface of the second chip is exposed by the second opening, the upper surface of the second chip is electrically connected with the third pins on the first sub-frame and the second sub-frame through bonding wires, and a gap is kept between the upper surface of the second chip and the lower surface of the first chip;
and the plastic package body encapsulates the first chip, the second chip, the first pin, the second pin and the third pin.
As a preferred scheme of the utility model, first pin is the straight pin with the upper surface parallel and level of lead frame main part, second pin and third pin are the pin of dishing of forming from the upper surface downward of lead frame main part, and the upper surface parallel and level of second pin and third pin.
As an optimized scheme of the utility model, the lower surface of first chip is equipped with the copper post bump of stretching to the evagination, the end of copper post bump is equipped with the tin cap, first chip passes through the tin cap and is welded connection respectively with first pin on the sub-frame of first sub-frame and the second sub-frame.
As an optimized scheme of the utility model, the upper surface of second chip is equipped with a plurality of pads, the pad passes through the bonding wire and the first sub-frame and the sub-frame of second on the third pin welded connection respectively.
As a preferred embodiment of the present invention, the second pin extends below the first opening.
As a preferable embodiment of the present invention, the distance between the upper surface of the first chip and the upper surface of the plastic package body is 90-110 μm.
As a preferable embodiment of the present invention, the distance between the upper surface of the first chip and the upper surface of the plastic package body is 100 μm.
As a preferable embodiment of the present invention, the surface area of the first chip is larger than the surface area of the second chip.
Compared with the prior art, the utility model has obvious advantage and beneficial effect, particularly speaking, through making second pin and third pin dent downwards relatively first pin, first chip is installed on the first pin on first sub-frame and second sub-frame, the second chip is installed on the second pin on first sub-frame and second sub-frame, and the second chip passes through the bonding wire and is connected with the third pin electricity, thereby make the chiplet bury in the bottom of big chip, and keep the interval between chiplet and the big chip, compared with the structure that the chiplet is carried to the surface of big chip, the utility ratio of lead frame structure space has been improved, the thickness of plastic-sealed body has been reduced, the encapsulation volume has been reduced, be favorable to the product towards littleer, thinner, lighter direction development; meanwhile, the chip is closer to the upper and lower side surfaces of the plastic package body, so that the heat dissipation of the chip is facilitated, the production quality of a product is improved, and the service life of the product is prolonged; the second pin and the third pin are the recessing pins formed by recessing downwards from the upper surface of the lead frame main body, so that the length of a welding wire is reduced, and the wire arc is more stable.
To more clearly illustrate the structural features and technical means of the present invention and the specific objects and functions achieved thereby, the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments:
drawings
FIG. 1 is a diagram of a chip package structure in the prior art;
fig. 2 is a schematic top view of an embodiment of the present invention;
FIG. 3 is a schematic side view of an embodiment of the present invention;
fig. 4 is a schematic structural view after rib cutting according to an embodiment of the present invention.
The attached drawings indicate the following:
10. a lead frame; 11. A first subframe; 12. A second sub-frame;
13. a first pin; 14. A second pin; 15. A third pin;
16. welding wires; 17. An insulating glue layer; 20. A first chip;
21. copper pillar bumps; 30. A second chip; 31. A pad;
40. and (7) molding the body.
Detailed Description
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the indicated position or element must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.
In the description of the present invention, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood as appropriate by those of ordinary skill in the art.
As shown in fig. 2 to 4, a non-contact top and bottom chip package structure includes: the lead frame 10 comprises a first sub-frame 11 and a second sub-frame 12, wherein a first pin 13, a second pin 14 and a third pin 15 are arranged on one opposite side of the first sub-frame 11 and one opposite side of the second sub-frame 12, the first pin 13 and the second pin 14 are arranged in a staggered mode, the second pin 14 is located below the first pin 13, a first opening is formed between the first pins 13 on the first sub-frame 11 and the second sub-frame 12, the second pin 14 extends out of the lower portion of the first opening, a second opening is formed between the second pins 14 on the first sub-frame 11 and the second sub-frame 12, and the width of the first opening is larger than that of the second opening; a first chip 20, a lower surface of the first chip 20 being electrically connected to the first leads 13 on the first subframe 11 and the second subframe 12, respectively, and a portion of the lower surface of the first chip 20 being exposed by the first opening; a second chip 30, a lower surface of the second chip 30 is fixedly connected to the second pins 14 on the first sub-frame 11 and the second sub-frame 12 through an insulating adhesive layer 17, and a portion of the lower surface of the second chip 30 is exposed by the second opening, an upper surface of the second chip 30 is electrically connected to the third pins 15 on the first sub-frame 11 and the second sub-frame 12 through bonding wires 16, respectively, and a gap is maintained between the upper surface of the second chip 30 and the lower surface of the first chip 20; the plastic package body 40 encapsulates the first chip 20, the second chip 30, the first leads 13, the second leads 14 and the third leads 15, and a distance between the upper surface of the first chip 20 and the upper surface of the plastic package body 40 is 90-110 μm, and specifically 100 μm. The surface area of the first chip 20 is larger than that of the second chip 30
Specifically, first pin 13 is the straight pin with the upper surface parallel and level of lead frame main part, second pin 14 and third pin 15 are the pin of caving of forming from the upper surface of lead frame main part is dug downwards, and the upper surface parallel and level of second pin 14 and third pin 15. The lower surface of the first chip 20 is provided with a copper pillar bump 21 protruding downwards, the end of the copper pillar bump 21 is provided with a tin cap, and the first chip 20 is respectively connected with the first pins 13 on the first sub-frame 11 and the second sub-frame 12 by welding through the tin cap. The upper surface of the second chip 30 is provided with a plurality of bonding pads 31, and the bonding pads 31 are respectively connected with the third pins 15 on the first sub-frame 11 and the second sub-frame 12 by bonding wires 16.
The utility model discloses the encapsulation process includes following step:
1) forming a pin: forming a first pin 13, a second pin 14 and a third pin 15 on a first sub frame 11 and a second sub frame 12 of a lead frame 10 by punching or cutting, wherein the extension length of the first pin 13 is smaller than that of the second pin 14 and the third pin 15, and the surface area of the second pin 14 is larger than that of the first pin 13 and that of the third pin 15;
2) and (3) concave forming of the second pin 14: stamping the second pins 14 by using a die, so that the second pins 14 are bent downwards relative to the first pins 13, a first opening is formed between the first pins 13 on the first sub-frame 11 and the second sub-frame 12, a second opening is formed between the second pins 14 on the first sub-frame 11 and the second sub-frame 12, and the width of the first opening is greater than that of the second opening;
3) and (3) recessing and molding a third pin 15: stamping the third pin 15 by using a die, so that the third pin 15 is bent downwards relative to the first pin 13; the third pins 15 comprise three inner pins and four peripheral pins, and when the third pins are punched, the three inner pins are firstly recessed, then the four peripheral pins are recessed, and finally the upper surfaces of the third pins 15 are flush with the upper surfaces of the second pins 14;
4) second chip 30 assembly: firstly, the second chip 30 is made to pass through the first opening, then the second chip 30 is fixedly connected with the second pins 14 on the first sub-frame 11 and the second sub-frame 12 respectively by the insulating glue layer 17, and finally the bonding pad 31 on the upper surface of the second chip 30 is electrically connected with the third pin 15 by the bonding wire 16; wherein the insulating adhesive layer 17 is cured after being baked for 2-3 hours at the temperature of 140-160 ℃, so that the second chip 30 is fixedly connected with the second pins 14;
5) first chip 20 assembly: the lower surface of the first chip 20 is provided with a plurality of copper pillar bumps 21, the tail ends of the copper pillar bumps 21 are provided with tin caps, and the tin caps are subjected to reflow soldering to enable the lower surface of the first chip 20 to be electrically connected with the first pins 13 on the first sub-frame 11 and the second sub-frame 12 respectively;
6) packaging and molding: encapsulating the first chip 20, the second chip 30, the first pins 13, the second pins 14 and the third pins 15 with an encapsulating material through a vacuum mold to form a plastic package body 40, and controlling the distance between the upper surface of the first chip 20 and the upper surface of the plastic package body 40 to be 90-110 μm, specifically 100 μm; when in packaging, the packaging material is plastic particles with good fluidity and the particle size of less than 50 μm.
7) The rib cutting molding is to cut the connecting ribs on the lead frame 10 to form a plurality of discrete packages and to bend and mold the outer leads of the lead frame 10.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention, so any modifications, equivalent replacements, improvements, etc. made to the above embodiments by the technology of the present invention are all within the scope of the technical solution of the present invention.
Claims (8)
1. A non-contact top and bottom chip package structure, comprising:
the lead frame comprises a first sub frame and a second sub frame, wherein one opposite side of the first sub frame and one opposite side of the second sub frame are respectively provided with a first pin, a second pin and a third pin, the first pin and the second pin are arranged in a vertically staggered mode and are positioned below the first pin, a first opening is formed between the first pins on the first sub frame and the second sub frame, a second opening is formed between the second pins on the first sub frame and the second sub frame, and the width of the first opening is larger than that of the second opening;
the lower surface of the first chip is electrically connected with the first pins on the first sub-frame and the second sub-frame respectively, and a part of the lower surface of the first chip is exposed by the first opening;
the lower surface of the second chip is fixedly connected with the second pins on the first sub-frame and the second sub-frame through an insulating glue layer, part of the lower surface of the second chip is exposed by the second opening, the upper surface of the second chip is electrically connected with the third pins on the first sub-frame and the second sub-frame through bonding wires, and a gap is kept between the upper surface of the second chip and the lower surface of the first chip;
and the plastic package body encapsulates the first chip, the second chip, the first pin, the second pin and the third pin.
2. The upper and lower non-contact chip package structure according to claim 1, wherein the first lead is a straight lead flush with the upper surface of the lead frame body, the second lead and the third lead are both recessed leads formed by recessing the upper surface of the lead frame body downward, and the upper surfaces of the second lead and the third lead are flush.
3. The upper and lower non-contact chip package structure as claimed in claim 1, wherein the lower surface of the first chip is provided with a copper pillar bump protruding downward, the end of the copper pillar bump is provided with a tin cap, and the first chip is soldered to the first pins on the first sub-frame and the second sub-frame respectively through the tin cap.
4. The upper and lower non-contact chip package structure according to claim 1, wherein the second chip has a plurality of bonding pads on its upper surface, and the bonding pads are connected to the third pins on the first and second subframes by bonding wires.
5. The upper and lower non-contact chip package structure of claim 1, wherein the second leads extend below the first opening.
6. The upper and lower non-contact chip package structure according to claim 1, wherein the distance between the upper surface of the first chip and the upper surface of the plastic package body is 90-110 μm.
7. The upper and lower non-contact chip package structure according to claim 6, wherein the distance between the upper surface of the first chip and the upper surface of the plastic package body is 110 μm.
8. The upper and lower non-contact chip package structure of claim 1, wherein the surface area of the first chip is larger than the surface area of the second chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921189793.0U CN210245488U (en) | 2019-07-26 | 2019-07-26 | Non-contact type upper and lower chip packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921189793.0U CN210245488U (en) | 2019-07-26 | 2019-07-26 | Non-contact type upper and lower chip packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN210245488U true CN210245488U (en) | 2020-04-03 |
Family
ID=69993153
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201921189793.0U Active CN210245488U (en) | 2019-07-26 | 2019-07-26 | Non-contact type upper and lower chip packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN210245488U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110323198A (en) * | 2019-07-26 | 2019-10-11 | 广东气派科技有限公司 | Contactless upper lower chip packaging structure and its packaging method |
| CN110323198B (en) * | 2019-07-26 | 2024-04-26 | 广东气派科技有限公司 | Non-contact type upper and lower chip packaging structure and packaging method thereof |
-
2019
- 2019-07-26 CN CN201921189793.0U patent/CN210245488U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110323198A (en) * | 2019-07-26 | 2019-10-11 | 广东气派科技有限公司 | Contactless upper lower chip packaging structure and its packaging method |
| CN110323198B (en) * | 2019-07-26 | 2024-04-26 | 广东气派科技有限公司 | Non-contact type upper and lower chip packaging structure and packaging method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7405104B2 (en) | Lead frame and method of producing the same, and resin-encapsulated semiconductor device and method of producing the same | |
| US9087827B2 (en) | Mixed wire semiconductor lead frame package | |
| JP4195804B2 (en) | Dual die package | |
| US10886448B2 (en) | Method for producing lead frame, method for producing package and method for producing light emitting device | |
| CN110429075B (en) | High-density multi-side pin exposed packaging structure and production method thereof | |
| CN210040170U (en) | High-density non-base island chip packaging structure | |
| CN210245488U (en) | Non-contact type upper and lower chip packaging structure | |
| CN110323198B (en) | Non-contact type upper and lower chip packaging structure and packaging method thereof | |
| CN105355567B (en) | Two-sided etching water droplet bump package structure and its process | |
| CN105206594B (en) | One side etches water droplet bump package structure and its process | |
| US7768106B2 (en) | Multi-chip stack structure and fabrication method thereof | |
| CN210200717U (en) | Silicon controlled rectifier adopting insulation encapsulation | |
| CN209232767U (en) | A kind of novel semi-conductor encapsulating structure | |
| CN113140469A (en) | Packaging structure and forming method thereof | |
| CN206789535U (en) | A kind of fan-out package structure of power electronic devices | |
| CN213878074U (en) | Substrate for lead bonding process | |
| CN214588813U (en) | Packaging structure of reverse-bending internal insulation product | |
| CN101459154B (en) | Conductive wire rack and encapsulation construction applying the conductive wire rack | |
| US20180233438A1 (en) | Leadframe, semiconductor package including a leadframe and method for forming a semiconductor package | |
| CN214542226U (en) | Intelligent power module | |
| CN212587519U (en) | LED wafer packaging structure | |
| CN212182316U (en) | Carrier-free semiconductor laminated packaging structure | |
| CN107845721A (en) | A kind of LED support for being used for upside-down mounting or vertical LED chip | |
| CN214898401U (en) | Full packaging structure of power device | |
| CN101447443B (en) | Method for manufacturing high-frequency integrated circuit encapsulation structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |