CN110323198A - Contactless upper lower chip packaging structure and its packaging method - Google Patents

Contactless upper lower chip packaging structure and its packaging method Download PDF

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Publication number
CN110323198A
CN110323198A CN201910679831.9A CN201910679831A CN110323198A CN 110323198 A CN110323198 A CN 110323198A CN 201910679831 A CN201910679831 A CN 201910679831A CN 110323198 A CN110323198 A CN 110323198A
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China
Prior art keywords
pin
chip
subframe
opening
contactless
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Granted
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CN201910679831.9A
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Chinese (zh)
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CN110323198B (en
Inventor
程浪
杨建伟
易炳川
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Guangdong Style Science And Technology Ltd
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Guangdong Style Science And Technology Ltd
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Priority to CN201910679831.9A priority Critical patent/CN110323198B/en
Priority claimed from CN201910679831.9A external-priority patent/CN110323198B/en
Publication of CN110323198A publication Critical patent/CN110323198A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H01L23/49551—Cross section geometry characterised by bent parts
    • H01L23/49555—Cross section geometry characterised by bent parts the bent parts being the outer leads
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

The present invention discloses the contactless upper lower chip packaging structure of one kind and its packaging method, it include: lead frame, first chip, second chip and plastic-sealed body, the lead frame includes the first subframe and the second subframe, first subframe and the opposite side of the second subframe are equipped with the first pin, second pin and third pin, and the second pin is located at the lower section of the first pin, the lower surface of first chip is electrically connected with the first pin on the first subframe and the second subframe, the lower surface of second chip is respectively fixedly connected with by insulation glue-line with the second pin on the first subframe and the second subframe, upper surface is electrically connected by bonding wire and the third pin on the first subframe and the second subframe, the plastic-sealed body encapsulates first chip, second chip, first pin, second pin With third pin.The present invention makes small chip be embedded in the bottom of large chip, improves the utilization rate in lead frame structure space, reduces encapsulation volume, improves radiating efficiency.

Description

Contactless upper lower chip packaging structure and its packaging method
Technical field
The present invention relates to microelectronic packaging technology fields, and in particular to a kind of contactless upper lower chip packaging structure and its Packaging method.
Background technique
Chip package is a kind of technology for being packaged the plastics of integrated circuit insulation or ceramic material, does not pacify only up to It puts, fix, sealing, protecting the effect of chip and increased thermal conductivity energy, but also being to link up the chip interior world and external circuit Bridge.As intellectual product and wearable device Xiang Geng little, thinner and lighter direction develop, the manufacturing process of chip is not yet It is disconnected to develop from micron to nanoscale, but the process of chip manufacturing develop more down it is more difficult.
As shown in Figure of description 1, the existing main mode of multi-chip package, which is that large chip 20 is folded, is loaded in lead frame 10 Upper surface, small chip 30 is folded to be loaded in 20 upper surface of large chip, and distance is very between the small chip 30 of such structure and large chip 20 Closely, 20 lower surface of large chip to the lower surface of plastic-sealed body 40 distance and small chip 30 to plastic-sealed body 40 upper surface away from It is larger from, the heat dissipation between chip is not utilized, and 40 thickness of plastic-sealed body is big after plastic packaging molding, and product overall volume is larger.
Summary of the invention
The present invention in view of the existing deficiencies of the prior art, provides the contactless upper lower chip packaging structure of one kind and its encapsulation Method can save the encapsulated space of chip, reduce the thickness of plastic-sealed body, improve chip cooling efficiency.
To achieve the above object, the present invention is using following technical solution:
A kind of contactless upper lower chip packaging structure, comprising:
Lead frame, the lead frame include the first subframe and the second subframe, first subframe and the second sub- frame The opposite side of frame is equipped with the first pin, second pin and third pin, and first pin and second pin are staggered up and down Setting, and the second pin is located at the lower section of the first pin, and first on first subframe and the second subframe draws It is formed with the first opening between foot, is formed with second between the second pin on first subframe and the second subframe and opens Mouthful, the width of first opening is greater than the width of the second opening；
First chip, the lower surface of first chip and the first pin on the first subframe and the second subframe are distinguished It is electrically connected, and lower surface a part of first chip is exposed by the first opening；
The lower surface of second chip, second chip passes through on insulation glue-line and the first subframe and the second subframe Second pin is respectively fixedly connected with, and lower surface a part of second chip is exposed by the second opening, second core The upper surface of piece is electrically connected by bonding wire and the third pin on the first subframe and the second subframe, second core Gap is maintained between the upper surface of piece and the lower surface of the first chip；
Plastic-sealed body, the plastic-sealed body are encapsulated first chip, the second chip, the first pin, second pin and third and are drawn Foot.
As a preferred solution of the present invention, first pin is concordant with the upper surface of lead frame body straight Pin, the second pin and third pin are from the downward dent dent pin in the upper surface of lead frame body, and institute It is concordant with the upper surface of third pin to state second pin.
As a preferred solution of the present invention, the lower surface of first chip is equipped with the copper pillar bump protruded out downwards, The end of the copper pillar bump is equipped with tin cap, and first chip passes through the on tin cap and the first subframe and the second subframe Connection is respectively welded in one pin.
As a preferred solution of the present invention, the upper surface of second chip is equipped with several pads, and the pad is logical It crosses bonding wire and is respectively welded with the third pin on the first subframe and the second subframe and is connect.
As a preferred solution of the present invention, the second pin stretches out in the lower section of the first opening.
A kind of contactless chip packaging method up and down, comprising the following steps:
1) it molded lead: using punching or cutting mode, is formed on the first subframe and the second subframe of lead frame First pin, second pin and third pin out, and the extension elongation of the first pin is made to be less than second pin and third pin Extension elongation；
2) the dent molding of second pin: punching press is carried out to second pin using mold, makes second pin with respect to the first pin It bends downward, makes to form the first opening, the first subframe and the between the first pin on the first subframe and the second subframe The second opening is formed between second pin on two subframes, the width of the first opening is greater than the width of the second opening；
3) the dent molding of third pin: punching press is carried out to third pin using mold, makes third pin with respect to the first pin It bends downward；Wherein, the third pin includes the peripheral pins of three interior pins and four, when punching press, is first drawn in dent three Foot dent four peripheral pins again.
4) the second chip assembles: firstly, the second chip is made to pass through the first opening, then, making the second core using insulation glue-line Piece is respectively fixedly connected with the second pin on the first subframe and the second subframe, finally, making the second chip by bonding wire Upper surface and third pin are electrically connected；
5) the first chip assembles: being made on lower surface and the first subframe and the second subframe of the first chip using Reflow Soldering The first pin be electrically connected；
6) encapsulated moulding: by vacuum mold make encapsulating material encapsulate first chip, the second chip, the first pin, Second pin and third pin are to form plastic-sealed body；
7) dowel on lead frame is cut off, forms the packaging body of multiple dispersions by Trim Molding.
As a preferred solution of the present invention, in step 3), the upper surface of third pin and the upper surface of second pin Concordantly.
It as a preferred solution of the present invention, is 140 DEG C~160 DEG C in temperature when the second chip assembles in step 4) When baking 2~3h make the curable adhesive layer that insulate, realize being fixedly connected for the second chip and second pin.
As a preferred solution of the present invention, the upper surface of first chip is at a distance from the upper surface of plastic-sealed body 90-110μm。
As a preferred solution of the present invention, in step 6), the encapsulating material selects good fluidity, partial size less than 50 μm plastic grain.
The present invention has obvious advantages and beneficial effects compared with the existing technology, specifically, by making second pin Dent downwards with respect to the first pin with third pin, what the first chip was installed on the first subframe and the second subframe first draws On foot, the second chip is installed in the second pin on the first subframe and the second subframe, and the second chip passes through bonding wire It is electrically connected with third pin, so that small chip be made to be embedded in the bottom of large chip, and keeps spacing between small chip and large chip, Compared with the utilization rate that the folded structure for being downloaded to large chip surface of small chip improves lead frame structure space, reduce the thickness of plastic-sealed body Degree, reduces encapsulation volume, is conducive to product and develops towards smaller, thinner and lighter direction；Chip is above and below plastic-sealed body simultaneously Both side surface is closer, is more advantageous to chip cooling, improves production quality, improves product service life；Second pin and Three pins are to reduce the length of bonding wire, bank is more stable from the downward dent dent pin in the upper surface of lead frame body.
More clearly to illustrate structure feature of the invention, technological means and its specific purposes achieved and function, under In conjunction with attached drawing and specific embodiment, invention is further described in detail in face:
Detailed description of the invention
Fig. 1 is chip-packaging structure schematic diagram in the prior art；
Fig. 2 is the overlooking structure diagram of embodiments of the present invention；
Fig. 3 is the side structure schematic view of embodiments of the present invention；
Fig. 4 is the structural schematic diagram after embodiments of the present invention rib cutting.
Description of drawing identification:
10, lead frame；11, the first subframe；12, the second subframe；
13, the first pin；14, second pin；15, third pin；
16, bonding wire；17, insulate glue-line；20, the first chip；
21, copper pillar bump；30, the second chip；31, pad；
40, plastic-sealed body.
Specific embodiment
In the description of the present invention, it should be noted that term " center ", "upper", "lower", "left", "right", "vertical", The orientation or positional relationship of the instructions such as "horizontal", "inner", "outside" be based on the orientation or positional relationship shown in the drawings, merely to Convenient for description invention and simplify description, rather than the position of indication or suggestion meaning or element must have a particular orientation, with Specific orientation construction and operation, therefore be not considered as limiting the invention.
In the description of the present invention, it should be noted that unless otherwise clearly defined and limited, term " installation ", " phase Even ", " connection " shall be understood in a broad sense, for example, it may be being fixedly connected, may be a detachable connection, or be integrally connected；It can To be mechanical connection, it is also possible to be electrically connected；It can be directly connected, can also can be indirectly connected through an intermediary Connection inside two elements.For the ordinary skill in the art, concrete condition can be regarded and understand that above-mentioned term exists Concrete meaning in the present invention.
As in Figure 2-4, a kind of contactless upper lower chip packaging structure, comprising: lead frame 10, the lead frame 10 wrap Include the first subframe 11 and the second subframe 12, first subframe 11 and the opposite side of the second subframe 12 are equipped with One pin 13, second pin 14 and third pin 15, first pin 13 and about 14 second pin are arranged in a staggered manner, and institute State the lower section that second pin 14 is located at the first pin 13, the first pin 13 on first subframe 11 and the second subframe 12 Between be formed with the first opening, the second pin 14 stretches out in the lower section of the first opening, first subframe 11 and second The second opening is formed between second pin 14 on subframe 12, the width of first opening is greater than the width of the second opening Degree；The first pin on first chip 20, the lower surface of first chip 20 and the first subframe 11 and the second subframe 12 13 are electrically connected, and lower surface a part of first chip 20 is exposed by the first opening；Second chip 30, it is described The lower surface of second chip 30 is divided by the glue-line 17 that insulate with the second pin 14 on the first subframe 11 and the second subframe 12 Be not fixedly connected, and lower surface a part of second chip 30 by second opening expose, second chip 30 it is upper Surface is electrically connected by bonding wire 16 with the third pin 15 on the first subframe 11 and the second subframe 12, and described second Gap is maintained between the upper surface of chip 30 and the lower surface of the first chip 20；Plastic-sealed body 40, the plastic-sealed body 40 encapsulate institute State the first chip 20, the second chip 30, the first pin 13, second pin 14 and third pin 15, first chip 20 it is upper Surface is 90-110 μm, specially 100 μm at a distance from the upper surface of plastic-sealed body 40.Specifically, the first sub- frame in the present invention Frame 11 and the second subframe 12 pass through dowel integrally connected before cutting.
Specifically, first pin 13 is the straight pin concordant with the upper surface of lead frame body, described second draws Foot 14 and third pin 15 are from the downward dent dent pin in the upper surface of lead frame body, and the second pin 14 It is concordant with the upper surface of third pin 15.The lower surface of first chip 20 is equipped with the copper pillar bump 21 protruded out downwards, described The end of copper pillar bump 21 is equipped with tin cap, and first chip 20 passes through on tin cap and the first subframe 11 and the second subframe 12 The first pin 13 connection is respectively welded.The upper surface of second chip 30 is equipped with several pads 31, and the pad 31 passes through Bonding wire 16 is respectively welded with the third pin 15 on the first subframe 11 and the second subframe 12 and connect.
A kind of contactless chip packaging method up and down, comprising the following steps:
1) molded lead: using punching or cutting mode, in the first subframe 11 and the second subframe 12 of lead frame 10 On mold the first pin 13, second pin 14 and third pin 15, and draw the extension elongation of the first pin 13 less than second The extension elongation of foot 14 and third pin 15, the surface area of second pin 14 are greater than the surface of the first pin 13 and third pin 15 Product；
2) the dent molding of second pin 14: carrying out punching press to second pin 14 using mold, makes second pin 14 opposite the One pin 13 is bent downward, and makes to form the first opening between the first pin 13 on the first subframe 11 and the second subframe 12, The second opening is formed between second pin 14 on first subframe 11 and the second subframe 12, the width of the first opening is greater than the The width of two openings；
3) the dent molding of third pin 15: carrying out punching press to third pin 15 using mold, makes third pin 15 opposite the One pin 13 is bent downward；Wherein, the third pin 15 includes the peripheral pins of three interior pins and four, when punching press, is first beaten Dent four peripheral pins, the upper surface of the upper surface and second pin 14 that finally make third pin 15 are flat again for recessed three interior pins Together；
4) the second chip 30 assembles: firstly, the second chip 30 is made to pass through the first opening, then, being made using insulation glue-line 17 Second chip 30 is respectively fixedly connected with the second pin 14 on the first subframe 11 and the second subframe 12, finally, passing through weldering Line 16 is electrically connected the pad 31 of 30 upper surface of the second chip and third pin 15；Wherein, insulation glue-line 17 is 140 in temperature DEG C~160 DEG C when baking 2~3h after solidified, realize being fixedly connected for the second chip 30 and second pin 14；
5) the first chip 20 assembles: the lower surface of first chip 20 is equipped with several copper pillar bumps 21, copper pillar bump 21 End be equipped with tin cap, tin cap by Reflow Soldering make the first chip 20 lower surface and the first subframe 11 and the second subframe 12 On the first pin 13 be electrically connected；
6) encapsulated moulding: draw encapsulating material encapsulating first chip 20, the second chip 30, first by vacuum mold Foot 13, second pin 14 and third pin 15 control upper surface and the plastic-sealed body of the first chip 20 to form plastic-sealed body 40 The distance of 40 upper surface is 90-110 μm, specially 100 μm；When encapsulation, the encapsulating material selects good fluidity, partial size small In 50 μm of plastic grain.
7) dowel on lead frame 10 is cut off, forms the packaging body of multiple dispersions, while to lead frame by Trim Molding 10 outer pin carries out bending forming.
The above described is only a preferred embodiment of the present invention, be not intended to limit the invention, therefore it is all according to this hair The practical any modification, equivalent substitution, improvement and etc. to the above embodiments of bright technology, still fall within technical solution of the present invention In the range of.

Claims (10)

1. a kind of contactless upper lower chip packaging structure characterized by comprising
Lead frame, the lead frame include the first subframe and the second subframe, first subframe and the second subframe phase Pair side be equipped with the first pin, second pin and third pin, first pin and second pin are arranged in a staggered manner up and down, And the second pin is located at the lower section of the first pin, between the first pin on first subframe and the second subframe It is formed with the first opening, the second opening is formed between the second pin on first subframe and the second subframe, it is described The width of first opening is greater than the width of the second opening；
First chip, the lower surface of first chip and the first pin on the first subframe and the second subframe are electrical respectively Connection, and lower surface a part of first chip is exposed by the first opening；
The lower surface of second chip, second chip passes through second on insulation glue-line and the first subframe and the second subframe Pin is respectively fixedly connected with, and lower surface a part of second chip is exposed by the second opening, second chip Upper surface is electrically connected by bonding wire and the third pin on the first subframe and the second subframe, second chip Gap is maintained between upper surface and the lower surface of the first chip；
Plastic-sealed body, the plastic-sealed body encapsulate first chip, the second chip, the first pin, second pin and third pin.
2. contactless upper lower chip packaging structure according to claim 1, which is characterized in that first pin be with The concordant straight pin in the upper surface of lead frame body, the second pin and third pin are the upper table from lead frame body Dent dent pin downwards, and the second pin is concordant with the upper surface of third pin.
3. contactless upper lower chip packaging structure according to claim 1, which is characterized in that under first chip Surface is equipped with the copper pillar bump that protrudes out downwards, and the end of the copper pillar bump is equipped with tin cap, first chip by tin cap with Connection is respectively welded in the first pin on first subframe and the second subframe.
4. contactless upper lower chip packaging structure according to claim 1, which is characterized in that second chip it is upper Surface is equipped with several pads, and the pad is respectively welded by bonding wire and the third pin on the first subframe and the second subframe Connection.
5. contactless upper lower chip packaging structure according to claim 1, which is characterized in that the second pin is stretched out In the lower section of the first opening.
6. a kind of contactless chip packaging method up and down, which comprises the following steps:
1) using punching or cutting mode, the molded lead: is molded on the first subframe and the second subframe of lead frame One pin, second pin and third pin, and make the extension elongation of the first pin less than the stretching of second pin and third pin Length；
2) the dent molding of second pin: punching press is carried out to second pin using mold, keeps second pin downward with respect to the first pin Bending makes to form the first opening between the first pin on the first subframe and the second subframe, the first subframe and the second son The second opening is formed between second pin on frame, the width of the first opening is greater than the width of the second opening；
3) the dent molding of third pin: punching press is carried out to third pin using mold, keeps third pin downward with respect to the first pin Bending；
4) the second chip assemble: firstly, make the second chip pass through first opening, then, using insulation glue-line make the second chip with Second pin on first subframe and the second subframe is respectively fixedly connected with, finally, making the upper table of the second chip by bonding wire Face and third pin are electrically connected；
5) the first chip assembles: making the on the lower surface and the first subframe and the second subframe of the first chip using Reflow Soldering One pin is electrically connected；
6) encapsulated moulding: encapsulating material is made to encapsulate first chip, the second chip, the first pin, second by vacuum mold Pin and third pin are to form plastic-sealed body.
7. contactless chip packaging method up and down according to claim 6, which is characterized in that
In step 3), the upper surface of third pin and the upper surface of second pin are concordant.
8. contactless chip packaging method up and down according to claim 6, which is characterized in that in step 4), the second core When piece assembles, when temperature is 140 DEG C~160 DEG C, 2~3h of baking makes the curable adhesive layer that insulate, and realizes the second chip and second pin Be fixedly connected.
9. it is according to claim 6 it is contactless up and down chip packaging method, which is characterized in that first chip it is upper Surface is 90-110 μm at a distance from the upper surface of plastic-sealed body.
10. contactless chip packaging method up and down according to claim 6, which is characterized in that in step 6), the envelope Package material selects the plastic grain of good fluidity, partial size less than 50 μm.
CN201910679831.9A 2019-07-26 Non-contact type upper and lower chip packaging structure and packaging method thereof Active CN110323198B (en)

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CN110323198B CN110323198B (en) 2024-04-26

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