CN210040170U - High-density non-base island chip packaging structure - Google Patents
High-density non-base island chip packaging structure Download PDFInfo
- Publication number
- CN210040170U CN210040170U CN201920838065.1U CN201920838065U CN210040170U CN 210040170 U CN210040170 U CN 210040170U CN 201920838065 U CN201920838065 U CN 201920838065U CN 210040170 U CN210040170 U CN 210040170U
- Authority
- CN
- China
- Prior art keywords
- chip
- lead frame
- base island
- density
- copper
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
The utility model relates to a high density does not have base island chip package structure, including lead frame, chip and plastic envelope material, the lead frame includes a plurality of pins, does not set up the base island, be equipped with the copper post on the chip, still be equipped with the tin cap on the copper post, the chip flip-chip is on the pin of lead frame to weld through copper post, tin cap and pin, the plastic envelope material is used for carrying out the plastic envelope to chip and lead frame. The special lead frame is adopted, only comprises pins and is not provided with a base island, so that the lead frame is very simple in structural design and high in density and can be integrally formed; the chip also adopts a special structure, the chip is connected with the pins through the copper columns, the welding surfaces of the copper columns can be designed to be larger, the cost cannot be obviously increased, the current-carrying capacity is obviously enhanced, the transmission path is short, the conductivity is better, and the yield is high; the product packaging process is simple, and the overall reliability of the product is higher; the single product material use amount is few, and the volume is super little, low thick after the encapsulation, is fit for the installation in less space, and the thermal diffusivity is better.
Description
Technical Field
The utility model relates to a semiconductor package technical field especially relates to a high density does not have base island chip package structure.
Background
In the prior art, as shown in fig. 1 and 2, the most common package structure includes a chip, a lead frame and a plastic package body, the lead frame includes a lead and a base island, the chip is fixed on the base island and then bonded with the lead through a gold wire, and the package structure has a large size and is difficult to further reduce in volume; the gold wires are adopted for connection, so that the size of a welding surface is smaller and is generally only 50x50 micrometers, otherwise, the cost of the gold wires is greatly increased, the occupied welding space is large, the gold wires have large span and length, the transmission distance is long, the current-carrying capacity is poor, and the loss of the welding yield is large; the chip needs to be supported by the base island, the pin is long, the lead frame is complex to process, the base island needs to be punched and formed for the second time, and the lead frame bracket has more copper material waste; the packaging process of the product is complex (dispensing and wire bonding are needed), and the overall reliability of the product is general, so that further improvement is needed.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a small, high, the no base island chip package structure of high density of yield height, with low costs.
The utility model discloses a realize like this: the utility model provides a high density does not have base island chip package structure, includes lead frame, chip and plastic envelope material, the lead frame includes a plurality of pins, does not set up the base island, be equipped with the copper post on the chip, still be equipped with the tin cap on the copper post, the chip flip-chip is on the pin of lead frame to through copper post, tin cap and pin welding, the plastic envelope material is used for carrying out the plastic envelope to chip and lead frame.
Wherein the diameter of the copper column is 90 μm, and the height is 60-70 μm.
The pins are located in the same horizontal plane, and no plastic package material is arranged below the pins.
The thickness of the plastic package material on the top of the chip is 50-100 mu m, and the thickness of the plastic package material on the side face of the chip is 50-100 mu m.
The width of the pins is less than or equal to 100 mu m, and the pitch of the pins is less than or equal to 50 mu m.
And steps are also etched above or below the edges of the pins.
The utility model has the advantages that: high density does not have base island chip package structure has adopted special lead frame, only includes the pin, does not set up the base island, and the chip also adopts special structure, is equipped with the copper post on the chip, still be equipped with the tin cap on the copper post, the chip flip-chip is on the pin of lead frame to through copper post, tin cap and pin welding, the plastic envelope material is used for carrying out the plastic envelope to chip and lead frame. Because the base island is not arranged, the lead frame has very simple structural design, high density and simple process, can be integrally formed, and improves the production efficiency; the chip is connected with the pins through the copper columns, the welding surfaces of the copper columns can be designed to be larger, the cost cannot be obviously increased, the current carrying capacity is obviously enhanced, gold wires are not adopted, the transmission path is short, the conductivity is better, the yield is high, and the problem of gold wire welding yield loss is effectively solved; the product packaging process is simple (no glue dispensing and wire bonding is performed), and the overall reliability of the product is higher; the single product material use amount is few, and the lead frame copper product all reduces with the plastic envelope material by a wide margin, and the volume is super little, low thick after the encapsulation, is fit for more little space installation, and the thermal diffusivity is better.
Drawings
Fig. 1 is a perspective view of a chip package structure in the prior art;
FIG. 2 is a cross-sectional view of a chip package structure of the prior art;
fig. 3 is a schematic perspective view of the high-density non-pad chip package structure of the present invention;
FIG. 4 is a sectional view taken along line A-A of FIG. 3;
FIG. 5 is a sectional view taken along line B-B of FIG. 3;
fig. 6 is a schematic view of a partial structure of the lead frame according to the present invention;
FIG. 7 is a schematic view of the structure of the present invention for bonding a chip to a lead frame;
fig. 8 is a schematic structural diagram of the chip and the lead frame after plastic encapsulation according to the present invention;
FIG. 9 is a schematic diagram of the structure of the whole package structure being cut into individual packaged products;
FIG. 10 is a schematic view of the back side of a product divided into individual packages;
fig. 11 is a cross-sectional view of another embodiment of the high-density non-pad chip package structure of the present invention.
Wherein, 1, lead frame; 11. a pin; 12. a base island; 13. a step; 2. a chip; 21. a copper pillar; 3. plastic packaging material; 4. a tin cap; 5. gold thread; 6. packaging the product; 7. and cutting a channel.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
As an embodiment of high density does not have base island chip package structure, as shown in fig. 3 to 10, including lead frame 1, chip 2 and plastic envelope material 3, lead frame 1 includes a plurality of pins 11, does not set up the base island, be equipped with copper post 21 on the chip 2, still be equipped with tin cap 4 on the copper post 21, 2 flip-chip of chip are on the pin 11 of lead frame to through copper post 21, tin cap 4 and the welding of pin 11, plastic envelope material 3 is used for carrying out the plastic envelope to chip 2 and lead frame 1.
As shown in fig. 9, after the plastic package process is completed, the package structure is cut along the cutting streets 7 to be separated into individual package products 6. As shown in fig. 10, the packaged product 6 has no base island on the back side, only the leads 21.
High density does not have base island chip package structure has adopted special lead frame 1, only includes pin 11, does not set up the base island, and chip 2 is direct to be connected with pin 11, and chip 2 also adopts special structure, is equipped with copper post 21 on chip 2. Because the base island is not arranged, the lead frame 1 has very simple structural design, high density and simple process, can be integrally formed and improves the production efficiency; the chip 2 is connected with the pins 11 through the copper columns 21, the welding surface of the copper columns 21 can be designed to be larger, the cost cannot be obviously increased, the current carrying capacity is obviously enhanced, gold threads are not adopted, the transmission path is short, the conductivity is better, the yield is high, the problem of gold thread welding yield loss is effectively solved, the chip copper column boss welding replaces metal wire welding, the risk of chip multiple bonding chopper impact damage cannot exist, the copper column bosses weld the chips and the pins, the welding ports are few, the overall welding reliability risk of the product is small, and the welding productivity is high by welding the product through the chip copper columns at one time; the product packaging process is simple (no glue dispensing and wire bonding is performed), and the overall reliability of the product is higher; the single product material use amount is few, and the lead frame copper product all reduces with the plastic envelope material by a wide margin, and the volume is super little, low thick after the encapsulation, is fit for more little space installation, and the thermal diffusivity is better. The product has small volume and no pin extends out, the product arrangement density in the whole lead frame is improved by about 10 times, and the output capacity (such as plastic package, rib cutting, electroplating and other processes) of the production process taking the lead frame as a unit is improved.
Although the flip-chip process is adopted, the gaps between the copper column bosses at the bottom of the chip are not required to be filled by dispensing in the traditional flip-chip process, and the plastic package material is directly adopted for integral plastic package and filling, so that the process steps are reduced. In the present embodiment, the diameter of the copper pillar 21 is 90 μm, the height thereof is 60-70 μm, and the height of the tin cap is 40 μm. Compared with the bonding surface size of a gold wire of 50x50 μm, the bonding surface size is greatly increased, so that the current carrying capacity is higher, the height of the copper pillar 21 is lower, and the thickness of the whole packaging structure can be reduced. By taking the packaging form of the DFN as a reference, but distinguishing the DFN, the DFN packaging method has the advantages that a base island is not provided, only pins are provided, and the pins are used as welding points for lower-level assembly while replacing the base island. The size of the plastic packaging material filling particles used by the product has special requirements, and a proper plastic packaging material needs to be selected according to the size of the copper column boss of the chip, otherwise, the gap between the copper column bosses at the bottom of the chip cannot be fully filled, the product quality is abnormal, and the reliability is poor.
In this embodiment, a plurality of pins 11 are located same horizontal plane, just pin 11 below does not set up the plastic envelope material, and 1 welding chip 2 one side of lead frame is by whole plastic envelope promptly, and plastic envelope material 3 covers parcel chip 2 and pin 11 to fill the space between pin and pin, the space between the copper post of chip and copper post, lead frame pin bottom surface expose, further reduce whole packaging structure's thickness. The exposed pins do not extend out, the problem that the edges of the pins have flash is completely solved, and the plastic package mold has universality and can be used for all size products with the same thickness. The pin does not stretch out the plastic-sealed body, only one side exposes, and other are protected by plastic-sealed material parcel, can not have the risk of deformation damage, and the management and control is easy.
In this embodiment, the thickness of the molding compound on the top of the chip 2 is 50-100 μm, and the thickness of the molding compound on the side of the chip 2 is 50-100 μm. The size of the packaged product is only 1.1 times of that of a bare chip, and the realization condition is provided for high integration and small volume of a lower-level assembly module. Compared with the original product, the volume is reduced to 20 percent, the usage amount of single product material is less, the used plastic package material is 20 percent, the used lead frame copper material is 30 percent, and the usage amount of packaging material is less. Compared with the original packaged product, the ultrathin plastic packaging material has greater advantages in product heat dissipation.
In this embodiment, the width of the leads 11 is less than or equal to 100 μm, and the pitch of the leads is less than or equal to 50 μm. The pins are ultra-short, ultra-narrow and high-density, the plastic package production efficiency is improved, the package products contained in the same lead frame size are ten times of the original scheme, the final product forming is completed by cutting with a mechanical knife, the connecting ribs of the lead frame are cut off, and the pins of each product are separated from each other. The cutting separation is carried out through the mechanical grinding wheel, mechanical stamping and rib cutting forming are not needed, the quality problem caused by rib cutting is avoided, and the flatness of the pins is guaranteed.
In this embodiment, a step 13 is further etched below the edge of the pin 11, so that a part of the molding compound is wrapped below the pin 11, and the bonding force between the pin 11 and the molding compound 3 is significantly enhanced.
Of course, as shown in fig. 11, a step 13 is also etched above the edge of the lead 11, and may also function to enhance the bonding force between the lead 11 and the molding compound 3.
The above description is only exemplary of the present invention and should not be taken as limiting the scope of the present invention, as any modifications, equivalents, improvements and the like made within the spirit and principles of the present invention are intended to be included within the scope of the present invention.
Claims (6)
1. The utility model provides a high density does not have base island chip package structure which characterized in that, includes lead frame, chip and plastic envelope material, the lead frame includes a plurality of pins, does not set up the base island, be equipped with the copper post on the chip, still be equipped with the tin cap on the copper post, the chip flip-chip is on the pin of lead frame to through copper post, tin cap and pin welding, the plastic envelope material is used for carrying out the plastic envelope to chip and lead frame.
2. The high-density island-free chip packaging structure of claim 1, wherein the copper pillar has a diameter of 90 μm and a height of 60-70 μm.
3. The high-density non-pad chip package structure according to claim 1, wherein the plurality of leads are located in a same horizontal plane, and no molding compound is disposed under the leads.
4. The high-density island-free chip package structure according to claim 1, wherein the thickness of the top molding compound of the chip is 50-100 μm, and the thickness of the side molding compound of the chip is 50-100 μm.
5. The high-density non-pad chip package structure of claim 1, wherein the lead width is equal to or less than 100 μm and the lead pitch is equal to or less than 50 μm.
6. The high-density island-free chip package structure according to claim 1, wherein a step is further etched above or below the edge of the lead.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920838065.1U CN210040170U (en) | 2019-06-04 | 2019-06-04 | High-density non-base island chip packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920838065.1U CN210040170U (en) | 2019-06-04 | 2019-06-04 | High-density non-base island chip packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN210040170U true CN210040170U (en) | 2020-02-07 |
Family
ID=69346620
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201920838065.1U Active CN210040170U (en) | 2019-06-04 | 2019-06-04 | High-density non-base island chip packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN210040170U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112670209A (en) * | 2020-12-23 | 2021-04-16 | 杰华特微电子（杭州）有限公司 | Heating jig and chip-on-lead packaging method |
| CN116613132A (en) * | 2023-07-19 | 2023-08-18 | 青岛泰睿思微电子有限公司 | Radio frequency chip packaging structure and method |
-
2019
- 2019-06-04 CN CN201920838065.1U patent/CN210040170U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112670209A (en) * | 2020-12-23 | 2021-04-16 | 杰华特微电子（杭州）有限公司 | Heating jig and chip-on-lead packaging method |
| CN112670209B (en) * | 2020-12-23 | 2023-08-29 | 杰华特微电子股份有限公司 | Heating jig and lead chip packaging method |
| CN116613132A (en) * | 2023-07-19 | 2023-08-18 | 青岛泰睿思微电子有限公司 | Radio frequency chip packaging structure and method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6744118B2 (en) | Frame for semiconductor package | |
| US6674154B2 (en) | Lead frame with multiple rows of external terminals | |
| US9087827B2 (en) | Mixed wire semiconductor lead frame package | |
| US6710430B2 (en) | Resin-encapsulated semiconductor device and method for manufacturing the same | |
| US20050218499A1 (en) | Method for manufacturing leadless semiconductor packages | |
| US7247520B2 (en) | Microelectronic component assemblies and microelectronic component lead frame structures | |
| KR0179920B1 (en) | Method of manufacturing chip-size package | |
| CN210040170U (en) | High-density non-base island chip packaging structure | |
| US7943424B1 (en) | Encapsulation method for packaging semiconductor components with external leads | |
| US6703694B2 (en) | Frame for semiconductor package including plural lead frames having thin parts or hollows adjacent the terminal roots | |
| CN208336207U (en) | A kind of biradical island lead frame frame and its SOT33-5L packaging part | |
| CN210245488U (en) | Non-contact type upper and lower chip packaging structure | |
| CN102214635A (en) | Semiconductor package structure and manufacturing method thereof | |
| CN110323198B (en) | Non-contact type upper and lower chip packaging structure and packaging method thereof | |
| CN210429868U (en) | Microminiature SMD TOP LED lead frame | |
| CN204216033U (en) | Lead frame, semiconductor package body | |
| CN103137593A (en) | Lead frame for packaging integrated circuit and corresponding packaging components | |
| CN104600048B (en) | A kind of semiconductor package and method | |
| CN202549841U (en) | Semiconductor module | |
| TW200830496A (en) | Substrate structure for semiconductor package and package method thereof | |
| CN102496610A (en) | Semiconductor packaging part with extension pin and manufacturing method of semiconductor packaging part | |
| CN216250716U (en) | Lead frame structure | |
| JP6143726B2 (en) | Resin-encapsulated semiconductor device, manufacturing method thereof, lead frame | |
| CN220873575U (en) | Lead frame and packaging structure | |
| CN216849921U (en) | Chip high-density packaging lead frame |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |