CN102214635A - Semiconductor package structure and manufacturing method thereof - Google Patents
Semiconductor package structure and manufacturing method thereof Download PDFInfo
- Publication number
- CN102214635A CN102214635A CN2011101402836A CN201110140283A CN102214635A CN 102214635 A CN102214635 A CN 102214635A CN 2011101402836 A CN2011101402836 A CN 2011101402836A CN 201110140283 A CN201110140283 A CN 201110140283A CN 102214635 A CN102214635 A CN 102214635A
- Authority
- CN
- China
- Prior art keywords
- carrier
- metal
- semiconductor package
- coat
- photoresist layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/32257—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
The invention discloses a semiconductor package structure and a manufacturing method thereof. The semiconductor package structure comprises a carrier, a chip, a plurality of bonding wires and a package colloid, wherein the carrier is provided with a chip base and a plurality of pins arranged around the chip base; the chip is arranged on the chip base of the carrier; the bonding wires are arranged between the chip and the pins; the package colloid is used for wrapping the chip, the bonding wires and the pins, and is provided with an upper surface and a lower surface which are opposite to each other, and side surfaces connected with the upper surface and the lower surface; and an angle of more than 0 degree is formed between each of the side surfaces and the normal of the lower surface.
Description
Technical field
The present invention relates to a kind of semiconductor element and preparation method thereof, and particularly relate to a kind of quad flat package structure and preparation method thereof.
Background technology
Manufacture method about the square flat non-pin encapsulation, main flow is for adopting a batch production (batch processing) now, elder generation on nead frame (leadframe), makes these chips be electrically connected to nead frame by many bonding wires a plurality of chip configuration then.Afterwards, come covered section nead frame, these bonding wires and these chips by packing colloid.At last, obtain a plurality of square flat non-pin encapsulation by cutting (punching) or sawing (sawing) singulation said structure.
Though output capacity (throughput) height that the more single mode of batch production is produced, a part of production cost saved, but simultaneously many again singulation technology increases cost on the contrary again.Thereby how generation reduces the demand of singulation technology.
Summary of the invention
The invention provides a kind of semiconductor package and preparation method thereof, its processing step is simple, can reduce production cost and enhances productivity.
The present invention proposes a kind of semiconductor package, and it comprises chip carrier, a plurality of pin around the configuration of this chip carrier, chip, many bonding wires and packing colloid.Each pin has upper inclined portion and the portion that has a down dip, and wherein upper inclined portion is engaged to the tip with the portion of having a down dip.Chip configuration is on chip carrier.Bonding wire is disposed between chip and the pin.Packing colloid has upper surface respect to one another with lower surface and be connected upper surface and the side surface of lower surface, and the upper inclined portion of packing colloid coating chip, bonding wire and pin, and the lower surface of the portion that has a down dip to small part from packing colloid of pin stretches out.Have angle between the normal of side surface and lower surface, and angle is greater than 0 degree.
The present invention proposes a kind of manufacture method of semiconductor package.Carrier is provided.Carrier has each other relative first surface and second surface, is disposed at first coat of metal on the first surface, a plurality of depression and a plurality of by the interior pin portion that is defined between a plurality of recesses.Interior pin portion disposes around depression, and carrier is divided into the linkage unit of a plurality of carrier elements and a plurality of connection carrier unit.Dispose a plurality of chips in the depression of carrier, its chips sees through many bonding wires and is electrically connected to interior pin portion.Form a plurality of packing colloids on carrier, covering chip, bonding wire and interior pin portion, and be filled in depression and recess.Second surface to carrier carries out etch process, with the eating thrown carrier element to being filled in till packing colloid in the opening exposes, so that form a plurality of pins, a plurality of chip carrier and a plurality of opening, eating thrown linkage unit simultaneously, and form a plurality of encapsulating structures independently separately.
Based on above-mentioned,, then see through etch process again and form a plurality of semiconductor packages independently separately because the present invention forms earlier a plurality of packing colloids on carrier.Therefore, carry out singulation step compared to known need through cutting or sawing, the manufacture method of semiconductor package of the present invention can effectively reduce processing step, to reduce production cost and can enhance productivity.
For above-mentioned feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and conjunction with figs. is described in detail below.
Description of drawings
Figure 1A to Fig. 1 K is the generalized section of manufacture method of a kind of semiconductor package of embodiments of the invention.
Fig. 2 is the generalized section of a kind of semiconductor package of embodiments of the invention.
Fig. 3 A to Fig. 3 K is the generalized section of manufacture method of a kind of semiconductor package of another embodiment of the present invention.
Fig. 4 is the generalized section of a kind of semiconductor package of another embodiment of the present invention.
Description of reference numerals
10a, 10b: the first photoresist layer 12a, 22b: the first patterning photoresist layer
20a, 20b: the second photoresist layer 21b: protective layer
22a, 22b: the second patterning photoresist layer
23a, 23a ': the 3rd photoresist layer
24a: the 4th photoresist layer 30: casting mold apparatus
32: jar M: sealing plastics
35a: the first communication channel 35a ': first connector
35b: the second communication channel 35b ': second connector
36: running channel 37: plunger
38: water road junction 39: mold
39a: array die cavity 39a ': array element adhesive body
39b: die cavity 39b ': unit adhesive body
40: dies with epoxy compound 42: mold
44: bed die 44a: die cavity
45a: removable die holder 45b: supporting mould
50: molded structure 52: chip-packaging structure
54: horizontal connector 56: vertical connector
58: blob of viscose 100a, 100b: semiconductor package
110: carrier 110a: metal substrate
111a: first surface 111b: second surface
111c: lateral edges 112: chip carrier
112a: basal surface 113a: depression
113b: recess 113c: opening
114: pin 114a: inner surface
114b: outer surface 114c: upper inclined portion
114d: portion 115 has a down dip: interior pin portion
116,116a: carrier element 118,118a: linkage unit
120: chip 130: bonding wire
140: packing colloid 140a: the running channel cull
140b: inferior running channel cull 142: upper surface
144: lower surface 146: side surface
150a, 150b: first coat of metal 160a, 160b: second coat of metal
170: carrier 172: holding tank
175,178: fixed mount 180: adhesive tape
α: angle N: normal
P: most advanced and sophisticated S: enclosure space
Embodiment
Figure 1A to Fig. 1 K is the generalized section of manufacture method of a kind of semiconductor package of embodiments of the invention.Manufacture method according to the semiconductor package of present embodiment please refer to Figure 1A, and metal substrate 110a is provided, and wherein metal substrate 110a has each other relative first surface 111a and second surface 111b.Then, on the first surface 111a of metal substrate 110a, be coated with the first photoresist layer 10a, and go up the coating second photoresist layer 20a in the second surface 111b of metal substrate 110a.In this, the first photoresist layer 10a and the second photoresist layer 20a be first surface 111a and the second surface 111b of comprehensive covering metal substrate 110a respectively.
Then, please refer to Figure 1B, simultaneously the first photoresist layer 10a and the second photoresist layer 20a are carried out step of exposure and development step, go up the formation first patterning photoresist layer 12a with first surface 111a, on the second surface 111b of metal substrate 110a, form the second patterning photoresist layer 22a in metal substrate 110a.In this, the first patterning photoresist layer 12a exposes part first surface 111a, and the second patterning photoresist layer 22a exposes part second surface 111b.
Then, please refer to Fig. 1 C, form first coat of metal 150a on the part first surface 111a that the first patterning photoresist layer 12a exposed, and form second coat of metal 160a on the part second surface 111b that the second patterning photoresist layer 22a exposed.In the present embodiment, the material of the material of first coat of metal 150a and second coat of metal 160a can be identical or different in fact, for example is gold, silver, tin, chromium, nickel/golden composite bed or nickel/palladium/golden composite bed.
Then, please refer to Fig. 1 D, remove the first patterning photoresist layer 12a and the second patterning photoresist layer 22a, to expose part first surface 111a and part second surface 111b.
Then, please refer to Fig. 1 E, form the 3rd photoresist layer 23a on the first surface 111a of metal substrate 110a, and form the 4th photoresist layer 24a on the second surface 111b of metal substrate 110a.Then, and be etching mask, etch partially metal substrate 110a, to form a plurality of depression 113a and a plurality of recess 113b on the part first surface 111a that is not covered at metal substrate 110a by the 3rd photoresist layer 23a with the 3rd photoresist layer 23a.
Then, please refer to Fig. 1 F, remove the 3rd photoresist layer 23a and the 4th photoresist layer 24a, to expose first coat of metal 150a and second coat of metal 160a.In this, a plurality of interior pin portion 115 and a plurality of chip carrier 112 that define between these recesses 113b, wherein these depressions 113a is disposed at these chip carrier 112 central authorities, and pin portions 115 dispose around these chip carriers 112 in these.So far, formed carrier 110.In the present embodiment, carrier 110 has each other relative first surface 111a and second surface 111b, be disposed on the first surface 111a first coat of metal 150a, these depressions 113a and by defined between these recesses 113b these in pin portion 115, wherein pin portions 115 dispose around these depressions 113a in these.In addition, carrier 110 can be divided into the linkage unit 118 of a plurality of carrier elements 116 (only schematically illustrating two carrier elements 116 among Fig. 1 F) and these carrier elements 116 of a plurality of connection.
Then, please refer to Fig. 1 G, dispose a plurality of chips 120 in these depressions 113a of carrier 110, wherein these chips 120 see through many bonding wires 130 and are electrically connected to pin portion 115 in these.
Then, please refer to Fig. 1 H, form a plurality of packing colloids 140 on carrier 110, with cover these chips 120, these bonding wires 130 with these in pin portion 115, and be filled in these depressions 113a and these recesses 113b.At this moment, the side surface 146 that each packing colloid 140 has upper surface 142 respect to one another and lower surface 144 and is connected upper surface 142 and lower surface 144 wherein have angle α between the normal N of side surface 146 and lower surface 144, and angle α spends greater than 0.Preferably, angle α is between 5 degree are to 45.In the present embodiment, forming the method for these packing colloids 140 on carrier 110 comprises and carries out molding process (molding process).
Fig. 1 H (a) illustrates schematic diagram into a kind of formation method of packing colloid to Fig. 1 H (c).Please refer to Fig. 1 H (a), in the embodiment of side running channel, the step that forms packing colloid 140 can comprise: casting mold apparatus 30 is provided earlier, and it comprises a plurality of jars 32 and two carriers 110 that are disposed at jar 32 both sides respectively, and these chip 120 arrayed are on carrier 110.At least one running channel 36 extends to the lateral edges 111c of carrier 110 respectively from the both sides of jar 32.Be connected with mold 39 on the carrier 110 by watering road junction 38.By the pressure that plunger 37 extrusion is produced, sealing plastics M flows to via running channel 36 from jar 32 and waters in the array die cavity 39a that road junction 38 enters mold 39.Casting mold apparatus 30 has the first communication channel 35a each array die cavity 39a of this mold 39 is connected in the lateral edges 111c of carrier 110 before watering road junction 38, and have the second communication channel 35b in each array die cavity 39a and be connected between the die cavity 39b, make in mold 39 each die cavity 39b sealing plastics M must via the second communication channel 35b interconnect and each array die cavity 39a between must interconnect via the first communication channel 35a.
Afterwards, please also refer to Fig. 1 H (b) and Fig. 1 H (c), wherein Fig. 1 H (c) illustrates along the generalized section of the line II-II of Fig. 1 H (b).Then, after molded semi-finished product are after mold 39 takes out, the outside of each array element adhesive body 39a ' on the carrier 110 is interconnected by the first connector 35a ', and the unit adhesive body 39b ' among each array element adhesive body 39a ' interconnects by a plurality of second connector 35b ', thereby makes each unit adhesive body 39b ' (being the packing colloid 140 of Fig. 1 H) form the array structure of one.Then, thimble (not illustrating) be can see through and these first connectors 35a ' (please refer to Fig. 1 H (b)) and these second connectors 35b ' (please refer to Fig. 1 H (c)) removed.
Fig. 1 H (d) illustrates and is the structural representation of another kind of packing colloid after forming.In the embodiment of vertical running channel, please refer to Fig. 1 H (f), the molded structure 50 after packing colloid forms comprises the chip-packaging structure of arranging with array way 52.In Fig. 1 H (h),, only show the packing colloid part (being the packing colloid 140 of Fig. 1 H) that coats carrier and chip in order to clearly demonstrate.In addition, molded structure 50 also comprises horizontal connector 54, vertical connector 56 and blob of viscose 58.In detail, formed horizontal connector 54 after the packing colloid material cured in the runner of level; Formed vertical connector 56 after the packing colloid material cured in the vertical cast gate; Formed blob of viscose 58 after the packing colloid material cured in the material cave.Horizontal connector 54 is connected with blob of viscose 58.In addition, horizontal connector 54 is connected with chip-packaging structure 52 via vertical connector 56.Then, can more vertical connector 56 be separated with chip-packaging structure 52.
Fig. 1 H (e) illustrates schematic diagram into the formation method of another kind of packing colloid to Fig. 1 H (f).In the embodiment of pressing mold (compression mold), please also refer to Fig. 1 H (e) and Fig. 1 H (f), the method that forms packing colloid 140 also can provide dies with epoxy compound 40, and it is suitable for the chip 120 that is installed on the carrier 110 is carried out sealing.Dies with epoxy compound 40 comprises mold 42 and bed die 44.Specifically, mold 42 is in order to settle carrier 110.Bed die 44 is disposed at the below of mold 42, and bed die 44 has die cavity 44a, and wherein die cavity 44a can hold sealing plastics M.Particularly, in the present embodiment, bed die 44 also can comprise removable die holder 45a and the supporting mould 45b that connects removable die holder 45a periphery, and wherein supporting mould 45b and removable die holder 45a form die cavity 44a.Then, when mold 42 during with bed die 44 relative shifting near, the die cavity 44a of carrier 110 and bed die 44 constitutes enclosure space S, shown in Fig. 1 H (h).At this moment, the sealing plastics M in the die cavity 44a coats the chip 120 on the carrier 110 that is positioned at mold 42, and finishes the making of the packing colloid 140 of Fig. 1 H.
After packaging technology was finished, the both sides that can utilize carrier and fixed mount to be held on semiconductor package were carried out subsequent technique again.Fig. 1 I (a) illustrates the vertical view into carrier and fixed mount clamping semiconductor package, and Fig. 1 I is the generalized section along the line III-III of Fig. 1 I (a).Then, please also refer to Fig. 1 I and Fig. 1 I (a), carrier (tray) 170 and fixed mount 175 are provided, wherein carrier 170 has a plurality of holding tanks 172, and these packing colloid 140 correspondences are arranged in these holding tanks 172, and expose the second surface 111b of carrier 110.Fixed mount 175 is disposed on the second surface 111b of carrier 110, wherein carrier 170 and fixed mount 175 with carrier 110 and on these packing colloids 140 be held on wherein so that carrier 110 and on these packing colloids 140 be fixed between carrier 170 and the fixed mount 175.Afterwards, second surface 111b to carrier 110 carries out etch process, by second coat of metal 160a as etching mask, these carrier elements 116 of eating thrown are to being filled in till these packing colloids 140 in these recesses 113b expose, so that form a plurality of pins 114, these chip carriers 112 that separate with these pins 114 and a plurality of opening 113c (shown in Fig. 1 J).And, at this etch process, these linkage units 118 of eating thrown simultaneously, to form a plurality of encapsulating structures independently separately, meaning is semiconductor package 100a.At present embodiment, because of will carrying out etch process to the second surface 111b of carrier 110, so the cross-sectional width of this fixed mount 175 should be less than the width of linkage unit 118, so, just can be in etch process these linkage units 118 of eating thrown in the lump.What deserves to be mentioned is that the present invention does not limit the form of carrier 170, have these holding tanks 172 though the carrier 170 that reaches mentioned herein is embodied as, and these packing colloid 140 correspondences are arranged in these holding tanks 172.But in the embodiment that other do not illustrate, carrier also can only have single holding tank (for example being brilliant boat (boat)), and these packing colloids are arranged in this holding tank.Moreover in the embodiment that another does not illustrate, packing colloid can see through viscose glue, for example is that two-sided tape is attached on the planes carry dish, and exposes the second surface 111b of carrier 110; In the embodiment that another does not illustrate, also can not provide carrier, and only provide adhesive tape on these packing colloids, and these packing colloids are attached on this adhesive tape again.Must explanation be that above-mentioned have the carrier 170 of a plurality of holding tanks 172, the carrier with single holding tank, planes carry dish or adhesive tape all to be used for collecting the follow-up formed encapsulating structure behind the etch process that finishes.Therefore, known other can reach and collect on an equal basis that the structural design of formed encapsulating structure effect all belongs to the adoptable technical scheme of the present invention behind the etch process, do not break away from the scope of institute of the present invention desire protection.
Then, please refer to Fig. 1 J and Fig. 1 J (a), Fig. 1 J (a) illustrates the vertical view into carrier and fixed mount clamping semiconductor package, and Fig. 1 J is the generalized section along the line IV-IV of Fig. 1 J (a).After etching is made, remove fixed mount 175 and provide fixed mount 178 on the second surface 111b of carrier 110, wherein, the lower surface 144 that fixed mount 178 sees through these packing colloids 140 of contact is fixed in semiconductor package 100a on the carrier 170, and provide support power, afterwards, carry out water cutter technology (water-jet process), so that the outer surface 114b of the lateral margin of second coat of metal 160b and these pins 114 trims in fact, shown in Fig. 1 K.In the present embodiment, each pin 114 has inner surface 114a respect to one another and outer surface 114b, configuration are adjacent to the upper inclined portion 114c of inner surface 114a and the 114d of the portion that has a down dip of configuration adjacent outer surface 114b, wherein upper inclined portion 114c is engaged to most advanced and sophisticated P with the 114d of portion that has a down dip, and these packing colloids 140 cover these upper inclined portion 114c of these pins 114 in fact, and the lower surface 144 of the 114d of the portion that has a down dip to small part from these packing colloids 140 of these pins 114 stretches out.At last, remove carrier 170 or adhesive tape (not illustrating), and finish the making of semiconductor package 100a.
Fig. 2 is the generalized section of a kind of semiconductor package of embodiments of the invention.Please refer to Fig. 2, the semiconductor package 100a of present embodiment comprises carrier 110, chip 120, these bonding wires 130, packing colloid 140, first coat of metal 150a and second coat of metal 160a.Carrier 110 has chip carrier 112 and these pins 114 around chip carrier 112 configurations.Chip 120 is disposed on the chip carrier 112 of carrier 110.These bonding wires 130 are disposed between chip 120 and these pins 114, and chip 120 sees through these bonding wires 130 and these pins 114 electric connections.Each pin 114 has inner surface 114a respect to one another and outer surface 114b, configuration are adjacent to the upper inclined portion 114c of inner surface 114a and the 114d of the portion that has a down dip of configuration adjacent outer surface 114b, and wherein upper inclined portion 114c is engaged to most advanced and sophisticated P with the 114d of portion that has a down dip.Packing colloid 140 coats these upper inclined portion 114c, chip 120 and these bonding wires 130 of these pins 114 in fact, and the lower surface 144 of the 114d of the portion that has a down dip to small part from these packing colloids 140 of these pins 114 stretches out.The side surface 146 that packing colloid 140 has upper surface 142 respect to one another and lower surface 144 and is connected upper surface 142 and lower surface 144 wherein have angle α between the normal N of side surface 146 and lower surface 144, and angle α spends greater than 0.Preferably, angle α is between 5 degree are to 45.First coat of metal 150a is disposed on these inner surfaces 114a of these pins 114, and exposed portions serve inner surface 114a, and second coat of metal 160a is disposed on the basal surface 112a of these outer surfaces 114b of these pins 114 and chip carrier 112, and cover all basal surface 112a, wherein the material of the material of first coat of metal 150a and second coat of metal 160a can be identical or different in fact, for example is gold, silver, tin, chromium, nickel/golden composite bed or nickel/palladium/golden composite bed.
Because present embodiment is to form earlier these packing colloids 140 on carrier 110, these linkage units 118 that then see through eating thrown carrier 110 form these semiconductor package 100a independently separately.Carry out singulation step compared to known need through cutting or sawing, the manufacture method of the semiconductor package 100a of present embodiment need not to cut or singulation step is carried out in sawing, can effectively reduce processing step, to reduce production cost and can enhance productivity.
In this mandatory declaration is that following embodiment continues to use the element numbers and the partial content of previous embodiment, wherein adopts identical label to represent identical or approximate element, and has omitted the explanation of constructed content.Explanation about clipped can be with reference to previous embodiment, and following embodiment no longer repeats to give unnecessary details.
Fig. 3 A to Fig. 3 K is the generalized section of manufacture method of a kind of semiconductor package of another embodiment of the present invention.Manufacture method according to the semiconductor package of present embodiment at first, please refer to Fig. 3 A, and metal substrate 110a is provided, and wherein metal substrate 110a has each other relative first surface 111a and second surface 111b.Then, on the first surface 111a of metal substrate 110a, be coated with the first photoresist layer 10b, and go up the coating second photoresist layer 20b in the second surface 111b of metal substrate 110a.In this, the first photoresist layer 10b and the second photoresist layer 20b be first surface 111a and the second surface 111b of comprehensive covering metal substrate 110a respectively.
Then, please refer to Fig. 3 B, simultaneously the first photoresist layer 10b and the second photoresist layer 20b are carried out step of exposure and development step, go up the formation first patterning photoresist layer 12b with first surface 111a, on the second surface 111b of metal substrate 110a, form the second patterning photoresist layer 22b in metal substrate 110a.In this, the first patterning photoresist layer 12b exposes part first surface 111a, and the second patterning photoresist layer 22b exposes part second surface 111b.Afterwards, the second patterning photoresist layer 22b and expose the part second surface 111b on protective mulch 21b.
Then, please refer to Fig. 3 C, form first coat of metal 150b on the part first surface 111a that the first patterning photoresist layer 12b exposed, wherein first coat of metal 150b for example is nickel/palladium/golden composite bed.
Then, please refer to Fig. 3 D, remove the first patterning photoresist layer 12b, to expose part first surface 111a.
Then, please refer to Fig. 3 E, form the 3rd photoresist layer 23a ' on the first surface 111a of metal substrate 110a, and be etching mask with the 3rd photoresist layer 23a ', etch partially metal substrate 110a, go up with the part first surface 111a that is not covered at metal substrate 110a and form a plurality of depression 113a and a plurality of recess 113b by the 3rd photoresist layer 23a '.
Then, please refer to Fig. 3 F, remove the 3rd photoresist layer 23a ', to expose first coat of metal 150b.In this, the a plurality of interior pin portion 115 that defines between these recesses 113b, wherein pin portions 115 are around these depressions 113a configuration in these, and this moment, metal substrate 110a can divide into the linkage unit 118a of a plurality of base board unit 116a and a plurality of connection base board unit 116a.
Then, please refer to Fig. 3 G, dispose a plurality of chips 120 in these depressions 113a of metal substrate 110a, wherein these chips 120 see through many bonding wires 130 and are electrically connected to pin portion 115 in these.
Then, please refer to Fig. 3 H, use forms a plurality of packing colloids 140 on metal substrate 110a with the molding process of aforementioned embodiment, with cover these chips 120, these bonding wires 130 with these in pin portion 115, and be filled in these depressions 113a and these recesses 113b.At this moment, the side surface 146 that each packing colloid 140 has upper surface 142 respect to one another and lower surface 144 and is connected upper surface 142 and lower surface 144, wherein has angle α between the normal N of side surface 146 and lower surface 144, and angle α is greater than 0 degree, preferably, angle α is between 5 degree are to 45.
Then, please refer to Fig. 3 I, remove protective layer 21b, with the part second surface 111b and the second patterning photoresist layer 22b that exposes metal substrate 110a.
Then, please refer to Fig. 3 J, form second coat of metal 160b on the part second surface 111b that the second patterning photoresist layer 22b exposed in the mode of electroplating, wherein second coat of metal 160b for example is a solder layer, and its material can comprise tin or sn-ag alloy.What deserves to be mentioned is, present embodiment can be controlled the thickness of second coat of metal 160b by the thickness of the second patterning photoresist layer 22b, thereby in the application of follow-up and external circuit (not illustrating), can directly be connected on the external circuit through second coat of metal 160b.In present embodiment, the thickness of second coat of metal 160b can be 50um to 150um, is preferably 80um to 120um.
Afterwards, please refer to Fig. 3 K, remove the second patterning photoresist layer 22b, to expose the part second surface 111b of metal substrate 110a, and the second surface 111b of the metal substrate 110a that exposed carried out etch process, with eating thrown base board unit 116a to being filled in till these packing colloids 140 in these recesses 113b expose, so that form a plurality of pins 114, a plurality of chip carrier 112 and a plurality of opening 113c.And, at this etch process, while eating thrown linkage unit 118a, to form the encapsulating structure of a plurality of each self-separation, meaning is semiconductor package 100b.In the present embodiment, each pin 114 has inner surface 114a respect to one another and outer surface 114b, configuration are adjacent to the upper inclined portion 114c of inner surface 114a and the 114d of the portion that has a down dip of configuration adjacent outer surface 114b, wherein upper inclined portion 114c is engaged to most advanced and sophisticated P with the 114d of portion that has a down dip, and these packing colloids 140 cover these upper inclined portion 114c of these pins 114 in fact, and the lower surface 144 of the 114d of the portion that has a down dip to small part from these packing colloids 140 of these pins 114 stretches out.So far, finished the making of semiconductor package 100b.
Fig. 4 is the generalized section of a kind of semiconductor package of another embodiment of the present invention.Please refer to Fig. 4, the semiconductor package 100b of present embodiment comprises carrier 110, chip 120, these bonding wires 130, packing colloid 140, first coat of metal 150b and second coat of metal 160b.Carrier 110 has chip carrier 112 and these pins 114 around chip carrier 112 configurations.Chip 120 is disposed on the chip carrier 112 of carrier 110.These bonding wires 130 are disposed between chip 120 and these pins 114, and chip 120 sees through these bonding wires 130 and these pins 114 electric connections.Each pin 114 has inner surface 114a respect to one another and outer surface 114b, configuration are adjacent to the upper inclined portion 114c of inner surface 114a and the 114d of the portion that has a down dip of configuration adjacent outer surface 114b, and wherein upper inclined portion 114c is engaged to most advanced and sophisticated P with the 114d of portion that has a down dip.Packing colloid 140 coats these upper inclined portion 114c, chip 120 and these bonding wires 130 of these pins 114 in fact, and the lower surface 144 of the 114d of the portion that has a down dip to small part from these packing colloids 140 of these pins 114 stretches out.The side surface 146 that packing colloid 140 has upper surface 142 respect to one another and lower surface 144 and is connected upper surface 142 and lower surface 144, wherein has angle α between the normal N of side surface 146 and lower surface 144, and angle α is greater than 0 degree, and preferably, angle α is between 5 degree are to 45.First coat of metal 150b is disposed on these inner surfaces 114a of these pins 114, and second coat of metal 160b is disposed on the basal surface 112a of these outer surfaces 114b of these pins 114 and chip carrier 112, wherein first coat of metal 150b for example is gold, silver, tin, chromium, nickel/golden composite bed or nickel/palladium/golden composite bed, and second coat of metal 160a for example is a solder layer, and its material can comprise tin.
In present embodiment, be to form these packing colloids 140 earlier on carrier 110, form second coat of metal 160b afterwards again and carry out etch process.Yet, in other embodiments, also can form second coat of metal 160b earlier, and after on the carrier 110, carry out etch process again in forming these packing colloids 140.
In addition, because second coat of metal 160b of present embodiment is a solder layer, therefore in the application of follow-up and external circuit (not illustrating), present embodiment need not be coated with solder cream again, can be connected on the external circuit through second coat of metal 160b.Thus, can effectively reduce the processing step of subsequent applications, to reduce production cost and can enhance productivity.
In sum, because the present invention forms earlier a plurality of packing colloids on carrier, the linkage unit (or linkage unit of metal substrate) that then sees through the eating thrown carrier forms a plurality of semiconductor packages independently separately.Therefore, carry out singulation step compared to known need through cutting or sawing, the manufacture method of semiconductor package of the present invention can effectively reduce processing step, to reduce production cost and can enhance productivity.Moreover because second coat of metal can be solder layer, therefore in the application of follow-up and external circuit (not illustrating), semiconductor package of the present invention can directly see through second coat of metal and be connected on the external circuit, can reduce journey step and production cost.
Though the present invention discloses as above with embodiment; right its is not in order to qualification the present invention, those of ordinary skill in any affiliated technical field, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention defines and is as the criterion when looking claim.
Claims (15)
1. semiconductor package comprises:
Chip carrier;
A plurality of pins around this chip carrier configuration, wherein each pin has upper inclined portion and the portion that has a down dip, and this upper inclined portion and this portion of having a down dip are engaged to the tip;
Chip is disposed on this chip carrier;
Many bonding wires are disposed between this chip and this a plurality of pins; And
Packing colloid, the side surface that has upper surface respect to one another and lower surface and be connected this upper surface and this lower surface, this packing colloid coats these a plurality of upper inclined portion of this chip, these a plurality of bonding wires and these a plurality of pins, and a plurality of portions that have a down dip of this of these a plurality of pins this lower surface to small part from this packing colloid stretches out, wherein have angle between the normal of this side surface and this lower surface, and this angle is greater than 0 degree.
2. semiconductor package as claimed in claim 1, wherein respectively this pin has inner surface respect to one another and outer surface, and this upper inclined portion configuration is adjacent to this inner surface, and contiguous this outer surface of this portion's of having a down dip configuration.
3. semiconductor package as claimed in claim 2 also comprises:
First coat of metal is disposed on these a plurality of inner surfaces of these a plurality of pins; And
Second coat of metal is disposed on the basal surface of this a plurality of outer surfaces of these a plurality of pins and this chip carrier.
4. semiconductor package as claimed in claim 3, wherein this first coat of metal is nickel/palladium/golden composite bed.
5. semiconductor package as claimed in claim 3, wherein this second coat of metal is a solder layer.
6. semiconductor package as claimed in claim 1, wherein this angle is between 5 degree are to 45.
7. the manufacture method of a semiconductor package comprises:
Carrier is provided, this carrier has each other relative first surface and second surface, is disposed at first coat of metal on this first surface, a plurality of depression and by defined between a plurality of recesses a plurality of in pin portion, wherein these a plurality of interior pin portions dispose around these a plurality of depressions, and this carrier is divided into the linkage unit of a plurality of carrier elements and a plurality of these a plurality of carrier elements of connection;
Dispose a plurality of chips in these a plurality of depressions of this carrier, wherein these a plurality of chips see through many bonding wires and are electrically connected to this a plurality of interior pin portions;
Form a plurality of packing colloids on this carrier,, and be filled in these a plurality of depressions and this a plurality of recesses with these a plurality of chips of covering, these a plurality of bonding wires and this a plurality of interior pin portions; And
This second surface to this carrier carries out etch process, with these a plurality of carrier elements of eating thrown to being filled in till a plurality of packing colloids of in these a plurality of recesses this expose, so that form a plurality of pins, a plurality of chip carrier and a plurality of opening, these a plurality of linkage units of eating thrown simultaneously, and form a plurality of encapsulating structures independently separately.
8. the manufacture method of semiconductor package as claimed in claim 7 also comprises:
This second surface of this carrier is carried out providing carrier before this etch process, and this carrier has at least one holding tank, and wherein these a plurality of packing colloid correspondences are arranged in this holding tank, and expose this second surface of this carrier.
9. the manufacture method of semiconductor package as claimed in claim 8, wherein this at least one holding tank is a plurality of holding tanks, these a plurality of packing colloids correspondence respectively are arranged in this a plurality of holding tanks.
10. the manufacture method of semiconductor package as claimed in claim 7 also comprises:
This second surface of this carrier is carried out providing carrier and viscose glue before this etch process, and wherein this carrier has the plane, and these a plurality of packing colloids see through this viscose glue and are pasted on this plane, and expose this second surface of this carrier.
11. the manufacture method of semiconductor package as claimed in claim 7 also comprises:
Metal substrate is provided, and this metal substrate has this first surface and this second surface;
Be coated with the first photoresist layer and the second photoresist layer respectively on this first surface and this second surface of this metal substrate;
This first photoresist and this second photoresist are carried out step of exposure and development step layer by layer, on this first surface of this metal substrate and this second surface, to form the first patterning photoresist layer and the second patterning photoresist layer, wherein this first patterning photoresist layer exposes this first surface of part, and this second patterning photoresist layer exposes this second surface of part;
Form first coat of metal on this first surface of part that this first patterning photoresist layer is exposed;
Form second coat of metal on this second surface of part that this second patterning photoresist layer is exposed;
Remove this first patterning photoresist layer;
This first surface of part of this metal substrate outside this first coat of metal of etching is to form these a plurality of depressions and these a plurality of openings; And
Remove this second patterning photoresist layer.
12. the manufacture method of semiconductor package as claimed in claim 11, wherein forming this second coat of metal is before this second surface to this carrier carries out this etch process on this second surface of part that this second patterning photoresist layer is exposed.
13. the manufacture method of semiconductor package as claimed in claim 12, wherein this second coat of metal is a solder layer.
14. the manufacture method of semiconductor package as claimed in claim 11, wherein form this second coat of metal on this second surface of part that this second patterning photoresist layer is exposed be providing these a plurality of chips in these a plurality of depressions of this carrier before, and carry out this etch process by this second coat of metal as etching mask, and form these a plurality of pins and this a plurality of chip carriers.
15. the manufacture method of semiconductor package as claimed in claim 14, wherein the material of this second coat of metal is identical with the material of this first coat of metal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011101402836A CN102214635A (en) | 2011-05-27 | 2011-05-27 | Semiconductor package structure and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011101402836A CN102214635A (en) | 2011-05-27 | 2011-05-27 | Semiconductor package structure and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102214635A true CN102214635A (en) | 2011-10-12 |
Family
ID=44745882
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011101402836A Pending CN102214635A (en) | 2011-05-27 | 2011-05-27 | Semiconductor package structure and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102214635A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102496608A (en) * | 2011-12-23 | 2012-06-13 | 日月光半导体制造股份有限公司 | Semiconductor packaging possessing clamp part and manufacturing method thereof |
| CN102738018A (en) * | 2012-06-13 | 2012-10-17 | 华天科技（西安）有限公司 | Framework carrier pore opening and solder ball film sticking based AAQFN (quad flat no-lead) product secondary plastic packaging manufacturing technology |
| CN107301956A (en) * | 2016-08-29 | 2017-10-27 | 上海兆芯集成电路有限公司 | Chip Packaging Process |
| CN109585575A (en) * | 2018-11-28 | 2019-04-05 | 深圳市兴森快捷电路科技股份有限公司 | A kind of photoelectric circuit packaging system based on ceramic carrier |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5847458A (en) * | 1996-05-21 | 1998-12-08 | Shinko Electric Industries Co., Ltd. | Semiconductor package and device having heads coupled with insulating material |
| US6762118B2 (en) * | 2000-10-10 | 2004-07-13 | Walsin Advanced Electronics Ltd. | Package having array of metal pegs linked by printed circuit lines |
| CN101540309A (en) * | 2008-03-14 | 2009-09-23 | 日月光半导体制造股份有限公司 | Semiconductor chip package and manufacturing methods thereof |
| CN101656238A (en) * | 2008-08-21 | 2010-02-24 | 日月光半导体制造股份有限公司 | Advanced quad flat non-leaded package structure and manufacturing method thereof |
-
2011
- 2011-05-27 CN CN2011101402836A patent/CN102214635A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5847458A (en) * | 1996-05-21 | 1998-12-08 | Shinko Electric Industries Co., Ltd. | Semiconductor package and device having heads coupled with insulating material |
| US6762118B2 (en) * | 2000-10-10 | 2004-07-13 | Walsin Advanced Electronics Ltd. | Package having array of metal pegs linked by printed circuit lines |
| CN101540309A (en) * | 2008-03-14 | 2009-09-23 | 日月光半导体制造股份有限公司 | Semiconductor chip package and manufacturing methods thereof |
| CN101656238A (en) * | 2008-08-21 | 2010-02-24 | 日月光半导体制造股份有限公司 | Advanced quad flat non-leaded package structure and manufacturing method thereof |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102496608A (en) * | 2011-12-23 | 2012-06-13 | 日月光半导体制造股份有限公司 | Semiconductor packaging possessing clamp part and manufacturing method thereof |
| CN102738018A (en) * | 2012-06-13 | 2012-10-17 | 华天科技（西安）有限公司 | Framework carrier pore opening and solder ball film sticking based AAQFN (quad flat no-lead) product secondary plastic packaging manufacturing technology |
| CN107301956A (en) * | 2016-08-29 | 2017-10-27 | 上海兆芯集成电路有限公司 | Chip Packaging Process |
| US11081371B2 (en) | 2016-08-29 | 2021-08-03 | Via Alliance Semiconductor Co., Ltd. | Chip package process |
| CN109585575A (en) * | 2018-11-28 | 2019-04-05 | 深圳市兴森快捷电路科技股份有限公司 | A kind of photoelectric circuit packaging system based on ceramic carrier |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102931161B (en) | Semiconductor package assembly and a manufacturing method thereof | |
| CN101656234B (en) | Advanced quad flat non-leaded package structure and manufacturing method thereof | |
| CN101859734A (en) | The manufacture method of lead frame and manufacture method thereof and encapsulating structure | |
| US20170294560A1 (en) | Semiconductor device package and a method of manufacturing the same | |
| CN102214631A (en) | Lead frame for semiconductor device | |
| CN103456645A (en) | Packaging-after etching three-dimensional system-on-chip upright stacking packaging structure and technology method | |
| CN106128965A (en) | A kind of manufacture method of device without substrate package | |
| CN106328639A (en) | LED encapsulating structure and preparing method thereof | |
| CN102214635A (en) | Semiconductor package structure and manufacturing method thereof | |
| US9659842B2 (en) | Methods of fabricating QFN semiconductor package and metal plate | |
| CN103208431A (en) | Semiconductor packaging structure and manufacturing method thereof | |
| CN102184908A (en) | Advanced square flat pin-free encapsulating structure and manufacturing method thereof | |
| CN102522394A (en) | On-chip chip package and production method thereof | |
| CN102263077A (en) | Double flat carrier-free pin-free IC chip packaging part | |
| CN101661918B (en) | Quad flat non-leaded chip package | |
| US8299587B2 (en) | Lead frame package structure for side-by-side disposed chips | |
| CN202633291U (en) | Chip-on-chip packaging structure | |
| JP6034078B2 (en) | Premold lead frame manufacturing method and semiconductor device manufacturing method | |
| US8535988B2 (en) | Large panel leadframe | |
| CN109037183A (en) | A kind of semiconductor chip packaging array and semiconductor chip packaging device | |
| CN103824820B (en) | Leadframe area array package technology | |
| CN102201348A (en) | Array cutting type quad flat non-leaded packaging method | |
| KR20140124251A (en) | Method for manufacturing multi-row qfn semiconductor package | |
| CN203242616U (en) | No-lead leadframe bar for semiconductor packaging | |
| JP2004063680A (en) | Method of manufacturing chip array type ball grid array package for substrate on chip |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20111012 |