CN106128965A - A kind of manufacture method of device without substrate package - Google Patents
A kind of manufacture method of device without substrate package Download PDFInfo
- Publication number
- CN106128965A CN106128965A CN201610595226.XA CN201610595226A CN106128965A CN 106128965 A CN106128965 A CN 106128965A CN 201610595226 A CN201610595226 A CN 201610595226A CN 106128965 A CN106128965 A CN 106128965A
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- Prior art keywords
- mucosa
- interim
- chip
- manufacture method
- substrate package
- Prior art date
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip
Abstract
The invention discloses the manufacture method of a kind of device without substrate package, comprise the steps: 1) accessory plate is provided；2) interim mucosa is formed；3) metal level is made；4) patterned metal layer reserved chip attachment room；5) pasting chip: pasting chip on the chip attachment room that step 4) is reserved, chip is close to interim mucosa upper surface；6) electrical interconnection: use the method for wire bonding to realize the electrical interconnection of chip and line layer；7) make molded packages body: use mould plastic package process, form the packaging body of mold sealing material；8) prepare without substrate package device: at a temperature of the adhesion failure of interim mucosa, remove interim mucosa and corresponding accessory plate, packaging body is dried and cools down, obtain without substrate package device.This manufacture method, manufacturing process is simple, with low cost, and yield rate is high, be suitable for batch production.
Description
Technical field
The present invention relates to the manufacturing technology field of packaging, particularly relate to the making side of a kind of device without substrate package
Method.
Technical background
Along with the development trend that microelectronic product is compact, high density and thin encapsulation become encapsulation industrial research heat
Point.In order to the requirement of high-density packages, commonly used packing forms is BGA Package (BGA), uses and prints electricity
Road plate (PCB) multilayer wiring technique, it is possible to realize the high-density packages requirement of solder joint multiple rows ofization array.But due to PCB material
The thermal coefficient of expansion of the materials such as material and chip Heraeus, chip does not mates, it is easy to excessive warpage occurs, affects properties of product；
And in order to realize multiple rows ofization array pin, needing to carry out in the pcb multilayer wiring, substrate manufacture technique is relative complex；Though
So substrate manufacture technical maturity, but high expensive.Additionally, use lead frame as the quad flat non-leaded chip package of support plate
(QFN) small size and high-density packages can the most also be realized, but owing to mostly lead frame manufacture is to pass through punching press
Or etching, owing to technique limits, framework wiring width is limited, connects up relatively complicated, is difficulty with pin multiple rows ofization array
High-density packages.Visible, in order to meet slimming encapsulation requirement, no matter be PCB substrate, or the thickness of lead frame all by
Reduce as far as possible, but owing to technique limits, be difficult to meet microelectronic component slimming encapsulation requirement.Accordingly, it would be desirable to exploitation one
New packaging method, to meet slimming and the high-density packages of device.
For reducing support plate thickness and realizing the encapsulation of pin multiple rows ofization array, existing solution is to use carrier-free grid
Array package (AAQFN) technique；It mainly by plating or half-etching technology, forms the slimming envelope with high-density pin
Dress, however it is necessary that and complete, easily to microelectronic component core under the assistance of the processing steps such as grinding, second etch and secondary plastic
Sheet pollutes；Complicated technical process improves the cost of microelectronic device package, reduces the reliability of packaging, very
Difficulty is applied in actual production.In order to adapt to the requirement of high density slimming encapsulation, it is necessary to develop a kind of technique simple, become
This is cheap, the novel encapsulated technique that yield rate is high.
Summary of the invention
It is an object of the invention to for prior art not enough, and the manufacture method of a kind of device without substrate package is provided.This
Plant manufacture method and can easily realize the requirement of pin multiple rows ofization array, and plastic packaging process and support plate manufacturing process can be made to close
Two is one, completes chip embedded type encapsulation, reduces package thickness, obtain Ultrathin packaging device.This manufacture method manufacturing process
Simply, with low cost, yield rate is high, be suitable for batch production.
The technical scheme realizing the object of the invention is:
The manufacture method of a kind of device without substrate package, comprises the steps:
1) accessory plate is provided；
2) interim mucosa is formed: paste on the auxiliary board or coat interim mucosa；
3) make metal level: the upper surface at interim mucosa arranges layer of metal layer, described metal level be copper, gold, silver, nickel, stannum,
The materials such as aluminum, palladium or ferrum are made, and form thin metal layer on interim mucosa；
4) patterned metal layer: use the graphical metal level of technique of etching, forms line layer, and reserved chip attachment room；
5) pasting chip: pasting chip on the chip attachment room that step 4) is reserved, chip is close to the upper table of interim mucosa
Face, chip is chip wafer or electronic devices and components；
6) electrical interconnection: use the methods such as wire bonding, flip chip bonding, carrier band automatic welding, physical vapour deposition (PVD) or printing to realize core
Sheet and the electrical interconnection of line layer；
7) making molded packages body: use mould plastic package process, form the packaging body of mold sealing material, described mould plastic package process is upper and lower
Pressing mold is by the injection packaging process of auxiliary film；
8) prepare without substrate package device: at a temperature of the adhesion failure of interim mucosa, remove interim mucosa and corresponding
Accessory plate, dries packaging body and cools down, and obtains without substrate package device.
The adhesion failure temperature of described interim mucosa is 80-250 DEG C.
The adhesion failure temperature of the most described interim mucosa is 150 DEG C.
When adhesion failure temperature, the adhesion failure of interim mucosa, packaging body can not separate with accessory plate with damaging.
Described interim mucosa is propylene glycol carbonate, Merlon or polymer-based material.
Described metal level is by paving, deposits, electroplates, chemical plating, sputters, sinters, prints or printing type is formed at
On interim mucosa.
Described mould plastic package process is the upper dip mold injection packaging process by auxiliary film, wherein auxiliary film be polyamide,
The combination of one or more in politef and poly-perfluoro alkoxy.
This manufacture method, it is achieved that the requirement of pin multiple rows ofization array, and plastic packaging process and support plate can be made to make
Process unites two into one, and completes chip embedded type encapsulation, reduces package thickness, obtained Ultrathin packaging device.This making
Method, manufacturing process is simple, with low cost, and yield rate is high, be suitable for batch production.
Accompanying drawing explanation
Fig. 1 is the manufacture method schematic flow sheet of embodiment；
Fig. 2-Fig. 9 is sectional view, that schematically shows the embodiment of the present invention manufacture method without substrate package device, its
In,
Fig. 2 is auxiliary plate structure schematic diagram；
Fig. 3 is for forming interim mucosa operation schematic diagram on the auxiliary board；
Fig. 4 is for forming thin metal layer operation schematic diagram；
Fig. 5 is that graphical thin metal layer forms line layer operation schematic diagram；
Fig. 6 is chip attachment operation schematic diagram；
Fig. 7 is chip and line layer electrical interconnection operation schematic diagram；
Fig. 8 is molding envelope operation schematic diagram；
Fig. 9 is without substrate package device package schematic diagram；
Figure 10 is to use the heretofore described ultrathin 3D stacked package body completed without the manufacture method of substrate package device to show
It is intended to.
In figure, 1. accessory plate 2. interim mucosa 3. metal level 4. line layer 5. chip 6. goes between 7. mold sealing materials 8.
Packaging body 9.3D stacked package body.
Detailed description of the invention
With embodiment, present invention is further elaborated below in conjunction with the accompanying drawings, but is not limitation of the invention.
Embodiment:
With reference to Fig. 1, a kind of ultrathin manufacture method without substrate package device, comprise the steps:
1) accessory plate 1 is provided, as shown in Figure 2；
2) interim mucosa 2 is formed: on accessory plate 1, paste or coat interim mucosa 2, as shown in Figure 3；
3) make metal level 3: the upper surface at interim mucosa 2 arranges layer of metal layer 3, described metal level 3 be copper, gold, silver,
The materials such as nickel, stannum, aluminum, palladium or ferrum are made, paving on interim mucosa 2, deposit, electroplate, chemical plating, sputter, sinter, print or
The modes such as printing form thin metal layer, as shown in Figure 4；In this example, the material of metal level 3 is copper；
4) patterned metal layer 3: use etching technics patterned metal layer 3, forms line layer 4, and reserved chip attachment room,
As shown in Figure 5；
5) pasting chip: pasting chip 5 on the chip attachment room that step 4) is reserved, chip 5 is adjacent to table on interim mucosa 2
Face, chip 5 can be chip wafer, it is also possible to be electronic devices and components, as shown in Figure 6；
6) electrical interconnection: use the methods such as wire bonding, flip chip bonding, carrier band automatic welding, physical vapour deposition (PVD) or printing to realize core
Sheet and the electrical interconnection of line layer；In this example, lead-in wire 6 is gold thread, uses the method for wire bonding to realize chip 5 and line layer 4
Electrical interconnection, as shown in Figure 7；
7) make molded packages body 8: use mould plastic package process, form the packaging body 8 of mold sealing material 7, as shown in Figure 8；Described mould
Plastic package process is the upper dip mold injection packaging process by auxiliary film；
Described auxiliary film is the combination of one or more in polyamide, politef and poly-perfluoro alkoxy.
Described mold sealing material is one or more in epoxy resin-matrix packaging EMC material, silica gel and phenylpropanolamine HC1
Combination；
In this example, auxiliary film material is polyamide, and mold sealing material 7 is epoxy resin-matrix packaging EMC material；
8) prepare without substrate package device: at a temperature of the adhesion failure of interim mucosa 2, remove interim mucosa 2 and therewith correspondence
Accessory plate 1, packaging body 8 is dried and is cooled down, obtains final without substrate package device.As shown in Figure 9；
The adhesion failure temperature of described interim mucosa is 80-250 DEG C.
The adhesion failure temperature of the interim mucosa of this example 2 is 150 DEG C.
The adhesion failure of interim mucosa 2 when 150 DEG C, packaging body 8 can not separate with accessory plate 1 with damaging.
Use said method, after design utilizes multiple chip to be packaged, i.e. above-mentioned steps 5) apply multiple chip to enter
Row attachment, and combine 3D laminated chips electrical interconnection, just available ultrathin type as shown in Figure 10 is without substrate 3D stacked package body
9。
Claims (6)
1. without a manufacture method for substrate package device, it is characterized in that, comprise the steps:
1) accessory plate is provided；
2) interim mucosa is formed: paste on the auxiliary board or coat interim mucosa；
3) metal level is made: the upper surface at interim mucosa arranges layer of metal layer；
4) patterned metal layer: use etching technics patterned metal layer, forms line layer, and reserved chip attachment room；
5) pasting chip: pasting chip on the chip attachment room that step 4) is reserved, chip is close to interim mucosa upper surface；
6) electrical interconnection: use the methods such as wire bonding, flip chip bonding, carrier band automatic welding, physical vapour deposition (PVD) or printing to realize core
Sheet and the electrical interconnection of line layer；
7) make molded packages body: use mould plastic package process, form the packaging body of mold sealing material；
8) prepare without substrate package device: at a temperature of the adhesion failure of interim mucosa, remove interim mucosa and corresponding
Accessory plate, dries packaging body and cools down, and obtains without substrate package device.
The manufacture method of device without substrate package the most according to claim 1, is characterized in that, the viscosity of described interim mucosa
Invalid temperature is 80-250 DEG C.
The manufacture method of device without substrate package the most according to claim 1, is characterized in that, the viscosity of described interim mucosa
Invalid temperature is 150 DEG C.
The manufacture method of device without substrate package the most according to claim 1, is characterized in that, described interim mucosa is carbonic acid
Propylene glycol ester, Merlon or polymer-based material.
The manufacture method of device without substrate package the most according to claim 1, is characterized in that, described metal level is by paving
Paste, deposit, electroplate, chemical plating, sputter, sinter, print or printing type is formed on interim mucosa.
The manufacture method of device without substrate package the most according to claim 1, is characterized in that, on described mould plastic package process is
Dip mold is by the injection packaging process of auxiliary film, during wherein auxiliary film is polyamide, politef and poly-perfluoro alkoxy
The combination of one or more.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610595226.XA CN106128965A (en) | 2016-07-27 | 2016-07-27 | A kind of manufacture method of device without substrate package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610595226.XA CN106128965A (en) | 2016-07-27 | 2016-07-27 | A kind of manufacture method of device without substrate package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106128965A true CN106128965A (en) | 2016-11-16 |
Family
ID=57290268
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610595226.XA Pending CN106128965A (en) | 2016-07-27 | 2016-07-27 | A kind of manufacture method of device without substrate package |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106128965A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108417522A (en) * | 2018-01-17 | 2018-08-17 | 桂林电子科技大学 | Three ply board structural circuit packaging method |
| CN108807192A (en) * | 2017-12-18 | 2018-11-13 | 深圳市环基实业有限公司 | A kind of IC package technique |
| CN110600439A (en) * | 2018-06-12 | 2019-12-20 | 深圳市环基实业有限公司 | RFID chip and manufacturing method thereof |
| CN110600382A (en) * | 2018-06-12 | 2019-12-20 | 深圳市环基实业有限公司 | Chip packaging process and product |
| CN113991004A (en) * | 2021-10-26 | 2022-01-28 | 东莞市中麒光电技术有限公司 | LED substrate manufacturing method, LED substrate, LED device manufacturing method and LED device |
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| US20070077728A1 (en) * | 2005-09-30 | 2007-04-05 | Kulkarni Sudhakar N | Adhesive system for supporting thin silicon wafer |
| CN101315923A (en) * | 2007-06-01 | 2008-12-03 | 南茂科技股份有限公司 | Chip stack package structure |
| CN102134453A (en) * | 2009-12-22 | 2011-07-27 | 日东电工株式会社 | Heat resistant adhesive sheet used in the fabrication of substrateless semiconductor package |
| CN102760665A (en) * | 2011-04-26 | 2012-10-31 | 群成科技股份有限公司 | Semiconductor package structure and manufacturing method thereof |
| CN105321867A (en) * | 2015-09-23 | 2016-02-10 | 桂林电子科技大学 | Fabrication method of interconnected support plate |
-
2016
- 2016-07-27 CN CN201610595226.XA patent/CN106128965A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070077728A1 (en) * | 2005-09-30 | 2007-04-05 | Kulkarni Sudhakar N | Adhesive system for supporting thin silicon wafer |
| CN101315923A (en) * | 2007-06-01 | 2008-12-03 | 南茂科技股份有限公司 | Chip stack package structure |
| CN102134453A (en) * | 2009-12-22 | 2011-07-27 | 日东电工株式会社 | Heat resistant adhesive sheet used in the fabrication of substrateless semiconductor package |
| CN102760665A (en) * | 2011-04-26 | 2012-10-31 | 群成科技股份有限公司 | Semiconductor package structure and manufacturing method thereof |
| CN105321867A (en) * | 2015-09-23 | 2016-02-10 | 桂林电子科技大学 | Fabrication method of interconnected support plate |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108807192A (en) * | 2017-12-18 | 2018-11-13 | 深圳市环基实业有限公司 | A kind of IC package technique |
| CN108417522A (en) * | 2018-01-17 | 2018-08-17 | 桂林电子科技大学 | Three ply board structural circuit packaging method |
| CN110600439A (en) * | 2018-06-12 | 2019-12-20 | 深圳市环基实业有限公司 | RFID chip and manufacturing method thereof |
| CN110600382A (en) * | 2018-06-12 | 2019-12-20 | 深圳市环基实业有限公司 | Chip packaging process and product |
| CN110600382B (en) * | 2018-06-12 | 2021-05-04 | 深圳市鼎华芯泰科技有限公司 | Chip packaging process and product |
| CN113991004A (en) * | 2021-10-26 | 2022-01-28 | 东莞市中麒光电技术有限公司 | LED substrate manufacturing method, LED substrate, LED device manufacturing method and LED device |
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Application publication date: 20161116 |