CN209232767U - A kind of novel semi-conductor encapsulating structure - Google Patents
A kind of novel semi-conductor encapsulating structure Download PDFInfo
- Publication number
- CN209232767U CN209232767U CN201821761996.8U CN201821761996U CN209232767U CN 209232767 U CN209232767 U CN 209232767U CN 201821761996 U CN201821761996 U CN 201821761996U CN 209232767 U CN209232767 U CN 209232767U
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- CN
- China
- Prior art keywords
- lead frame
- semiconductor chip
- bonding
- functional areas
- novel semi
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
The utility model discloses a kind of novel semi-conductor encapsulating structures, can be manufactured by using the plate armature of lead frame, encapsulating material, provide excellent heat radiation performance, high reliability, lightening, cheap semiconductor component.The utility model semiconductor packages includes semiconductor chip；Lead frame, front are that the semiconductor chip is carried in functional areas, and the back side is leg；The array of lead frames unit is encapsulated as an entirety by encapsulating material；Bonding die glue realizes that the semiconductor chip is bonding with lead frame functional areas；Bonding line realizes being electrically connected for the semiconductor chip and lead frame functional areas；Seal seals the semiconductor chip, bonding die glue, bonding line by sealing resin in the encapsulating material.
Description
Technical field
The utility model belongs to technical field of semiconductor encapsulation, and in particular to a kind of novel semi-conductor encapsulating structure and its system
Make method.
Background technique
With electronic product miniaturization and the development trend of multifunction, the semiconductor being mounted on electronic product
Part requirement is more frivolous, highly integrated, high reliability.In addition, in the commodity environment of current low priceization, it is desirable that these are partly led
The encapsulation of body component is more cheap.
Currently, most of semiconductor packages, especially DIP, SOP, QFP series encapsulate, use lead frame as partly leading
The carrier of body chip completes plastic packaging using die press technology for forming by two processes of upper core and bonding wire.This semiconductor package welding equipment
Foot is arranged in seal two sides, extends the heat dissipation path of semiconductor component, so that reliability and service life reduction.Meanwhile it is this
Semiconductor packages volume is larger, so that electronic product cannot achieve miniaturization.In addition, this frame for enclosing semi-conductor leadwire
Metal material dosage is big, has been lifted the cost of semiconductor packages.
Utility model content
The purpose of the utility model is to provide a kind of novel semi-conductor encapsulating structure and its manufacturing methods.
In order to meet above-mentioned purpose, the technical solution that the utility model is taken are as follows:
A kind of novel semi-conductor encapsulating structure, the semiconductor packages include: including lead frame, and the lead frame is just
Face is functional areas, and the back side is bottom land, and semiconductor chip is carried in the functional areas, and functional areas are equipped with several interior pin pads
For bonding wire, the interior pin pad is electrically connected with bottom land；The array of lead frames unit is encapsulated by encapsulating material
A cavity is formed at an entirety, and in the functional areas of lead frame, the inside cavity is equipped with semiconductor chip, and described half
Conductor chip is fixed on lead frame top face by bonding die glue, and the semiconductor chip is connected by bonding line and interior pin pad
It connects, realizes and be electrically connected between the semiconductor chip and the bottom land of lead frame functional areas；In the cavity of the encapsulating material
Equipped with seal, the seal is that fixed semiconductor chip, bonding die glue, interior pin pad and bonding are sealed by sealing resin
Line.
Preferably, the lead frame material by several metals in copper, iron, aluminium, gold, silver or nickel multiple layer metal material
It constitutes.
Preferably, the encapsulating material is that the insulator of resin, ceramics or glass composition is constituted.
Preferably, the material of the bonding die glue is epoxy systems or organosilicon systems resin material.
Preferably, the bonding line is made of gold thread, silver wire, copper wire or aluminum steel metal wire.
Preferably, the material of the seal is epoxy systems or organosilicon systems resin material.
The utility model has the following beneficial effects: passing through a kind of novel semi-conductor encapsulating structure of the utility model and its manufacturer
Means described in method make semiconductor component realize vertical heat dissipation, the lead that the heat that semiconductor chip generates passes through lower section
Frame is directly transferred to outside semiconductor component, and electrode heat dissipation area is big, has excellent heat dissipation performance, realizes high reliability.Half
Conductor part leg is located at seal bottom, and plate armature area occupied is small, reduces the volume of entire semiconductor component, real
It is existing lightening.Metal material dosage is saved simultaneously, is able to produce cheap semiconductor package part.
Detailed description of the invention
Fig. 1 is the cross-sectional view of the structure of the utility model；
Fig. 2 is the bottom view of Fig. 1；
In figure: 1. lead frames, 2. encapsulating materials, 3. semiconductor chips, 4. bonding die glue, 5. bonding lines, 6. cavitys, in 7.
Pin pad, 8. functional areas, 9. bottom lands.
Specific embodiment
The utility model is described further with working principle with reference to the accompanying drawing:
A kind of novel semi-conductor encapsulating structure, the semiconductor packages include lead frame 1, and the front of lead frame 1 is function
Energy area 8, the back side are bottom land 9, and semiconductor chip 3 is carried in functional areas 8, and functional areas 8 are equipped with several interior pin pads 7 and are used for
Bonding wire, interior pin pad 7 are electrically connected with bottom land 9；1 array element of lead frame by encapsulating material 2 be encapsulated as one it is whole
Body, and a cavity 6 is formed in the functional areas of lead frame 18, semiconductor chip 3 is equipped with inside cavity 6, semiconductor chip 3 is logical
It crosses bonding die glue 4 and is fixed on 1 top face of lead frame, semiconductor chip 3 is connect by bonding line 5 with interior pin pad 7, realizes institute
It states and is electrically connected between semiconductor chip 3 and the bottom land 9 of 1 functional areas 8 of lead frame；Sealing is equipped in the cavity 6 of encapsulating material 2
Body, seal are that fixed semiconductor chip 3, bonding die glue 4, interior pin pad 7 and bonding line 5 are sealed by sealing resin.Draw
1 material of wire frame is made of the multiple layer metal material of several metals in copper, iron, aluminium, gold, silver or nickel.Encapsulating material 2 is tree
The insulator of rouge, ceramics or glass composition is constituted.The material of bonding die glue 4 is epoxy systems or organosilicon systems resin material.Key
Zygonema 5 is made of gold thread, silver wire, copper wire or aluminum steel metal wire.The material of seal is epoxy systems or organosilicon systems resin
Material.
The manufacturing method of a kind of manufacturing method of novel semi-conductor encapsulating structure, the semiconductor packages has following steps:
A. multiple functional areas, interior pin pad 7 and bottom land 9 are formed in lead frame 1；
B. 1 array element of lead frame is encapsulated as an entirety by encapsulating material 2；
C. bonding die glue 4 is bonded the semiconductor chip 3 in 1 functional areas of lead frame；
D. the interior pin pad 7 of 1 functional areas of the semiconductor chip 3 and lead frame is electrically connected by bonding line 5；
E. again by with sealing resin sealing semiconductor chips 3, bonding die glue 4, interior pin pad 7, bonding line 5 and lead frame
1 functional areas of frame, form each semiconductor package part.
The functional areas and pad being arranged on lead frame 1 are by punching press, etching, laser processing, electroplating processing method
And formed.Encapsulating material 2 is that 1 array element of lead frame is encapsulated as an entirety by molding sintering or injection moulding process,
It forms mechanical, electrical, physics and is connected chemically, bonding die glue 4 passes through dispensing, dips in glue, method for printing screen arrangement to lead frame 1
Functional areas.Cured method realizes sealing, the array after sealing resin encapsulates glue spots glue by compression molding or liquid
In the step of unit sealed enclosure, " Air-Uplift " cutting method or patterning method are used.
The utility model semiconductor packages includes lead frame 1, and 1 front of lead frame is functional areas 8, and the back side is bottom weldering
Disk 9；Lead frame 1 is encapsulated as an entirety by molding sintering or injection moulding process by encapsulating material 2, and is pushed up in lead frame 1
Portion forms seal cavity 6.It is 3 installation region of semiconductor chip inside cavity 6；Carry semiconductor chip in 1 functional areas 8 of lead frame
3；Bonding die glue 4 is used to semiconductor chip 3 being bonded in lead frame 1；Bonding line 5 is logical according to 3 design requirement of semiconductor chip
It crosses bonding line 5 to connect semiconductor chip 3 and the interior pin pad 7 on lead frame 1, interior pin pad 7 is passing through bottom
Portion's pad 9 is electrically connected with extraneous electric elements formation；All semiconductor chips 3, bonding die glue 4, interior pin pad 7,5 and of bonding line
1 functional areas of lead frame are respectively positioned in encapsulating material 2, while also being located in seal cavity 6.
Claims (6)
1. a kind of novel semi-conductor encapsulating structure, which is characterized in that the semiconductor packages include: including lead frame (1), it is described
The front of lead frame (1) is functional areas (8), and the back side is bottom land (9), and the functional areas (8) carry semiconductor chip
(3), functional areas (8) are equipped with several interior pin pads (7) and are used for bonding wire, the interior pin pad (7) and bottom land (9) electricity
Connection；Lead frame (1) array element is encapsulated as an entirety, and the function in lead frame (1) by encapsulating material (2)
Energy area (8) forms a cavity (6), is equipped with semiconductor chip (3) inside the cavity (6), the semiconductor chip (3) passes through
Bonding die glue (4) is fixed on lead frame (1) top face, and the semiconductor chip (3) passes through bonding line (5) and interior pin pad
(7) it connects, realizes and be electrically connected between the semiconductor chip (3) and the bottom land (9) of lead frame (1) functional areas (8)；It is described
Seal is equipped in the cavity (6) of encapsulating material (2), the seal is that fixed semiconductor chip is sealed by sealing resin
(3), bonding die glue (4), interior pin pad (7) and bonding line (5).
2. a kind of novel semi-conductor encapsulating structure according to claim 1, which is characterized in that lead frame (1) material
Matter is made of the multiple layer metal material of several metals in copper, iron, aluminium, gold, silver or nickel.
3. a kind of novel semi-conductor encapsulating structure according to claim 1, which is characterized in that the encapsulating material (2) is
The insulator of resin, ceramics or glass composition is constituted.
4. a kind of novel semi-conductor encapsulating structure according to claim 1, which is characterized in that the material of the bonding die glue (4)
Matter is epoxy systems or organosilicon systems resin material.
5. a kind of novel semi-conductor encapsulating structure according to claim 1, which is characterized in that the bonding line (5) is by gold
Line, silver wire, copper wire or aluminum steel metal wire are constituted.
6. a kind of novel semi-conductor encapsulating structure according to claim 1, which is characterized in that the material of the seal is
Epoxy systems or organosilicon systems resin material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821761996.8U CN209232767U (en) | 2018-10-29 | 2018-10-29 | A kind of novel semi-conductor encapsulating structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821761996.8U CN209232767U (en) | 2018-10-29 | 2018-10-29 | A kind of novel semi-conductor encapsulating structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN209232767U true CN209232767U (en) | 2019-08-09 |
Family
ID=67501080
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201821761996.8U Active CN209232767U (en) | 2018-10-29 | 2018-10-29 | A kind of novel semi-conductor encapsulating structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN209232767U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109360815A (en) * | 2018-10-29 | 2019-02-19 | 天水华天科技股份有限公司 | A kind of novel semi-conductor encapsulating structure and its manufacturing method |
-
2018
- 2018-10-29 CN CN201821761996.8U patent/CN209232767U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109360815A (en) * | 2018-10-29 | 2019-02-19 | 天水华天科技股份有限公司 | A kind of novel semi-conductor encapsulating structure and its manufacturing method |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20230118 Address after: 512029 No. 88, Shengqiang Road, Wujiang District, Shaoguan City, Guangdong Province Patentee after: Guangdong Shaohua Technology Co.,Ltd. Address before: 741000 Gansu province Tianshui District Shuangqiao Road No. 14 Patentee before: TIANSHUI HUATIAN TECHNOLOGY Co.,Ltd. |
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| TR01 | Transfer of patent right |