CN102221671B - Signal stability detector and time delay tester - Google Patents
Signal stability detector and time delay tester Download PDFInfo
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- CN102221671B CN102221671B CN 201110078659 CN201110078659A CN102221671B CN 102221671 B CN102221671 B CN 102221671B CN 201110078659 CN201110078659 CN 201110078659 CN 201110078659 A CN201110078659 A CN 201110078659A CN 102221671 B CN102221671 B CN 102221671B
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Abstract
The invention provides a signal stability detector and a time delay tester employing the signal stability detector. Each key combination logic output point of the time delay tester is provided with one corresponding signal stability detector for detecting whether a signal output by each key combination logic output point in the stable period of a combination logic signal rolls over or not; and moreover, the time delay tester is also provided with a global error signal generator for generating a global error signal when any signal stability detector detects that the combination logic signal rolls over in a detection scope so as to indicate the timing out of a circuit. The time delay tester not only can be used for effectively implementing online time delay failure detection, but also applies a partial scan enable signal generator in a scan chain of the circuit. The time delay tester can be used for effectively conducting online time delay failure detection, and can be used for providing effective support for off-line time delay failure detection. Moreover, hardware expenses are lower.
Description
Technical field
The invention belongs to the semiconductor process techniques field, relate in particular in high performance chip, by the delay failure in the chip is effectively detected, guarantee the Performance And Reliability of chip.
Background technology
Along with the development of integrated circuit fabrication process, the continuous refinement of transistor feature size.Complexity and the integrated level of whole chip improve constantly.Chip comprises the phenomenon of various defectives after manufacturing more and more significant, and has brought serious challenge for thus the Performance And Reliability of chip.In addition, under deep submicron process, the technological parameter in the integrated circuit is difficult to accurately control to corresponding expectation value, but has a process deviation.Thereby cause logic gate and signal propagation path in the chip can have very large time-delay deviation, and may cause the chip timing out.Thus, the quality of paying in order to ensure chip, in the situation that the timing constraint of chip also becomes more and more stricter, usually need to be to being operated under the specified clock frequency that chip carries out that effective delay testing guarantees that it can be correct.
As a rule, for the delay failure in the test chip, need to use one group of test vector＜V1, V2 at circuit-under-test〉finish.First test vector wherein, i.e. initialization vector V1 is used for the internal logic states of initialization circuit-under-test; Second test vector namely loads vectorial V2, is used for exciting the fault effect with the communication target fault, thereby the response by capture circuit after the specified clock period comes the delay failure in the testing circuit.The initialization vector V1 of delay testing vector centering generally is that the scan test clock of using at a slow speed obtains by scan chain is shifted.Obtain manner according to delay testing vector centering being loaded vectorial V2 can roughly be divided into enhancement type scanning to common time delay measuring method, catches loading, and displacement loads and three kinds of methods.In the reinforced scanning delay tests method, can preserve simultaneously two bits in the sweep trigger, can there be any structural constraint between initialization vector V1 and the vectorial V2 of loading during test.Therefore, this method can reach very satisfied jump delay failure coverage rate.But the circuit test state when not affecting displacement in order to preserve two bit test data needs very large hardware spending, thereby seldom is used.In catching load mode, load vectorial V2 and be by loading stage clock period, the Circuit responce that circuit is caught initialization vector V1 obtains.The realization cost of this delay testing mode is very little.Yet in the middle of this method, owing to when obtaining the vectorial V2 of loading, will be subject to the constraint of circuit structure, thereby cause a lot of jump failures to detect, namely can not get the Observable output that a corresponding circuit state can encourage the fault effect of these faults and propagate into chip.Therefore, catch the fault coverage that loads time delay measuring method relatively low.Load in the delay testing mode in displacement, loading vectorial V2 is to be shifted by initialization vector V1 to obtain, although displacement loads the scan enable signals that delay testing need to be realized a real speed, yet this method can realize higher fault coverage, and only needs less test vector collection scale.Chip all needs to adopt aforesaid off-line time delay measuring method to guarantee that it can correctly be operated under the specified frequency of operation before dispatching from the factory usually.
Even chip can correctly be operated under the specified clock frequency of chip when the off-line delay testing, chip is in the middle of use procedure, also may because soft error has occured, crosstalked, power supply noise etc. causes chip generation transient state delay failure, and final generating function inefficacy.Therefore, for the application of some keys, usually also need chip to detect in the online delay failure that normal manipulation mode carries out disabler.By the signal stabilization of observation circuit Combinational logic output under the normal function pattern, the transient state delay failure whether can be online come occurs in the detection chip.In the former online time delay detection technology, the people is arranged by come the delay on the test set logic output signal at a kind of concurrent detecting device of Combinational logic output design.Yet adopt this concurrent detecting device, also need in circuit, increase the detection that designs an XOR gate ability supporting signal time delay by each Combinational logic output.In addition, also needing to design the delay situation that an extra circuit complex network analyzes on each Combinational logic output in the chip comes whether to have delay failure in the middle of the decision circuitry.Thereby adopt this method, will bring very large complex circuit designs degree and hardware spending.
In addition, in the former technology, realize that for supporting chip displacement loads the off-line delay testing and the online delay testing technology of supporting chip is all separated consideration, namely need respectively to design differently hardware configuration and realize.
Summary of the invention
As seen in order to guarantee the reliability requirement of chip, both be necessary very much chip is adopted effective off-line delay testing, also be necessary very much it is adopted effectively online delay testing.Therefore, the object of the invention is to overcome the defective of above-mentioned prior art, in integrated circuit chip, designed a kind of proving installation of low expense, this proving installation can realize effectively that online delay failure detects, can effectively support the detection of off-line delay failure again, thereby improve the q﹠r that chip dispatches from the factory.
The objective of the invention is to be achieved through the following technical solutions:
On the one hand, provide in an embodiment of the present invention a kind of signal stabilization detecting device, having comprised: the first transistor, transistor seconds, the 3rd transistor, the 4th transistor, the 5th transistor, the 6th transistor and a phase inverter; Wherein, the grid of the first transistor receives the Combinational logic output signal, and the source electrode of the first transistor connects power supply, and the drain electrode of the first transistor connects the source electrode of transistor seconds and is connected to the 4th transistorized grid and the 6th transistorized grid; The grid receive clock signal of transistor seconds, the drain electrode of transistor seconds connect the 3rd transistorized drain electrode and are connected to the 5th transistorized grid by phase inverter; The 3rd transistorized grid receives Combinational logic output signal, the 3rd transistorized source ground; The 4th transistorized source electrode provides output signal; The 4th transistorized drain electrode connects the 5th transistorized source electrode; The 5th transistorized drain electrode connects the 6th transistorized drain electrode; The 6th transistorized source ground.
Signal stabilization detecting device according to the embodiment of the invention, it is within the stabilization sub stage of Combinational logic output signal, if the output signal of described signal stabilization detecting device transfers logic low to from logic high, can determine that then upset has occured the Combinational logic output signal; The start time of described stabilization sub stage is the triggering of clock deducts trigger along the moment that arrives Time Created; The termination time of described stabilization sub stage is that the clock that the triggering of clock adds trigger constantly along arriving is delayed time to data terminal time-delay and the shortest path in the circuit-under-test.
According to the signal stabilization detecting device of the embodiment of the invention, wherein said the first transistor is the PMOS transistor, and other transistors are nmos pass transistor.
Another aspect provides a kind of delay testing device in an embodiment of the present invention, comprising: one or more aforesaid signal stabilization detecting devices, and it is arranged at least one Combinational logic output point that need to detect; An and global error signal generator that links to each other with described one or more signal stabilization detecting devices; When any one described signal stabilization detecting device detected Combinational logic output signal generation upset, described global error signal generator generated a global error signal, and described global error signal is used to indicate the timing out of circuit.
Delay testing device according to the embodiment of the invention, wherein said global error signal generator comprises the 7th transistor, phase inverter and impact damper, the 7th transistorized grid is connected in the phase inverter output of receive clock signal, the 7th transistorized source electrode connects power supply, the 7th transistorized drain electrode is connected with the output of one or more described signal stabilization detecting devices by connecting line and by impact damper output global error signal, described the 7th transistor is the PMOS transistor.
Delay testing device according to the embodiment of the invention, wherein can also comprise a local scan enable signal maker in the scan chain that is arranged on circuit-under-test, what described local scan enable signal was given birth to device is input as scan enable signals, scan input signal and circuit clock signal; The first output that described local scan enable signal is given birth to device is connected in the scan chain the with it scan input end of adjacent next scanning element, second is output as local scan enable signal, and described local scan enable signal is used for the scan enable end of scanning element in the driven sweep chain.
According to the delay testing device of the embodiment of the invention, wherein, described local scan enable signal maker comprise first, second and third trigger, selector switch and one or; Wherein said the first trigger is not connected with circuit-under-test, it is input as scan input signal and clock signal, output is connected to the second input end of selector switch, the output of described selector switch is connected to the input end of the second trigger, the output of the second trigger be connected to the input end of the 3rd trigger, described selector switch first input end and or the door first input end; The second input end described or door receives scan enable signals, and its output is connected to the selecting side of described selector switch, and exports local enable signal; The output of described the 3rd trigger is connected to the next scanning element of circuit-under-test scan chain.
Delay testing device according to the embodiment of the invention, when displacement loads delay testing, the second trigger of described local scan enable signal maker is swept logic high when last clock period that scanning moves into, be loaded logic low when loading the clock period; Described local scan enable signal is turned to logic low along with the state turnover of the second trigger after loading the clock period; After catching the clock period, be turned to logic high with scan enable signals.
Compared with prior art, the invention has the advantages that: at first, a kind of proving installation of low expense is provided, when carrying out online delay failure detection, any one signal stabilization detecting device that is arranged on crucial Combinational logic output point detects the signal stabilization violation, the global error signal generator will generate a global error signal, is used to refer to the timing out of circuit, thereby the transient state delay failure that chip is occured under the normal function pattern can be detected effectively.Secondly, by be provided with a local scan enable signal maker in the scan chain of circuit-under-test, this proving installation effectively supporting chip displacement loads the off-line delay testing.So this proving installation adopts identical hardware configuration to unify to support off-line and online delay failure to detect.
Description of drawings
Embodiments of the present invention is further illustrated referring to accompanying drawing, wherein:
Fig. 1 is the Combinational logic output signal waveform schematic diagram according to the embodiment of the invention;
Fig. 2 is the signal stabilization detecting device schematic diagram according to the embodiment of the invention;
Fig. 3 is the global error signal generator schematic diagram according to the embodiment of the invention;
Fig. 4 is the local scan enable signal maker schematic diagram according to the embodiment of the invention;
Fig. 5 is the schematic diagram according to the device that is used for online and off-line delay testing of the embodiment of the invention;
Fig. 6 is the online delay testing simulation waveform schematic diagram according to the embodiment of the invention;
Fig. 7 is the off-line delay testing simulation waveform schematic diagram according to the embodiment of the invention.
Embodiment
In order to make purpose of the present invention, technical scheme and advantage are clearer, and the present invention is described in more detail by specific embodiment below in conjunction with accompanying drawing.Should be appreciated that specific embodiment described herein only in order to explain the present invention, is not intended to limit the present invention.
A completely delay testing requirement can check the transmission delay of any path in the circuit-under-test whether to surpass the work clock cycle.The path here is the physical path in the combinational circuit, i.e. an alternate sequence that is comprised of lead-in wire and door the input end of the original output from the output terminal of the original input of circuit or trigger to circuit or trigger.Because rising skip signal and the propagation delay of decline skip signal in circuit component are different, every physical path is again corresponding to two logical paths.For arbitrary logical path, if its signal transmission delay has surpassed the work clock cycle, then there is path delay fault (path delay fault) in this logical path.Therefore, in delay testing, be often referred to the test to the logical path of combinational circuit.
The circuit that adopts in embodiments of the present invention belongs to clock decline edge sensitive, and in fact, the present invention also can be applied in the middle of the sequential circuit of rising edge sensitivity.Concerning a synchronizing sequential circuit, in theory, if there is not any fault in this circuit, concerning a Combinational logic output signal S, certainly exist the stage of a signal stabilization so.This stage can represent with formula TS=(t1, t2), and wherein t1 and t2 represent respectively the initial sum termination time of stabilization sub stage.In fact, why having so signal stabilization period is because signal must keep stablizing a Time Created before clock trigger signal arrives, in addition, this signal also keeps stablizing in will be during ensuing clock adds the shortest circuit delay to flip-flop data output.
Wherein, signal stabilization stage TS can represent with following formula:
TS＝((Tc-Tsetup)，(Tc+Tcq+Tcommin))(1)
Wherein Tsetup represents the Time Created of trigger, and Tcommin represents shortest path time-delay in the circuit, and Tcq represents the clock of trigger to the data terminal time-delay, and Tc represents the triggering of clock along arriving constantly.
Fig. 1 is the schematic diagram according to the Combinational logic output signal waveform of the embodiment of the invention, wherein shows respectively stabilization sub stage, changes phase and the sensing range of Combinational logic output signal.Obviously, if the circuit normal operation, all Combinational logic output signals are stable with holding signal within the stabilization sub stage.Otherwise the signal upset occurs at least one Combinational logic output signal during this, also can be called signal the stability violation occurs.Therefore, in an embodiment of the present invention to delay failure detect also be based on to the Combinational logic output signal within the stabilization sub stage, whether occur the upset detect, sensing range is exactly the stabilization sub stage TS of signal.In the middle of the practical application, need a signal to identify this sensing range.Yet, if id signal of specialized designs will produce larger cost expense so.Therefore can adopt the negative half-cycle of clock signal to indicate this sensing range.It should be noted that embodiments of the invention are based on high speed circuit, and the shortest path time delay has also surpassed half of circuit delay in the circuit.Otherwise, when application is of the present invention, just need to adjust the dutycycle of clock signal, so that negative half-cycle width the prolonging the most in short-term less than circuit of clock signal.
Provide in one embodiment of the invention and be used at the sensing range detection signal whether the signal stabilization detecting device that stability is violated occuring.Fig. 2 is the schematic diagram of realizing according to the transistor level of the signal stabilization detecting device of the embodiment of the invention, two input signals is wherein arranged: clock signal clk and Combinational logic output signal CO
1With an output signal.
As shown in Figure 2, described signal stabilization detecting device comprises 6 MOS transistor npn npn M1, M2, M3, M4, M5, M6, and a phase inverter; Wherein the grid of M1 receives the Combinational logic output signal, and the source electrode of M1 is connected to power vd D, and the drain electrode of M1 connects the source electrode of M2 and is connected to the grid of M4 and the grid of M6 at the S1 place; The grid receive clock signal CLK of M2, the drain electrode of M2 connects the drain electrode of M3 and is connected to the grid of M5 by phase inverter at the S3 place at the S2 place; The grid of M3 receives Combinational logic output signal CO
1, the source ground GND of M3; The source electrode of M4 provides output signal at node Error1 place, and the drain electrode of M4 connects the source electrode of M5; The drain electrode of M5 connects the drain electrode of M6; The source ground of M6.Wherein, M1 is the PMOS transistor, and other transistors are nmos pass transistor.
As shown in Figure 2, when clock signal clk is in logic high, transistor M2 will be switched on, thereby will produce identical logical value at S1 with the S2 place.At this moment, as Combinational logic output signal CO
1Be 0 o'clock, M1 also is switched on, and is 1 in the logical value of node S1 and S2; When the CLK signal switches to logic low, S2 will be in quick condition and keep logical value 1 before, and another logical value that meets the node S1 of electricity is 1.If this moment combinational logic signal CO
1On signal upset has occured becomes 1, M3 and be switched on, it is that the logical value at 0, S3 place becomes 1, S1 and is in quick condition that the logical value of S2 will be discharged, the logical value 1 before keeping, will all have logic high, Error owing to S1 and S3 this moment
1To form a path between node and the GND, thus Error
1Will be discharged to logic low, therefore at node Error
1The place will provide the output signal of logic low.
Similarly, when clock signal clk is in logic high, as Combinational logic output signal CO
1Be 1 o'clock, M2 and M3 are switched on, and S1 and S2 are 0; When the CLK signal switches to logic low, S1 will be in quick condition and keep logical value 0 before, and the node S2 of another ground connection is discharged to 0.If this moment combinational logic signal CO
1On signal upset has occured becomes 0, M1 and be switched on, S2 will be in quick condition and keep before logical value 0, the logical value at S3 place is that the logical value of 1, S1 will become 1, all have logic high, Error owing to S1 and S3 this moment
1To form a path between node and the GND, thus Error
1Will be discharged to logic low, therefore at node Error
1The place will provide the output signal of logic low.
As seen, within the stabilization sub stage of Combinational logic output signal, if the drain electrode of the drain electrode of described M1 and M3 is in different logic levels, M4 then, M5, three transistors of M6 all will with the ground conducting, the output signal of described signal stabilization detecting device transfers logic low to from logic high, thereby can judge Combinational logic output signal CO
1The signal upset has occured in sensing range.
In yet another embodiment of the present invention, the source electrode of the transistor M4 in as shown in Figure 2 the signal stabilization detecting device is at node Error
1Can also be connected to as shown in Figure 3 global error signal generator by connecting line.
Fig. 3 is the schematic diagram of realizing according to the transistor level of the global error signal generator of the embodiment of the invention, it can connect one or more signal stabilization detecting devices, violate situation when its any one signal stabilization detecting device that connects detects a signal stabilization, it will generate the timing out that a global error signal is used to refer to circuit.
The global error signal generator comprises PMOS transistor M7 as shown in Figure 3, the grid of M7 is connected in the phase inverter output of receive clock signal, the source electrode of M7 connects power supply, and the drain electrode of M7 is connected with the output at the Error node place of each signal stabilization detecting device by connecting line and exports the global error signal by impact damper.When clock signal clk was in logic high, M7 was switched on, and the Error node of each signal stabilization detecting device is charged to logic high, Error
1To form a high resistance pathways (as shown in Figure 2) between node and the GND, this is because S1 has different logic level values with S3.When clock signal clk was in logic low, the logical value of each Error node was in quick condition, the logic high before keeping, and this moment, the global error signal of output was logic high.Detected the upset of signal when any one signal stabilization detecting device of its connection, (as shown in Figure 2) is because Combinational logic output signal CO
1Overturn in sensing range, node S1 and S3 place will all have logic high, Error
1To form a path between node and the GND, thus Error
1Will be discharged to logic low, the global error signal also can pass through this Error
1Node is discharged to low level to the path between the earth point GND.When the global error signal is logic low, just mean that delay failure has occured circuit.
In yet another embodiment of the present invention, a kind of proving installation online and that the off-line delay failure detects that is used for of unification is provided, Fig. 4 is online and the off-line delay testing device schematic diagram of being used for according to the embodiment of the invention, this delay testing device mainly comprises: one or more signal stabilization detecting devices and a global error signal generator, and a local scan enable signal maker.
Wherein, each the crucial Combinational logic output point at circuit-under-test has inserted a signal stabilization detecting device as shown in Figure 2; Each signal stabilization detecting device can be directly connected to a global error signal generator as shown in Figure 3; When any one signal stabilization detecting device has detected the signal stabilization violation, the global error signal generator can generate a global error signal, is used to refer to the timing out of circuit.With reference to figure 2, work as Error
1When node becomes logic low, just mean Combinational logic output signal CO
1Sent out the signal upset in the stabilization sub stage.For each Combinational logic output CO
i(1＜=i＜=N), all be provided with respectively a signal stabilization detecting device, corresponding Error
iSignal can be used for driving global error signal generator (as shown in Figure 3).Become low level when upset occurs for the logical value of certain Error node, the global error signal also can be discharged to low level to the path between the earth point by this Error node.When the global error signal is logic low, just mean that delay failure has occured circuit.
In order effectively to support the off-line delay testing, also in the scan chain of circuit-under-test, used a local scan enable signal maker in addition.
When carrying out the off-line delay testing, usually adopt one by the high-frequency clock loading that generates in the sheet and the test response of capture circuit, and the slow scanning clock that adopts an outside auto testing instrument to provide moves into and shifts out test and excitation and test response.Usually, scan enable signals SEN (Scan Enable) is used as at a high speed and the selection signal of clock at a slow speed.When scan enable signals was logic low, the high-frequency clock that generates in the sheet was transferred to the inside circuit timing unit, otherwise, the scan clock at a slow speed that transmission measuring set is provided.Therefore, when adopting displacement to load the delay testing mode, be difficult to usually guarantee that the interval of delay testing between loading and catching is a high-frequency clock cycle just.
In order to overcome the problems referred to above, in the scan chain of circuit-under-test, inserted in an embodiment of the present invention a local scan enable signal maker, adopted local scan enable signal generative circuit as shown in Figure 5, what local scan enable signal was given birth to device is input as scan enable signals SEN, scan input signal SI and circuit clock signal CLK; Its output Q is connected to the input end of the next scanning element in the scan chain, also export simultaneously local scan enable signal LSEN (Local Scan Enable), local scan enable signal LSEN is used for driving the scan enable end (as shown in Figure 5) of scanning element in the circuit-under-test.The local scan enable signal generative circuit by N.Ahmed etc. document " At-Speed Transition Fault Testing With Low Speed Scan Enable; " Proceedings of VLSI Test Symposium, 2005, having increased a trigger FF0 on the basis of the inner scanning enable signal generative circuit (Local Scan Enable Generator) that the pp.1-6 punching proposes is used for avoiding FF1 (Flip Flop) front to be attached thereto the value constraint of sweep trigger, wherein, the value constraint refers to because FF1 must value be 0 after loading the clock period, and this value derives from the scanning immigration that the front is attached thereto the state value of sweep trigger.If obviously define link to each other with the FF1 state of sweep trigger of this front, may cause the reduction of fault coverage rate.For fear of this constraint, in the local scan enable signal generative circuit, increased a FF0 trigger that does not link to each other with circuit-under-test in FF1 trigger front.Local scan enable signal maker as shown in Figure 5 comprises 3 trigger FF0, FF1, FF2; Trigger FF0 is not connected with circuit-under-test, it is input as scan input signal SI and clock signal clk, its output is connected to the second input end of selector switch, the output of this selector switch is connected to the input end of trigger FF1, the output of trigger FF1 be connected to the input end of trigger FF2, described selector switch first input end and or the door first input end; The second input end described or door receives scan enable signals SEN, and its output is connected to the selecting side of described selector switch, and exports local enable signal LSEN; The output of described trigger FF2 is connected to the next scanning element of circuit-under-test scan chain.
When displacement loads the off-line delay testing, at first generate corresponding delay testing vector for circuit-under-test; Then, scan enable signals SEN is set to logic high, and test clock loads displacement in the scan chain of delay testing vector immigration circuit-under-test thereby pass through at a slow speed.In last clock period that scanning moves into is displaced to logic high by the application testing vector FF1 trigger in the local scan enable signal generative circuit unit.Then, the SEN signal switches to logic low from logic high; When loading the clock period, by the application testing vector logic low is loaded in the FF1 trigger in the local scan enable signal generative circuit unit.Thereby after loading the clock period, local scan enable signal LSEN will be turned to along with the state turnover of FF1 logic low.Obviously, after catching the clock period, local scan enable signal LSEN will follow scan enable signals SEN and be turned to logic high.For catching the delay testing mode that loads, as long as last clock period that scanning moves into and loading are during the clock period, FF1 in the local scan enable signal generative circuit unit is constrained to logic low, and so obvious local scan enable signal LSEN will follow scan enable signals SEN and carry out state turnover.
Load and catch loading off-line delay testing for the displacement of using based on the local scan enable signal maker, with regard to scan enable SEN signal, all be to move into last clock period in scanning to become logic low, be logic low loading and catch the clock period.By noted earlier, when scan enable SEN signal is logic low, high-frequency clock is sent in the middle of the circuit in the sheet, thereby has guaranteed the reality fast characteristic of test vector between loading and catching.
At last, after arriving at sampling clock, detected by the dejitterizer that is in each crucial Combinational logic output point and circuit-under-test to be applied behind the test vector Combinational logic output whether stability occurs in sensing range violate, if have, then generate the global error signal by the global error maker and come delay failure in the indicating circuit.Like this, by adopting the local scan enable signal that generates, this proving installation can support displacement to load the delay testing mode effectively.Can find, only need ignore structure of the present invention, traditional catching loads delay testing and the stuck-at fault detection can not be affected.
In the delay testing device that the embodiment of the invention provides, by introducing such local scan enable signal maker, scan enable signals SEN can when the sheet internal clock of guaranteeing to select a high speed enters into circuit, can also guarantee to support displacement to load the delay testing mode with the local scan enable signal that generates.It should be noted that, guarantee the reality fast characteristic of test vector between loading and catching when adopting in embodiments of the present invention the fundamental purpose of local scan enable signal maker to be to load delay testing for the chip displacement, and be not for local scan enable signal being designed to a timed-shutoff key signals.Thereby only need in the present invention to use a local scan enable signal generative circuit, and unlike above-mentioned list of references, need in circuit, design a large amount of local scan enable signal generative circuits.
Delay testing device in above-described embodiment can be used for online and the delay failure of detection chip off-line, thereby improves the q﹠r that chip dispatches from the factory, and implementation step is as follows:
Online delay testing:
When circuit is under the normal function state, if being detected stability, violates the Combinational logic output of a key, may be owing to crosstalking, power supply noise, soft errors etc. cause, and the global error signal will indicate this circuit that timing out has occured so.After sampling clock arrives, detect each crucial Combinational logic output signal; If finding has the Combinational logic output signal to overturn in sensing range, then produce a global error signal and come whether to exist in the indicating circuit delay failure.
Displacement loads the off-line delay testing:
Step 1: for circuit-under-test generates corresponding delay testing vector;
Step 2: be the SEN signal setting logic high, thereby passing through at a slow speed, test clock loads displacement in the scan chain of delay testing vector immigration circuit-under-test, after in the end a displacement sweeps the stage, by the application testing vector logic high is swept among the trigger FF1 in the local scan enable signal maker;
Step 3:SEN signal switches to logic low from logic high, by the application testing vector logic low is loaded into when loading the clock period in the FF1 trigger in the local scan enable signal maker;
Step 4: whether after sampling clock arrives, detecting in sensing range has Combinational logic output that stability occurs to violate, if having, then generates the global error signal and comes delay failure in the indicating circuit.
For the good effect of delay testing device in the embodiment of the invention is described, the inventor adopts 90nmCMOS technique to carry out emulation experiment.Fig. 6 is for carrying out the simulation waveform schematic diagram of online delay testing according to the proving installation of the embodiment of the invention.Shortest path time delay in the circuit is greater than half circuit clock cycle.In order to illustrate conveniently, two Combinational logic output signal CO have only been listed among Fig. 6
1And CO
2Can find from Fig. 6, when circuit works, when delay failure has occured, global error signal Global Error will become logic low, thus the timing out in the indicating circuit.
Fig. 7 is for carrying out the simulation waveform schematic diagram of off-line delay testing according to the delay testing device of the embodiment of the invention.As can be seen from Figure 7, when the SEN signal was logic high, the slow scanning clock sclk is selected to be sent into the system clock tree and test vector V1 is swept in the middle of the circuit.When SEN switched to logic low, high speed circuit clock FCLK was sent to the Circuits System Clock Tree and is used for loading test vector V2 and indicator signal sensing range.In final stage and load phase that scanning moves into, the FF1 in the local scan enable signal generative circuit is set to respectively 1 and 0, thereby when load phase, the LSEN signal will turn to logic low from logic high.Thereby the V2 vector can obtain by the V1 vector is carried out 1 bit shift.The dejitterizer that is arranged on each crucial Combinational logic output point is used for detecting circuit-under-test is applied the delay situation on the Combinational logic output line behind the test vector, and the delay failure of circuit-under-test also can be by violating to detect by the stability of detection signal in sensing range like this.
Table 1
For the hardware spending of the delay testing device that the embodiment of the invention provides is described, can embed the delay testing device of the embodiment of the invention respectively in the middle of the circuit of full scan IWLS2005, and having adopted a kind of commercial synthesis tool under 90nm CMOS technique, to assess, corresponding experimental result is presented in the middle of the table 1.The hardware spending of the delay testing device of table 1 embodiment of the invention.
In the table 1 the 1st classified circuit name as, and the 2nd row and the 3rd are listed as the number represent respectively trigger and original output in the circuit.The 4th row represent the pass key output signal in the circuit.Pass key output signal wherein is defined as the time slot value that has a paths at least and passes through this output node less than 20% circuit clock cycle.Each pass key output signal in the circuit all is provided with respectively a Detection of Stability device.The 5th classifies the hardware spending of proving installation of the present invention as.The 6th classifies the hardware spending of whole circuit as.The 7th hardware spending of classifying this proving installation as accounts for the hardware spending number percent of whole circuit.As can be seen from Table 1, delay testing device of the present invention has lower hardware spending.
A kind of delay testing device of low expense is provided for integrated circuit being carried out online and off-line delay testing among the invention described above embodiment in sum.At first, when carrying out online delay failure detection, any one signal stabilization detecting device that is arranged on crucial Combinational logic output point detects the signal stabilization violation, the global error signal generator will generate a global error signal, be used to refer to the timing out of circuit, thereby the transient state delay failure that chip is occured can be detected effectively under the normal function pattern.Secondly, the signal stabilization detecting device that also can utilize each to be arranged on each crucial Combinational logic output point when being shifted test detects the time delay situation of the circuit behind the application testing vector, and keep the reality fast characteristic of test vector between loading and catching by be provided with a local scan enable signal maker in the scan chain of circuit-under-test, this delay testing device also can detect the off-line delay failure provides effective twelve Earthly Branches to hold.
Although the present invention is described by preferred embodiment, yet the present invention is not limited to embodiment as described herein, also comprises without departing from the present invention various changes and the variation done.
Claims (8)
1. a signal stabilization detecting device is characterized in that comprising: the first transistor, transistor seconds, the 3rd transistor, the 4th transistor, the 5th transistor, the 6th transistor and a phase inverter; Wherein, the grid of the first transistor receives the Combinational logic output signal, and the source electrode of the first transistor connects power supply, and the drain electrode of the first transistor connects the source electrode of transistor seconds and is connected to the 4th transistorized grid and the 6th transistorized grid; The grid receive clock signal of transistor seconds, the drain electrode of transistor seconds connect the 3rd transistorized drain electrode and are connected to the 5th transistorized grid by phase inverter; The 3rd transistorized grid receives Combinational logic output signal, the 3rd transistorized source ground; The 4th transistorized source electrode provides output signal; The 4th transistorized drain electrode connects the 5th transistorized source electrode; The 5th transistorized drain electrode connects the 6th transistorized drain electrode; The 6th transistorized source ground.
2. signal stabilization detecting device according to claim 1, it is characterized in that within the stabilization sub stage of Combinational logic output signal, if the output signal of described signal stabilization detecting device transfers logic low to from logic high, can determine that then upset has occured the Combinational logic output signal; The start time of described stabilization sub stage is the triggering of clock deducts trigger along the moment that arrives Time Created; The termination time of described stabilization sub stage is that the clock that the triggering of clock adds trigger constantly along arriving is delayed time to data terminal time-delay and the shortest path in the circuit-under-test.
3. signal stabilization detecting device according to claim 2 is characterized in that described the first transistor is the PMOS transistor, and other transistors are nmos pass transistor.
4. delay testing device is characterized in that comprising:
One or more such as the described signal stabilization detecting device of above-mentioned arbitrary claim, it is arranged at least one Combinational logic output point that need to detect; And
A global error signal generator that links to each other with described one or more signal stabilization detecting devices;
When any one described signal stabilization detecting device detected Combinational logic output signal generation upset, described global error signal generator generated a global error signal, and described global error signal is used to indicate the timing out of circuit.
5. delay testing device according to claim 4, it is characterized in that described global error signal generator comprises the 7th transistor, the second phase inverter and impact damper, the 7th transistorized grid is connected in the second phase inverter output of receive clock signal, the 7th transistorized source electrode connects power supply, the 7th transistorized drain electrode is connected with the output of one or more described signal stabilization detecting devices by connecting line and by impact damper output global error signal, described the 7th transistor is the PMOS transistor.
6. according to claim 4 or 5 described delay testing devices, characterized by further comprising a local scan enable signal maker in the scan chain that is arranged on circuit-under-test, described local scan enable signal maker be input as scan enable signals, scan input signal and circuit clock signal; The first output of described local scan enable signal maker is connected in the scan chain the with it scan input end of adjacent next scanning element, second is output as local scan enable signal, and described local scan enable signal is used for the scan enable end of scanning element in the driven sweep chain.
7. delay testing device according to claim 6, it is characterized in that described local scan enable signal maker comprise first, second and third trigger, selector switch and one or; Wherein said the first trigger is not connected with circuit-under-test, it is input as scan input signal and clock signal, output is connected to the second input end of selector switch, the output of described selector switch is connected to the input end of the second trigger, the output of the second trigger be connected to the input end of the 3rd trigger, described selector switch first input end and or the door first input end; The second input end described or door receives scan enable signals, and its output is connected to the selecting side of described selector switch, and exports local enable signal; The output of described the 3rd trigger is connected to the next scanning element of circuit-under-test scan chain.
8. delay testing device according to claim 7, it is characterized in that when displacement loads delay testing, the second trigger of described local scan enable signal maker is swept logic high when last clock period that scanning moves into, be loaded logic low when loading the clock period; Described local scan enable signal is turned to logic low along with the state turnover of the second trigger after loading the clock period; After catching the clock period, be turned to logic high with scan enable signals.
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| US8531225B1 (en) * | 2012-05-18 | 2013-09-10 | Mediatek Singapore Pte. Ltd. | Configurable critical path emulator |
| CN105067994B (en) * | 2015-09-15 | 2018-08-28 | 上海新储集成电路有限公司 | System sequence logic error, error rate calculating and its application process on locating plate |
| CN105629159B (en) * | 2015-12-31 | 2018-08-21 | 上海华虹宏力半导体制造有限公司 | The measuring circuit of the data setup time of d type flip flop |
| WO2018098773A1 (en) * | 2016-12-01 | 2018-06-07 | 华为技术有限公司 | Timing error detection circuit, trigger and latch |
| CN109188246B (en) * | 2018-09-06 | 2020-09-08 | 长沙理工大学 | Testability design structure of safe encryption chip |
| CN112230130A (en) * | 2020-08-12 | 2021-01-15 | 深圳先进技术研究院 | Monitoring sensor and chip |
| CN116106729B (en) * | 2023-02-10 | 2024-06-07 | 无锡玖熠半导体科技有限公司 | Scan chain and combinational logic fault diagnosis method based on cost loss factor |
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Application publication date: 20111019 Assignee: Zhongke Jianxin (Beijing) Technology Co.,Ltd. Assignor: Institute of Computing Technology, Chinese Academy of Sciences Contract record no.: X2022990000752 Denomination of invention: Signal stability detector and time delay test device Granted publication date: 20130403 License type: Exclusive License Record date: 20221009 |
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