CN106444505B - A kind of multi-channel synchronous signal acquiring system - Google Patents
A kind of multi-channel synchronous signal acquiring system Download PDFInfo
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- CN106444505B CN106444505B CN201610887154.6A CN201610887154A CN106444505B CN 106444505 B CN106444505 B CN 106444505B CN 201610887154 A CN201610887154 A CN 201610887154A CN 106444505 B CN106444505 B CN 106444505B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/21—Pc I-O input output
- G05B2219/21137—Analog to digital conversion, ADC, DAC
Abstract
The present invention provides a kind of multi-channel synchronous signal acquiring system, including analog module, data acquisition module and system control module；Wherein: the received acquired electromagnetic data of radio-frequency front-end is sent to the analog module through several channels；The analog module is for being sent to data acquisition module after amplifying acquired electromagnetic data；Amplified acquired electromagnetic data is further sent to system control module for acquiring, storing amplified acquired electromagnetic data by the data acquisition module；Start and stop of the system control module for data acquisition, storage in the data transmission between various modules of the initialization of system, control channel signal and the data acquisition module.The advantages of by the I/O pin abundant for making full use of FPGA to have and flexible logic unit, at least achievable data to 4 channel baseband signals of signal acquiring system of the invention acquire.
Description
Technical field
The present invention relates to electronic measuring technology fields, and in particular to a kind of multi-channel synchronous signal acquiring system.
Background technique
So that electronics, electrical equipment are widely used, adjoint electromagnetic environment occurs huge for the development of the communication technology
Big change causes concern of the people to EMC (concern of Electromagnetic Compatibility: Electro Magnetic Compatibility).It is right
For rail traffic, with the rapid development of high-speed rail technology, the electromagnetic environment of emu vehicle becomes increasingly complex, and surveys
The radiation characteristic of amount emu vehicle is to study the basic measures of its Electro Magnetic Compatibility.In order to guarantee human health and equipment,
The normal operation of system, international, country have formulated the electromagnetic compatibility standard about rail traffic.Under this major premise, with drive
The high development of dynamic system, communication system and control system is corresponding, how to measure and evaluate the electricity of high-speed EMUs vehicle
Magnetic radiation also becomes focus of attention.
The complexity of rail system and external environment makes its electromagnetic compatibility test simultaneously when the outer dimension and operation of vehicle
It is not easy to carry out in laboratory, and there are electromagnetic environment complexity, test when general place carries out test electromagnetic compatibility
The deficiencies of method is not easy to realize and test result is vulnerable to interference.Above-mentioned both sides limitation is so that at present for high-speed EMUs
There are biggish difficulty for the electromagnetic radiation measuring of whole vehicle.Common receiver carries out test measurement under environment at the scene at present
As a result, since by Environmental Noise Influence, there are large errors.
Summary of the invention
In view of this, the present invention provides a kind of multi-channel synchronous signal acquiring system, it is intended to when vehicle operates in practical electricity
Its radiation emission measurement signal is acquired when under magnetic environment.
The technical solution adopted by the present invention specifically:
A kind of multi-channel synchronous signal acquiring system, including analog module, data acquisition module and system control mould
Block；Wherein:
The received acquired electromagnetic data of radio-frequency front-end is sent to the analog module through several channels；
The analog module is for being sent to data acquisition module after amplifying acquired electromagnetic data；
The data acquisition module is used to acquire, store amplified acquired electromagnetic data, and further will be amplified
Acquired electromagnetic data is sent to system control module；
Initialization, control channel signal data transmission between various modules of the system control module for system
And the start and stop that data are acquired, stored in the data acquisition module.
It further include host computer in above-mentioned multi-channel synchronous signal acquiring system, on the one hand, in the order of the host computer
The system control module reads the amplified acquired electromagnetic data of the data acquisition module storage under control, on the other hand
Amplified acquired electromagnetic data is sent into the host computer by serial ports by the system control module, passes through the host computer
Application software completes checking and showing for data.
It further include power module in above-mentioned multi-channel synchronous signal acquiring system, for distinguishing to each chip of system
Direct current supply voltage is provided.
In above-mentioned multi-channel synchronous signal acquiring system, the analog module includes voltage reference chip, digital-to-analogue
Converter, at least one adjustable signal amplifying circuit (VGA) and several low-pass filters (LPF)；Wherein:
Radio-frequency front-end transmission acquired electromagnetic data successively through the adjustable signal amplifying circuit, the low-pass filter into
The signal condition of row amplification, filtering, the signal after the completion of signal condition are sent into the data acquisition module；
For the digital analog converter according to the instruction of the system control module received, output phase answers the control electricity of gain
Pressure, control adjustable signal amplifying circuit may amplify the signal to corresponding degree；
The voltage reference chip is used to provide reference voltage to the digital analog converter.
In above-mentioned multi-channel synchronous signal acquiring system, the analog module includes two adjustable signal amplification electricity
Road, the adjustable signal amplifying circuit are binary channels variable gain amplifier chip.
In above-mentioned multi-channel synchronous signal acquiring system, the analog module includes four low-pass filters.
In above-mentioned multi-channel synchronous signal acquiring system, the data acquisition module includes field programmable gate battle array
Arrange (FPGA), multiple analog-digital converters (ADC), clock distribution chip and static memory (SRAM) chip and configuration chip；Its
In:
The data that the analog-digital converter is used to export the low-pass filter sample, and sampled data is stored in existing
In first in, first out (FIFO) chip and external static memory chip inside field programmable logic gate array, and according to life
It enables the data read in static memory chip and data is uploaded to the system control module；
The clock distribution chip is used to for the clock output of the field programmable gate array being divided into be turned with modulus
The corresponding synchronised clock of parallel operation number supplies analog-digital converter described in each road simultaneously, guarantees the analog-digital converter acquisition data
Synchronism.
In above-mentioned multi-channel synchronous signal acquiring system, the system control module includes single-chip microcontroller and complex programmable
Logical device (CPLD)；Wherein:
The single-chip microcontroller parses the instruction of the host computer, controls the field programmable gate array and complexity respectively
Programmable logic device executes respective function respectively, and reads the data of the field programmable gate array, transmission
To the host computer；Wherein:
The function of the Complex Programmable Logic Devices are as follows: in the receiver system course of work, control signal acquisition system
The digital analog converter of system provides digital analog converter digital input code by programming.
In above-mentioned multi-channel synchronous signal acquiring system, the power module includes several voltage regulator chips, at least
The output voltage values of two voltage regulator chips are different,
In above-mentioned multi-channel synchronous signal acquiring system, the voltage regulator chip is linear voltage regulator chip.
The beneficial effect comprise that:
Multi-channel synchronous signal acquiring system of the invention is that the electromagnetic radiation characteristic of large scale system and Electro Magnetic Compatibility are ground
Study carefully and effective research method and experimental technique means are provided.The test site for solving EMU vehicle electromagnetic radiation measuring is wanted
It asks, realizes the live extract real-time of EMU vehicle ELECTROMAGNETIC RADIATION SIGNATURE.The system guarantees the synchronous acquisition of multiple signals
The phase of interchannel is consistent, convenient for carrying out algorithm process to data.It develops hence for subsequent based on blind signal processing theory
Separation EMU radiation signal and the fanaticism measuring receiver of ambient noise have great importance.
Detailed description of the invention
When considered in conjunction with the accompanying drawings, the present invention can be more completely and better understood.Attached drawing described herein is used to provide
A further understanding of the present invention, examples and descriptions thereof are used to explain the present invention, does not constitute improper limitations of the present invention.
Fig. 1 is a kind of structural block diagram of multi-channel synchronous signal acquiring system of the present invention；
Fig. 2 is a kind of structural schematic diagram of multi-channel synchronous signal acquiring system of the present invention；
Fig. 3 is the FPGA inner function module of data acquisition module in a kind of multi-channel synchronous signal acquiring system of the present invention
Structural schematic diagram；
Fig. 4 a is the simplification program of the CPLD of system control module in a kind of multi-channel synchronous signal acquiring system of the present invention
Functional block diagram；
Fig. 4 b is the program principle of the CPLD of system control module in a kind of multi-channel synchronous signal acquiring system of the present invention
Block diagram；
Fig. 5 is the simplified former of the FPGA program of data acquisition module in a kind of multi-channel synchronous signal acquiring system of the present invention
Manage block diagram.
Specific embodiment
The technical scheme of the present invention will be explained in further detail with reference to the accompanying drawings and embodiments.
The present invention provides a set of multi-channel signal acquiring system based on FPGA, CPLD and single-chip microcontroller, as shown in Figure 1, main
It to include analog module (1), data acquisition module (2), system control module (3) and power module (4)；Wherein:
The structure of analog module 1 is specific as shown in Fig. 2, mainly including 2 binary channels variable gain amplifier chips
(VGA), 1 digital analog converter (DAC), 1 voltage reference chip and 4 low-pass filters (LPF), compared to a piece of four-way
Road VGA chip uses two panels binary channels VGA in the present invention, not only avoids two antennas of radio-frequency front-end received two channel letter
Interfering with each other between number, and ensure that the consistency of each channel IQ two-way amplification.DAC is according in system control module
CPLD programs the digital input code that provides, and output phase answers the control voltage of gain, VGA may amplify the signal to degree appropriate according to
Process control switching range, by the electric signal of input be amplified to the comparable degree of range of analog-digital converter (ADC) chip, make
The effective accuracy of ADC is improved；And before filter circuit is then used directly in the ADC of data acquisition module, it is suppressed that letter to be collected
Number out-of-band high-frequency noise.
Further as shown in Fig. 2, data acquisition module is able to achieve the synchronous acquisition in 4 channels, FPGA is controlled according to system
The instruction control that the single-chip microcontroller of module is sent acquires, storage, transmits data, and uploads after transferring data to system control module
To host computer,
After starting acquisition tasks, ADC carries out high speed (50MSps) to the signal that 4 tunnel time domains export and samples, and sampled data is deposited
It stores up in first in, first out module (FIFO) and static memory (SRAM) chip inside FPGA, and SRAM is read according to order
In data and upload to host computer.
Voltage reference chip provides reference voltage to DAC, and output voltage 2.5V should with 0.05% voltage accuracy
The precision of chip determines the precision of DAC output voltage, while also determining the gain accuracy of VGA.
The programming information power down of FPGA is lost, it is therefore desirable to be re-downloaded configuration data when system powers on every time, be configured
Chip is responsible for storing the configuration data of FPGA, and data are kept after power-off, power on automatic load.
The FPGA structure block diagram of 4 channel datas acquisition is as shown in Figure 3:
FPGA mainly includes following five most of: clock frequency division module (altpll0), command analysis module (decode),
Adc data acquisition module (write), SRAM control unit (ram) and data read module (mcuread)；Wherein:
External 100MHz clock is divided into the 50MHz clock output of difference form all the way by clock frequency division module, passes through FPGA
External clock distribution chip is divided into the 50MHz clock of the synchronization of two-pass DINSAR, while supplying two-way ADC, to guarantee
The synchronism of two-way ADC acquisition；
Command analysis module receives the instruction sent of single-chip microcontroller and decodes to it, control adc data acquisition module into
The acquisition of row data, and readback of the completion to storing data under the control of host computer；
Adc data acquisition module be responsible for the digital signal that two panels double channel A/D C is converted carry out parallel synchronous acquisition and
It keeps in, and four circuit-switched datas is arranged successively into the digital signal of High Data Rate all the way, send SRAM control unit to；
SRAM control unit is responsible for completing the communication work to sram chip.The address according to provided by prime will be current
Digital signal is stored in sram chip, or the data in the address of reading back；
Data read module is responsible for controlling the read work of data in sram chip, it is according to the finger of command analysis module
It enables, the address of data in required sram chip is communicated to sram chip.The internal processes of FPGA are as shown in Figure 5.
Further as shown in Fig. 2, system control module 3 includes single-chip microcontroller and CPLD, main control of the single-chip microcontroller as system
Device, major function are to parse the instruction of host computer, and control FPGA and CPLD executes respective function respectively, and it is right to read acquisition data
After be transferred to host computer；Wherein:
In the receiver system course of work, the DAC of the control signal acquiring system of CPLD and the devices such as PLL of radio-frequency front-end
Part works normally；CPLD and FPGA programme diagram is further as shown in Fig. 4 a-4b and Fig. 5, in figs 4 a and 4b, clk, clkmcu,
The input pins such as encpld, addr, data connect single-chip microcontroller, issue command adapted thereto by single-chip microcontroller and control PLL and DAC, and in Fig. 5
In, command analysis module is responsible for MCU Instruction decoding, for controlling data acquisition module and data read module work, SRAM
The relevant interface that control module is each responsible for reading data in data write-in SRAM and from SRAM correctly matches.It can be seen that
Initialization, signal condition, acquisition storage start and stop and the data transmission of system all carry out under the control of system control module.
Power module include 5 output different voltages value linear voltage regulator chips, in the present embodiment, this system it is each
Chip is respectively necessary for the direct current supply voltage of 5V, 3.3V, 2.5V, 1.8V, 1.2V.Pass through external DC source or power supply adaptor
After 220V alternating current is converted to 9V direct current, 5V output is converted to by linear voltage regulator chip, then be respectively converted by 5V
3.3V,2.5V,1.8V,1.2V.As a kind of preferred embodiment, the linear voltage regulator chip in the present invention uses LDO chip, and 5
A chip selects the LT1085-5 chip of output electric current 3A respectively, exports the LT1085-3.3 chip of electric current 3A, exports electric current
The LT1963-1.8 chip of 1.5A exports the LP3891-1.2 chip and LM4132A-2.5 voltage reference core of electric current 800mA
Piece.The linear voltage regulator chip that different voltages value is exported by 5 ensure that power module exports stable and accurate voltage.
Signal acquiring system of the invention is completed using 2 binary channels variable gain amplifier chips to 4 groups of channel signals
Adjustable amplification, that is, ensure that a consistency for signal amplification in group, and can neatly control the times magnification of two groups of signals respectively
Number.
In conjunction with the needs of blind signal processing algorithm in practical application, the radio-frequency front-end of receiver system is to two-way 30MHz-
The electromagnetic signal of 1GHz is received, and the high-frequency signal of every 10MHz bandwidth is down-converted to base band with 10MHz stepping and is transformed to
IQ two-way.Multi-channel signal acquiring system of the invention takes full advantage of the I/O pin abundant and flexible logic list of FPGA
Member completes the data collection task to 4 channel baseband signals.System control module parses host computer instruction, and controls simulation
Circuit module amplifies filtering to the analog signal of input, is believed by ADC analog-digital converter in control data acquisition module simulation
Number sampled, FPGA by the digital signal real-time storage after conversion in sram.System control module is in host computer order
The lower data for reading FPGA storage of control, and data are sent into host computer by serial ports, data are completed by upper computer software
The functions such as check and show.
In conjunction with attached drawing, embodiments of the present invention are described in detail above, and attached drawing herein is for providing to this
Invention is further understood.Obviously, the foregoing is merely the preferable specific embodiment of the present invention, but protection scope of the present invention
Be not limited thereto, it is any be to one skilled in the art can readily occur in, essentially without be detached from it is of the invention
Change or replacement are also all included in the scope of protection of the present invention.
Claims (4)
1. a kind of multi-channel synchronous signal acquiring system, which is characterized in that including analog module, data acquisition module and be
System control module；Wherein:
The received acquired electromagnetic data of radio-frequency front-end is sent to the analog module through several channels；
The analog circuit includes two adjustable signal amplifying circuits and voltage reference chip, the adjustable signal amplification electricity
Road is that binary channels variable gain amplifier chip and four low-pass filters, low-pass filter are used directly in data acquisition module
Before ADC, that is, analog-digital converter；The analog module is for being sent to data acquisition module after amplifying acquired electromagnetic data
Block；
The data acquisition module is used to acquire, store amplified acquired electromagnetic data, and further by amplified electromagnetism
Signal data is sent to system control module, wherein the data acquisition module includes field programmable gate array, two-way
ADC, clock distribution chip and static memory chip；Wherein:
For the analog-digital converter for sampling to the data of the low-pass filter, sampled data is stored in field-programmable
In FIFO and external static memory chip inside logic gate array, and according in order reading static memory chip
Data and data are uploaded to the system control module；
The clock distribution chip is used to for the clock output of the field programmable gate array being divided into and analog-digital converter
The corresponding synchronised clock of number, while two-way ADC is supplied, guarantee the synchronism of the analog-digital converter acquisition data；
The field programmable gate array includes five most of: clock frequency division module, command analysis module, adc data are adopted
Collect module, static memory chip control module and data read module；Wherein:
External 100MHz clock is divided into the 50MHz clock output of difference form all the way by clock frequency division module, can be compiled by scene
Clock distribution chip outside journey logic gate array is divided into the 50MHz clock of the synchronization of two-pass DINSAR, while supplying two-way
ADC, to guarantee the synchronism of two-way ADC acquisition；
Command analysis module receives the instruction that single-chip microcontroller is sent and decodes to it, and control adc data acquisition module is counted
According to acquisition, and readback of the completion to storing data under the control of host computer；
Adc data acquisition module is responsible for the digital signal converted to two panels double channel A/D C and carries out parallel synchronous acquisition and keep in,
And four circuit-switched datas are arranged successively into the digital signal of High Data Rate all the way, send static memory chip control module to；
Static memory chip control module is responsible for completing the communication work to static memory chip, according to provided by prime
Current digital signal is stored in static memory chip by address, or the data in the address of reading back；
Data read module is responsible for controlling the read work of data in static memory chip, it is according to the finger of command analysis module
It enables, the address of data in required static memory chip is communicated to static memory chip；
The system control module includes single-chip microcontroller and Complex Programmable Logic Devices, initialization, control channel for system
Signal between various modules data transmission and the data acquisition module in data acquisition, storage start and stop, in which:
The single-chip microcontroller parses the instruction of the host computer, and controlling the field programmable gate array and complexity respectively can compile
Journey logical device executes respective function respectively, and reads the data of the field programmable gate array, is transferred to institute
State host computer；Wherein:
The function of the Complex Programmable Logic Devices are as follows: in the receiver system course of work, control signal acquiring system
Digital analog converter provides digital analog converter digital input code by programming.
2. multi-channel synchronous signal acquiring system according to claim 1, which is characterized in that further include host computer, a side
Face, the system control module reads the amplified of the data acquisition module storage under the order control of the host computer
Acquired electromagnetic data, on the other hand amplified acquired electromagnetic data is sent on described by the system control module by serial ports
Position machine completes checking and showing for data by the application software of the host computer.
3. multi-channel synchronous signal acquiring system according to claim 2, which is characterized in that the analog module packet
Include voltage reference chip, digital analog converter, two adjustable signal amplifying circuits and four low-pass filters；Wherein:
The acquired electromagnetic data of radio-frequency front-end transmission is successively put through the adjustable signal amplifying circuit, the low-pass filter
Greatly, the signal condition filtered, the signal after the completion of signal condition are sent into the data acquisition module；
The digital analog converter answers the control voltage of gain according to the instruction of the system control module received, output phase,
Control adjustable signal amplifying circuit may amplify the signal to corresponding degree；
The voltage reference chip is used to provide reference voltage to the digital analog converter.
4. multi-channel synchronous signal acquiring system according to claim 1, which is characterized in that further include power module, use
In providing direct current supply voltage respectively to each chip of system.
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| CN110873632B (en) * | 2020-01-17 | 2020-08-04 | 中国铁道科学研究院集团有限公司铁道建筑研究所 | Differential pressure type dynamic disturbance sensor based on wireless and monitoring system |
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| CN114265031A (en) * | 2021-12-03 | 2022-04-01 | 电子科技大学 | High-speed real-time data acquisition system of radar in well based on FPGA |
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