CN104270154B - Sampling apparatus and the method for sampling based on parallel processing - Google Patents
Sampling apparatus and the method for sampling based on parallel processing Download PDFInfo
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Abstract
The invention discloses a kind of sampling apparatus and the method for sampling based on parallel processing.The method of sampling includes：Input signal is received, the sample waveform consistent with input signal is remained in each period tracking input signal of the first sampling clock, and by output；The sample waveform exported in each cycle of the first sampling clock is received by a plurality of path respectively, control each period tracking sample waveform of a plurality of path respectively in the second sampling clock, and output is remained into sample waveform respectively, wherein, multiple second sampling clocks drive a path respectively, the frequency of multiple second sampling clocks is equal and frequency sum is equal to the frequency of the first sampling clock, and the phase of multiple second sampling clocks staggers a cycle of the first sampling clock successively；Data fusion is carried out to the sample waveform of multiple-channel output, obtains the wideband sampling signal consistent with the first sample clock frequency.The present invention can suppress caused non-homogeneous error during parallel sampling before signal sampling completion.
Description
Technical field
The present invention relates to technical field of signal sampling, especially a kind of sampling apparatus and sampling side based on parallel processing
Method.
Background technology
In current broadband reception system, IBW (instant bandwidth, Instantaneous Bandwidth) and DR (dynamic models
Enclose, dynamic range) it is increasingly becoming the bottleneck problem of signal reception.And ADC (analog/digital converter, Analog to
Digital Converter) core devices as broadband reception, its technological level turns into limitation IBW and DR technical indicators
Principal element.In the case where ADC technical indicator can not be lifted, frequency band folding sampling, compression sampling, single-bit sampling just into
To expand the Main Means of signal acquisition bandwidth.However, frequency range folding sampling can make radio-frequency channel become increasingly complex and can damage
Lose system sensitivity；It is corresponding openness that compression sampling then requires that signal has；Single-bit samples the meeting in signal amplitude, phase
Lose and system dynamic is low.These all can limited samples systematic difference scope.
In the prior art, the common approach for improving digital sample real-time bandwidth is to use parallel organization.Parallel organization refers to
Time-interleaved sampling is carried out using multi-channel A/D C, the approach can make sample rate double, and M pieces ADC compared with low sampling rate to believe input
The sampling of number time-interleaved, whole-sample rate can reach M times of monolithic ADC.But using parallel organization there is also shortcoming, by
The factors such as the otherness of the sampling clock between multi-channel A/D C can unavoidably produce non-homogeneous mistake during parallel sampling
Difference, so as to produce parasitic spectral peak, if not being acted upon, the DR of sampling system will be had influence on.Meanwhile greatly improved in sample rate
In the case of, analog bandwidth limited monolithic ADC again limits the application of sampling system.
To solve the problems, such as non-homogeneous error, traditional processing method be in multi-channel A/D C sampled data splicings,
Non-homogeneous error is compensated in a manner of digital processing.Although this kind of method is more excellent to the compensation effect of the non-homogeneous error of system
It is good, but need to carry out more operand and take more process resource, the real-time generation to sampling system is larger
Influence, it is even more important the problem of be, non-homogeneous error compensation is carried out on the premise of signal sampling has been completed, only
It is to make certain amendment and compensation to the sampled data with error, fails fundamentally solve multi-channel A/D C progress parallel sampling mistakes
Caused by Cheng Zhonghui the problem of non-homogeneous error, the fidelity of sampled signal can still be influenceed by non-homogeneous error.
The content of the invention
The technical problems to be solved by the invention are：For above-mentioned problem, there is provided a kind of based on parallel processing
Sampling apparatus and the method for sampling.
The technical solution adopted by the present invention is：A kind of sampling apparatus based on parallel processing, the sampling apparatus bag are provided
Primary sampling unit, two level sampling unit, Clock Managing Unit and data integrated unit are included, wherein：The Clock Managing Unit
The first sampling clock is provided to primary sampling unit, provides multiple second sampling clocks to two level sampling unit, multiple second adopt
The frequency of sample clock is equal and frequency sum is equal to the frequency of the first sampling clock, and the phase of multiple second sampling clocks is successively
Stagger a cycle of the first sampling clock；The primary sampling unit receives input signal, in each of the first sampling clock
Period tracking input signal, and output is remained into the sample waveform consistent with input signal；The two level sampling unit passes through
A plurality of path receives the sample waveform in the output of each cycle of the first sampling clock respectively, controls a plurality of path respectively second
Each period tracking sample waveform of sampling clock, and output is remained into sample waveform respectively, wherein, during multiple second samplings
Clock drives a path respectively；The data fusion unit carries out data fusion to the sample waveform of multiple-channel output, obtains and the
The consistent wideband sampling signal of one sample clock frequency.
Preferably, each cycle of first sampling clock and the second sampling clock is divided into tracking phase and keeps rank
Section, the tracking phase of every one second sampling clock are at least partially disposed at the holding stage of the first sampling clock, wherein：The primary
The tracking phase that sampling unit was specifically used in each cycle of the first sampling clock tracks the input signal, and is keeping rank
Output is remained the sample waveform consistent with input signal by section, untill the tracking phase until next cycle arrives；Described two
The tracking phase that level sampling unit is specifically used for controlling a plurality of path respectively in each cycle of the second sampling clock tracks primary
The sample waveform that sampling unit exports in the different cycles of the first sampling clock, and output is remained respectively in the holding stage and adopted
Sample waveform.
Preferably, the sampling apparatus also includes matching unit, and the matching unit is used to receive the primary sampling list
The sample waveform that member exports in each cycle of the first sampling clock, and it is sent into described two after carrying out Signal Matching to sample waveform
Level sampling unit.
Preferably, the process of the Signal Matching comprises at least power distribution, impedance matching, amplitude range matching and phase
Relationship match.
Preferably, the sampling apparatus also includes signal condition unit, and the signal condition unit is described defeated for receiving
Enter signal, and the primary sampling unit is sent into after nursing one's health the input signal, so that input signal meets primary and adopted
The reception requirement of sample unit.
The technical solution adopted by the present invention is：A kind of method of sampling based on parallel processing, the method for sampling bag are provided
Include：Input signal is received, is remained and input signal in each period tracking input signal of the first sampling clock, and by output
Consistent sample waveform；The sample waveform exported in each cycle of the first sampling clock, control are received by a plurality of path respectively
A plurality of path is made respectively in each period tracking sample waveform of the second sampling clock, and output is remained into sampling ripple respectively
Shape, wherein, multiple second sampling clocks drive a path respectively, and the frequency of multiple second sampling clocks is equal and frequency sum
Phase equal to the frequency of the first sampling clock, and multiple second sampling clocks staggers week of the first sampling clock successively
Phase；Data fusion is carried out to the sample waveform of multiple-channel output, obtains the wideband sampling consistent with first sample clock frequency
Signal.
Preferably, each cycle of first sampling clock and the second sampling clock is divided into tracking phase and keeps rank
Section, the tracking phase of every one second sampling clock are at least partially disposed at the holding stage of the first sampling clock, wherein：It is described
Each period tracking input signal of one sampling clock, and the step of remaining the sample waveform consistent with input signal will be exported
Specially：The input signal is tracked in the tracking phase in each cycle of the first sampling clock, and will be exported in the stage of holding
The sample waveform consistent with input signal is remained, untill the tracking phase until next cycle arrives；The control is a plurality of logical
Road has the step of output is remained into sample waveform respectively respectively in each period tracking sample waveform of the second sampling clock
Body is：Tracking phase of a plurality of path respectively in each cycle of the second sampling clock is controlled to track primary sampling unit first
The sample waveform of the different cycles output of sampling clock, and output is remained into sample waveform respectively in the holding stage.
Preferably, by a plurality of path receive respectively the first sampling clock each cycle export sample waveform it
Before, the method for sampling also includes：Signal Matching is carried out to the sample waveform of the output of each cycle in the first sampling clock.
Preferably, the process of the Signal Matching comprises at least power distribution, impedance matching, amplitude range matching and phase
Relationship match.
Preferably, after input signal is received, the method for sampling also includes：The input signal is nursed one's health.
In summary, by adopting the above-described technical solution, the beneficial effects of the invention are as follows：By primary sampling unit with
High sampling rate is sampled, and two level sampling unit sets a plurality of path to carry out time-interleaved sampling, two level with low sampling rate
The object of sampling unit sampling is the sample waveform of primary sampling unit output, and the sample waveform of primary sampling unit is at one
It can keep constant in cycle, therefore non-homogeneous error will not be produced in two level sampling unit sampling process, so as in signal
Sampling suppresses caused non-homogeneous error during parallel sampling before completing, and sampled signal has higher fidelity, can be with
Digital sample bandwidth and raising sampled signal are improved without false dynamic range.
Brief description of the drawings
Examples of the present invention will be described by way of reference to the accompanying drawings, wherein：
Fig. 1 is the structured flowchart of the sampling apparatus based on parallel processing of the embodiment of the present invention.
Fig. 2 is the sampling time sequence figure of the primary sampling unit and two level sampling unit in Fig. 1.
Fig. 3 be using prior art parallel sampling data fusion after with using the present invention the sampling based on parallel processing
Spectral contrast figure after the sample waveform fusion of device.
Fig. 4 is the schematic flow sheet of the method for sampling based on parallel processing of the embodiment of the present invention.
Embodiment
All features disclosed in this specification, or disclosed all methods or during the step of, except mutually exclusive
Feature and/or step beyond, can combine in any way.
Any feature disclosed in this specification, unless specifically stated otherwise, can be equivalent by other or with similar purpose
Alternative features are replaced.I.e., unless specifically stated otherwise, each feature is an example in a series of equivalent or similar characteristics
.
As shown in figure 1, it is the structured flowchart of the sampling apparatus based on parallel processing of the embodiment of the present invention.The present embodiment
Sampling apparatus based on parallel processing includes primary sampling unit 1, two level sampling unit 2, Clock Managing Unit 3 and data fusion
Unit 4.
Clock Managing Unit 3 provides the first sampling clock to primary sampling unit 1, is provided to two level sampling unit 2 multiple
Second sampling clock, the frequency of multiple second sampling clocks is equal and frequency sum is equal to the frequency of the first sampling clock, and more
The phase of individual second sampling clock staggers a cycle of the first sampling clock successively.Wherein, the frequency of the first sampling clock with
The frequency of second sampling clock is multiple proportion, and multiple is equal to the quantity of the second sampling clock.Multiple second sampling clocks
After phase staggers successively, a cycle of corresponding first sampling clock of initial phase of first the second sampling clock, second
The second period of corresponding first sampling clock of the initial phase of individual second sampling clock, the 3rd the second sampling clock it is initial
3rd cycle of corresponding first sampling clock of phase, by that analogy.
Primary sampling unit 1 receives input signal, in each period tracking input signal of the first sampling clock, and will be defeated
Go out to remain the sample waveform consistent with input signal.Wherein, input signal is high frequency or intermediate-freuqncy signal, primary sampling unit 1
Start to sample after receiving input signal.Primary sampling unit 1 the first sampling clock first period tracking input signal,
And the signal for remaining and tracing into, i.e., sample waveform consistent with input signal will be exported.Primary sampling unit 1 is every afterwards
One cycle repeated same operation.It should be noted that the waveform of input signal is at any time in change, so primary sampling is single
Member 1 the first sampling clock each period tracking to signal be probably different, and then keep signal be also likely to be not
With.
Two level sampling unit 2 receives the sampling ripple exported in each cycle of the first sampling clock respectively by a plurality of path
Shape, each period tracking sample waveform of a plurality of path respectively in the second sampling clock is controlled, and output is remained adopted respectively
Sample waveform, wherein, multiple second sampling clocks drive a path respectively.The quantity of a plurality of path is at least 2.A plurality of path can
Be multi-disc independence ADC chips or a piece of ADC chips in multiple parallel ADC channels.Although a plurality of path is simultaneously
The sample waveform of the output of each cycle of the first sampling clock is received, but each path is by the second different sampling clocks
Driving, then in some cycle of the first sampling clock, an only path is tracking primary sampling unit 1 in cycle output
Sample waveform, that is to say, that a plurality of path in two level sampling unit 2 be in time by time-interleaved sample in a manner of it is complete
The double sampling for the signal that paired initial samples unit 1 is kept, the tracking of two level sampling unit 2 and the detailed process that keeps with
The tracking of primary sampling unit 1 is identical with the detailed process kept, and here is omitted.
Data fusion unit 4 carries out data fusion to the sample waveform of multiple-channel output, obtains and the first sample clock frequency
Consistent wideband sampling signal.Wherein, data fusion unit 4 according to each path in two level sampling unit 2 the second sampling clock
Phase relation carry out data gradually interweave, be integrated into the broadband consistent with the sample clock frequency of initial samples unit 1 first and adopt
Sample signal.
Alternatively, sampling apparatus can also include matching unit 5 and signal condition unit 6.Matching unit 5 is used to receive just
Level sampling unit 1 the first sampling clock each cycle export sample waveform, and to sample waveform carry out Signal Matching after
It is sent into two level sampling unit 2.The process of Signal Matching comprises at least power distribution, impedance matching, amplitude range matching and phase
Relationship match.Matching unit 5 mainly completes the power distribution that single channel (initial samples unit 1) arrives multichannel (two level sampling unit 2),
And ensure the port Impedance of front stage, phase matched.The realization of matching unit 5 can have two methods：First, pass through resistance net
Network builds match circuit of the front and rear single channel to multichannel；Second, completing the coupling of signal by transformer, the how defeated of front stage is realized
Enter the matching of output port.
Signal condition unit 6 is used to receive input signal, and primary sampling unit is sent into after nursing one's health input signal
1, so that input signal meets the reception requirement of primary sampling unit 1.Signal condition unit 6 receives prior to primary sampling unit 1
Input signal, mainly complete to the amplitude of input signal, the conditioning of band limits, coupled modes, input signal is met primary
The reception requirement of the input port of sampling unit 1.
Specifically, please also refer to Fig. 1 and Fig. 2.In fig. 2, the first sampling clock clk and the second sampling clock
Each cycle of (clk1, clk2 ..., clkM) is divided into tracking phase and holding stage, and tracking phase is in a cycle
High level lasting time, it is the low duration in a cycle to be kept for the stage.And every one second sampling clock with
The track stage is at least partially disposed at the holding stage of the first sampling clock, as shown in Fig. 2 the second sampling clock clk1 high level
Trailing edge lags compared to the trailing edge of the first sampling clock clk high level, and is at least partially disposed at the first sampling clock clk
Low level.The trailing edge of second sampling clock clk2 to clkM high level is also at least partially disposed at the first sampling clock clk
Low level.
The tracking phase that primary sampling unit 1 is specifically used in each cycle of the first sampling clock tracks input signal,
And will be exported in the holding stage and remain the sample waveform consistent with input signal, until the tracking phase arrival in next cycle is
Only.Two level sampling unit 2 be specifically used for controlling a plurality of path respectively the second sampling clock each cycle tracking phase with
The sample waveform that track primary sampling unit 1 exports in the different cycles of the first sampling clock, and respectively will output in the stage of holding
Remain sample waveform.
Wherein, it is difficult to ensure that uniformly dividing between each ADC sampling clocks that the mode of prior art is sampled due to time-interleaved
The phase relation matched somebody with somebody, non-homogeneous error can be unavoidably produced when being merged to multichannel data.And provided in the present embodiment
It is signal constant, that two level sampling unit 2 traces into that primary sampling unit 1, which keeps the signal of stage output in each cycle,
It is constant, then can suppresses the non-homogeneous error of parallel sampling brought due to the change of the phase relation of sampling clock.
As an example it is assumed that input signal is 0 to 2 stairstep signal, stepping length is 0.1.The number of second sampling clock
Measure as 5, primary sampling unit 1 divides to be sampled for 5 cycles, and two level sampling unit 2 divides for 5 paths.Primary sampling is single
Member 1 starts to trace into 0 in a cycle, and it is 0 to keep output；0.5 is traced into second period, and keeps the output to be
0.5；In the 3rd period tracking to 1, and it is 1 to keep output；In the 4th period tracking to 1.5, and it is 1.5 to keep output；
In the 5th period tracking to 2, and it is 2 to keep output.
First path of two level sampling unit 2 receives primary sampling at the end of the tracking phase of the second sampling clock
Unit 1 keeps the 0 of output, then the signal 0 that first path can only trace into, and it is 0 to keep output, likewise, Article 2
The signal 0.5 that path can only trace into, and it is 0.5 to keep output；The signal 1 that Article 3 path can only trace into, and keep defeated
Go out for 1；The signal 1.5 that Article 4 path can only trace into, and it is 1.5 to keep output；The letter that Article 5 path can only trace into
Numbers 2, and it is 2 to keep output.
The multiple-channel output of two level sampling unit 2 is respectively 0,0.5,1,1.5,2, then data fusion unit 4 carries out data
The discrete series of (0,0.5,1,1.5,2) is obtained after fusion.
Referring again to Fig. 3, A is using the spectrogram after the parallel sampling data fusion of prior art in Fig. 3, and B is to adopt
Spectrogram after being merged with the sample waveform of the sampling apparatus based on parallel processing of the present invention, in a kind of embodiment of the present invention
Specific implementation process in, the sampling clock clk frequencies that set primary sampling unit 1 are Fs=3GSPS, two level sampling unit 2
Path be two, sampling clock clk1, clk2 frequency are Fs/2=1.5GSPS, frequency input signal 2100MHz.From figure
In it can clearly be seen that using sampling apparatus of the present invention carry out sample waveform fusion after, frequency spectrum is spuious substantially to diminish, hence it is evident that raising
Signal sampling without false dynamic range.
As shown in figure 4, it is the schematic flow sheet of the method for sampling based on parallel processing of the embodiment of the present invention.The present embodiment
The method of sampling based on parallel processing include：
S1：Receive input signal, in each period tracking input signal of the first sampling clock, and by output remain with
The consistent sample waveform of input signal.
Wherein, input signal is high frequency or intermediate-freuqncy signal, starts to sample after receiving input signal.In the first sampling clock
First period tracking input signal, and remain the signal that traces into by exporting, i.e., sampling ripple consistent with input signal
Shape, and same operation is repeated in each cycle afterwards.It should be noted that the waveform of input signal is to change at any time
, thus the first sampling clock each period tracking to signal be probably different, and then keep signal may also
It is different.
S2：The sample waveform exported in each cycle of the first sampling clock is received by a plurality of path respectively, control is more
Bar path respectively in each period tracking sample waveform of the second sampling clock, and output is remained into sample waveform respectively, its
In, multiple second sampling clocks drive a path respectively, and the frequency of multiple second sampling clocks is equal and frequency sum is equal to
The frequency of first sampling clock, and the phase of multiple second sampling clocks staggers a cycle of the first sampling clock successively.
Wherein, the quantity of a plurality of path is at least 2.A plurality of path can be the ADC chips or one of multi-disc independence
Multiple parallel ADC channels in piece ADC chips.Although a plurality of path receives the output of each cycle of the first sampling clock simultaneously
Sample waveform, but each path is driven by different the second sampling clock, then in some week of the first sampling clock
The sample waveform that phase, only a path export in tracking in the cycle, that is to say, that a plurality of path is in time with parallel
The mode of alternating sampling completes the double sampling of the sample waveform of the output of each cycle to the first sampling clock.
S3：Data fusion is carried out to the sample waveform of multiple-channel output, obtains the broadband consistent with the first sample clock frequency
Sampled signal.
Wherein, data are carried out according to the phase relation of the second sampling clock of each bar path gradually to interweave, can be integrated into
The wideband sampling signal consistent with the first sample clock frequency.
In the present embodiment, the sampling ripple exported in each cycle of the first sampling clock is received by a plurality of path respectively
Before shape, the method for sampling also includes：Signal Matching is carried out to the sample waveform of the output of each cycle in the first sampling clock.
The process of Signal Matching comprises at least power distribution, impedance matching, amplitude range matching and phase relation matching.
Single channel is mainly completed with process to the power distribution of multichannel, and ensures the port Impedance of front stage, phase matched.Signal Matching
Realization can have two methods：First, match circuit of the front and rear single channel to multichannel is built by resistor network；Second, pass through transformation
Device completes the coupling of signal, realizes the matching of the Multiinputoutput port of front stage.
After input signal is received, the method for sampling also includes：Input signal is nursed one's health.Carried out again after being nursed one's health
The sample waveform consistent with input signal is remained in each period tracking input signal of the first sampling clock, and by output.
The process of conditioning mainly completes the conditioning of the amplitude to input signal, band limits, coupled modes, input signal is subsequently inputted
The reception requirement of port.
By the above-mentioned means, the sampling apparatus based on parallel processing and the method for sampling of the embodiment of the present invention are adopted by primary
Sample unit is sampled with high sampling rate, and two level sampling unit sets a plurality of path to carry out time-interleaved with low sampling rate and adopted
Sample, the object of two level sampling unit sampling is the sample waveform of primary sampling unit output, and the sampling ripple of primary sampling unit
Shape can keep constant in a cycle, therefore will not produce non-homogeneous error in two level sampling unit sampling process, so as to
Enough caused non-homogeneous errors during suppressing parallel sampling before signal sampling completion, sampled signal have higher fidelity
Degree, digital sample bandwidth and raising sampled signal can be improved without false dynamic range.Compared to existing non-homogeneous error school
Positive technology has more preferable real-time, and is not take up extra process resource, and directly suppresses to adopt parallel from signal sampling source
The generation of the non-homogeneous error of sample.
The invention is not limited in foregoing embodiment.The present invention, which expands to, any in this manual to be disclosed
New feature or any new combination, and disclose any new method or process the step of or any new combination.
Claims (10)
1. a kind of sampling apparatus based on parallel processing, it is characterised in that the sampling apparatus includes primary sampling unit, two level
Sampling unit, Clock Managing Unit and data integrated unit, wherein：
The Clock Managing Unit provides the first sampling clock to primary sampling unit, and multiple second is provided to two level sampling unit
Sampling clock, the frequency of multiple second sampling clocks is equal and frequency sum is equal to the frequency of the first sampling clock, and multiple the
The phase of two sampling clocks staggers successively, and the interval time of two neighboring second sampling clock is a week of the first sampling clock
Phase；
The primary sampling unit receives input signal, in each period tracking input signal of the first sampling clock, and will be defeated
Go out to remain the sample waveform consistent with input signal；
The two level sampling unit receives the sampling ripple exported in each cycle of the first sampling clock respectively by a plurality of path
Shape, each period tracking sample waveform of a plurality of path respectively in the second sampling clock is controlled, and output is remained adopted respectively
Sample waveform, wherein, multiple second sampling clocks drive a path respectively；
The data fusion unit carries out data fusion to the sample waveform of multiple-channel output, obtains and the first sample clock frequency one
The wideband sampling signal of cause.
2. sampling apparatus according to claim 1, it is characterised in that first sampling clock and the second sampling clock
Each cycle is divided into tracking phase and holding stage, and the tracking phase of every one second sampling clock is at least partially disposed at first and adopted
The holding stage of sample clock, wherein：
The primary sampling unit is specifically used for the tracking phase tracking input letter in each cycle of the first sampling clock
Number, and will be exported in the holding stage and remain the sample waveform consistent with input signal, until the tracking phase in next cycle arrives
Untill coming；
The two level sampling unit be specifically used for controlling a plurality of path respectively the second sampling clock each cycle tracking rank
Section tracks the sample waveform that primary sampling unit exports in the different cycles of the first sampling clock, and respectively will be defeated in the stage of holding
Go out to remain sample waveform.
3. sampling apparatus according to claim 1, it is characterised in that the sampling apparatus also includes matching unit, described
Matching unit is used to receive the sample waveform that the primary sampling unit exports in each cycle of the first sampling clock, and to adopting
Sample waveform is sent into the two level sampling unit after carrying out Signal Matching.
4. sampling apparatus according to claim 3, it is characterised in that the process of the Signal Matching is including at least power point
Match somebody with somebody, impedance matching, amplitude range matching and phase relation matching.
5. sampling apparatus according to claim 1, it is characterised in that the sampling apparatus also includes signal condition unit,
The signal condition unit is used to receive the input signal, and the primary is sent into after nursing one's health the input signal and is adopted
Sample unit, so that input signal meets the reception requirement of primary sampling unit.
6. a kind of method of sampling based on parallel processing, it is characterised in that the method for sampling includes：
Input signal is received, in each period tracking input signal of the first sampling clock, and output is remained and believed with inputting
Number consistent sample waveform；
The sample waveform exported in each cycle of the first sampling clock is received by a plurality of path respectively, controls a plurality of path point
Not in each period tracking sample waveform of the second sampling clock, and output is remained into sample waveform respectively, wherein, Duo Ge
Two sampling clocks drive a path respectively, when the frequency of multiple second sampling clocks is equal and frequency sum is equal to the first sampling
The frequency of clock, and the phase of multiple second sampling clocks staggers successively, interval time of two neighboring second sampling clock are the
The a cycle of one sampling clock；
Data fusion is carried out to the sample waveform of multiple-channel output, obtains the wideband sampling consistent with first sample clock frequency
Signal.
7. the method for sampling according to claim 6, it is characterised in that first sampling clock and the second sampling clock
Each cycle is divided into tracking phase and holding stage, and the tracking phase of every one second sampling clock is at least partially disposed at first and adopted
The holding stage of sample clock, wherein：
Each period tracking input signal in the first sampling clock, and output is remained into consistent with input signal adopt
The step of sample waveform is specially：The input signal is tracked in the tracking phase in each cycle of the first sampling clock, and is being protected
Hold the stage by export remain the sample waveform consistent with input signal, until next cycle tracking phase arrival untill；
The a plurality of path of control respectively keeps output respectively in each period tracking sample waveform of the second sampling clock
It is specially for the step of sample waveform：Tracking phase of a plurality of path respectively in each cycle of the second sampling clock is controlled to track
The sample waveform that primary sampling unit exports in the different cycles of the first sampling clock, and respectively keep output in the stage of holding
For sample waveform.
8. the method for sampling according to claim 6, it is characterised in that received respectively by a plurality of path when first samples
Before the sample waveform of the output of each cycle of clock, the method for sampling also includes：
Signal Matching is carried out to the sample waveform of the output of each cycle in the first sampling clock.
9. the method for sampling according to claim 8, it is characterised in that the process of the Signal Matching is including at least power point
Match somebody with somebody, impedance matching, amplitude range matching and phase relation matching.
10. the method for sampling according to claim 6, it is characterised in that after input signal is received, the method for sampling
Also include：
The input signal is nursed one's health.
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| US9496887B1 (en) * | 2015-05-12 | 2016-11-15 | Microchip Technology Incorporated | Analog to digital converter with internal timer |
| CN111077821A (en) * | 2019-12-24 | 2020-04-28 | 北京百度网讯科技有限公司 | Method and device for collecting data and single chip microcomputer |
| CN113033722B (en) * | 2021-05-31 | 2021-08-17 | 中铁第一勘察设计院集团有限公司 | Sensor data fusion method and device, storage medium and computing equipment |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101888247A (en) * | 2010-07-02 | 2010-11-17 | 北京工业大学 | Self-adoptive correcting device of mismatch error of time-interleaved analog-digital converter |
| CN101917362A (en) * | 2010-06-25 | 2010-12-15 | 杭州万工科技有限公司 | Phase compensation method for multi-channel analog to digital converted signals |
| CN102497210A (en) * | 2011-11-30 | 2012-06-13 | 电子科技大学 | Data synchronous identification device of multiple analog-to-digital converter (ADC) high-speed data acquisition system |
-
2014
- 2014-09-19 CN CN201410484254.5A patent/CN104270154B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101917362A (en) * | 2010-06-25 | 2010-12-15 | 杭州万工科技有限公司 | Phase compensation method for multi-channel analog to digital converted signals |
| CN101888247A (en) * | 2010-07-02 | 2010-11-17 | 北京工业大学 | Self-adoptive correcting device of mismatch error of time-interleaved analog-digital converter |
| CN102497210A (en) * | 2011-11-30 | 2012-06-13 | 电子科技大学 | Data synchronous identification device of multiple analog-to-digital converter (ADC) high-speed data acquisition system |
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| CN104270154A (en) | 2015-01-07 |
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