CN101888247A - Self-adoptive correcting device of mismatch error of time-interleaved analog-digital converter - Google Patents
Self-adoptive correcting device of mismatch error of time-interleaved analog-digital converter Download PDFInfo
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Abstract
The invention discloses a self-adoptive correcting device of mismatch error of time-interleaved analog-digital converter, comprising an M channel TIADC, a signal recombination, a digital reference signal memorizer, a simulated reference signal generator, a self-adaptive reconstruction filter bank, a clock generation circuit and a subtraction device. Signals after passages are reconstructed are used to correct each passage instead of single correction on each passage, thereby solving the problem that when an input signal bandwidth is larger than the Nyquist frequency of each passage ADC, the time error can not be corrected due to aliasing. Each self-adoptive reconstruction filter is divided into a plurality of sub-filters for concurrent working, thereby not improving the requirement of the treatment speed for a self-adoptive correcting filter while realizing the effect of signal recombination and ensuring the practicability of the hardware of the structure of the invention. A digital reference signal is internally installed in the device and is taken as a target to carry out the self-adoptive correction, pre-measuring or calculating a passage mismatch error is not needed, and the source of the error is not needed to be discriminated so that various mismatch errors can be corrected.
Description
Technical field
The present invention relates to a kind of calibrating installation, be specifically related to be applied to a kind of adaptive calibration device of multichannel time-interleaved analog-digital converter (TIADC), can calibrate the mismatch error between a plurality of passages among the TIADC.
Background technology
Adopting a plurality of relative low speed, the time-interleaved sampling of a plurality of channel parallels of high-precision analog to digital converter (ADC) to constitute the TIADC system is the developing direction of present high speed, high-precision ADC.The manufacturing process of ADC etc. are introduced channel mismatching error (time error, gain error and biased error), if mismatch error is not calibrated, will have a strong impact on the performance of TIADC system but in actual applications.The number of applying for a patent is the method that 200510094743.0 self correcting multipath A/D converters have provided calibration-gain sum of errors biased error; The number of applying for a patent provides a kind of clock control circuit that reduces time error for 200510122833.6 four-channel mismatch-free clock control circuits, this method requires sampling hold circuit to move with the sample rate of system, and the sampling hold circuit of design high-speed, high precision is very difficult, has limited the sample rate of TIADC system.U.S. Pat 2008174461-A1 reduces the mismatch error of TIADC at analog domain from the angle of design ADC, does not then have versatility for existing ADC chip.U.S. Pat 2008030387-A1 can only the calibration-gain error; US2008024338-A1 can only calibration-gain sum of errors biased error.
M the parallel alternation of ADC that sampling rate is fs, the formation sampling rate is the TIADC system of Fs (Fs=Mfs), the bandwidth of the manageable analog input signal of TIADC system this moment is Fs/2.But for the manageable maximum bandwidth of the ADC of each passage is fs/2, that is to say the output aliasing not that just can guarantee each ADC less than fs/2 when the input signal bandwidth.Because gain error and biased error are linear, therefore can be extrapolated to then in the whole Fs/2 input bandwidth by in fs/2 input bandwidth, single passage being compensated.But, in the input bandwidth during, can utilize the filtering wave by prolonging time device to carry out phase compensation by after injecting test signal and calculating time error less than fs/2 for time error.When the bandwidth of input signal during greater than fs/2, the output of each passage ADC all is aliasing, be reflected on the output spectrum is that input signal greater than fs/2 is folded back in the fs/2, this moment, output spectrum information can not reflect time difference information really, therefore can not carry out error compensation by introduce the filtering wave by prolonging time device on each passage again.When how importing in the broadband (the input signal bandwidth is Fs/2), the calibration of deadline error is the object of the invention.
Summary of the invention
The present invention seeks to by a kind of adaptive calibration device of multichannel time-interleaved analog-digital converter is provided, not only can calibrate the gain error and the biased error of TIADC system, can also calibrate the frequency response mismatch error of relevant time error with frequency input signal and each passage ADC.
The present invention realizes by the following technical solutions:
The adaptive calibration device of a kind of time-interleaved analog-digital converter (TIADC) mismatch error comprises clock generation circuit, M passage TIADC, signal reorganization, self-adapting reconstruction bank of filters, digital reference signal generator, analog generator, asks poor device.This structure has two kinds of mode of operations, calibration mode and normal mode of operation.When calibration mode, the reference signal that the input of M passage TIADC generates from reference signal generator, after signal reorganization and self-adapting reconstruction filtering are carried out in the output of M passage TIADC, send into the reference signal of asking poor device and built-in reference signal generator to produce and ask poor, the Error Feedback of gained is adjusted the coefficient of filter to the self-adapting reconstruction bank of filters based on the LMS algorithm, the order of magnitude until error satisfies the design objective requirement, and calibration is finished.After calibration was finished, the output of self-adapting reconstruction bank of filters disconnected with the input of asking poor device, and the coefficient of self-adapting reconstruction bank of filters remains unchanged, and the input of importing M passage TIADC this moment is connected to input signal and enters normal mode of operation.
Compared with prior art, the present invention has the following advantages:
Built-in synchronous training signal also carries out adaptive calibration as reference signal, and this adaptive calibration device does not need to measure in advance or calculate the size of channel mismatching error, thereby has avoided the measurement of mismatch error, the complex work of calculating; And do not need to distinguish the source of error, to the equal adjustable of various mismatch errors.With the signal after the reorganization of each passage each passage is calibrated, rather than calibration separately on each passage, when having solved the input signal bandwidth greater than the nyquist frequency of each passage ADC because aliasing and problem that can not the alignment time error.Adopt the TIADC behind this structural alignment not need input signal is carried out over-sampling, promptly the input signal bandwidth is not subjected to any restriction of introducing because of calibration algorithm in system's Nyquist sampling frequency, realizes two-forty broadband analog-to-digital conversion truly.Calibrating installation is simple, thereby has avoided complicated calibration algorithm to be difficult to be converted to the problem of hardware circuit, is easy to hardware and realizes.There is not the realization offset issue of analogue device in the digital realization of calibrated section.The uncontrollability that calibration accuracy is realized by simulation process is converted into the controllability that calibration algorithm is optimized, and can not introduce any restriction to the design of ADC chip, and highly versatile is applicable to most ADC of new generation.
Description of drawings
Fig. 1 is an enforcement structured flowchart of the present invention;
Fig. 2 realizes schematic diagram for signal reorganization equivalence, and the nothing of the 3rd passage ADC# 3 is worth calculating partially;
Fig. 3 realizes schematic diagram for signal reorganization equivalence, and the nothing of the 4th passage ADC# 4 is worth calculating partially;
Fig. 4 realizes schematic diagram for signal reorganization equivalence, and the nothing of second passage ADC# 2 is worth calculating partially;
Fig. 5 is an adaptive calibration device block diagram of the present invention;
Fig. 6 is the implementation structure schematic diagram of first channel adaptive reconfigurable filter # 1.
Among the figure, 1.M passage TIADC, 2. signal reorganization, 3. digital reference signal memory, 4. analog generator, 5. self-adapting reconstruction bank of filters, 6. clock generation circuit is 7. asked poor device, 8. MUX, 51. registers group, 52. subfilter groups.
Embodiment
Describe the specific embodiment of the present invention in detail below in conjunction with accompanying drawing.
As shown in Figure 1, passage number M=4, the sampling rate fs=100MHz of each passage ADC (ADC# 1, ADC# 2, ADC# 3, ADC#4), the Nyquist Bandwidth of each ADC is 50MHz, promptly when the analog input bandwidth of each ADC during less than 50MHz, the output that could guarantee each passage ADC is aliasing not.The parallel alternation of the ADC of 4 passages constitutes the TIADC system of sampling rate Fs=400MHz, and switching rate improves 4 times, and the Nyquist Bandwidth of simultaneity factor also should improve 4 times to 200MHz; But when the simulation input tape of system was wider than 50MHz, the ADC of each passage produced the output aliasing because of not satisfying Nyquist's theorem, and aliasing has brought difficulty for the calibration with the mismatch error of frequency dependence.
If individual processing on each passage can calibration-gain sum of errors biased error, because gain error and biased error are linear.But for the time error that is reacted on the phase place, then can not proofread and correct, this be because: the bandwidth of input signal has surpassed the process range of single ADC, thereby has drawn aliasing at output, and the frequency spectrum behind the aliasing is the information of reaction time error really.Be head it off, adopted signal to recombinate among the present invention and avoided aliasing.
Signal reorganization theory is that the dateout of each passage ADC is lined up a sample value sequence in time, the sample rate of each passage ADC is fs, then after the output reorganization with M ADC, the signal sampling rate after the reorganization should be brought up to Fs (Fs=Mfs) could guarantee not aliasing of signal.Therefore, the signal reorganization is to be equivalent to the sampling rate of each passage has been improved M doubly in theory.If directly the signal after the reorganization is carried out follow-up digital processing (digital filtering), will require the digital filter operating rate also to be increased to Fs like this, when M is more greatly Fs when higher, realize having brought difficulty for the hardware of digital filter.Therefore when particular hardware of the present invention is implemented, the dateout of M passage ADC is not lined up a sample value sequence in time, but adopt when calibrating each passage, all utilize the dateout of other passage, thereby reach effect the dateout reorganization of M passage ADC.
With 4 passage TIADC systems among Fig. 1 is example, describes schematic diagram such as Fig. 2, Fig. 3 and shown in Figure 4 that the signal reorganization realizes.Among Fig. 2,1 in the circle, 2,3,4 sampled points of representing 4 ADC (ADC# 1 to ADC#4) respectively, following axis is represented the uniform sampling point, and top axis is represented the nonuniform sampling point, and the sampled point with ADC# 1 among the figure is decided to be the zero deflection datum mark.(n+2) of ADC# 3 unbiased sampling value constantly can obtain by (n+2) have inclined to one side value y (n+2) and the adjacent inclined to one side value linear combination (digital filtering) that has thereof constantly, shown in arrow line among Fig. 2.The next unbiased sampling value of ADC#3 (n+6 constantly) also can obtain by these computational methods.No inclined to one side sample value computational methods and the ADC# 3 of ADC# 4 is similar among Fig. 3, just be used for calculating the inclined to one side sample value of having of ADC# 4 and compare integral body in time with ADC# 3 and moved one backward, and the linear combination computing formula of ADC# 4 is also different.In like manner, as shown in Figure 4, the no inclined to one side sample value computational methods of ADC# 2 are also similar with ADC# 3, just be used for calculating the inclined to one side sample value of having of ADC# 2 and compare integral body in time with ADC# 3 and moved forward one, and the linear combination computing formula of ADC# 2 is also different.Simultaneously, digital filter adopts parallel organization, each digital filter is split into 4 subfilters, thereby can receive the parallel data of 4 passages.
Utilize the equivalent signal recombination structure to solve because after aliasing can not calibrate time error and frequency response error relevant with frequency, obtaining of the tap coefficient of each passage digital calibration filter was another key issue of the present invention.According to traditional correction mode, before carrying out error compensation, at first want the size of estimation error, and error estimation is the work of a complexity.In addition, actual TIADC system will reach higher precision, timing not only will be considered static mismatch error (biased error, gain error, time error), also will the frequency response mismatch error of each the passage ADC relevant with frequency input signal be compensated, and the estimation of this frequency response mismatch error relevant with frequency input signal is complicated especially.The present invention proposes a kind of adaptive calibration device based on LMS (Least Mean Square) algorithm, avoids complicated error measure and evaluation work.
The core concept of adaptive calibration device of the present invention be to reference signal of fixed system as standard, adopt the adaptive targets optimization, the output of system to be calibrated is approached, until reaching required precision to reference signal.Do not need to know in advance the size and the source of mismatch error when therefore calibrating, avoided complicated error measure or estimation work, solve the problem that complicated estimation error algorithm is difficult to hardware conversion simultaneously.The present invention propose based on the adaptive calibration schematic diagram of LMS algorithm as shown in Figure 5, the analog input signal of TIADC system when wherein x (t) is operate as normal, d (t) is the reference signal under the calibration mode, x (n) and y (n) are respectively the input and output of adaptive calibration filter, d (n) is a desired output, and e (n) is an error signal.Filter coefficient iterative formula based on the LMS algorithm is:
W(n+1)＝W(n)+μ·e(n)·X(n) (1)
e(n)＝d(n)-y(n) (2)
Wherein W (n) is a filter coefficient, vector representation; X (n) is the vector that several x (n) form.
The key of this calibration algorithm is obtaining of reference signal and obtaining of adaptive calibration filter coefficient.In order to satisfy the calibration effect in the whole Nyquist frequency band range of TIADC system, reference signal should be to contain the band limit random signal (should comprise all frequency components in 0～Fs/2 in theory) of enriching spectrum component.Reference signal comprise be used for the external reference signal of analog input to the TIADC system is provided and when being used for carrying out adaptive calibration as the built-in reference signal of optimization aim.Use for reference the base band shaping theory in the digital communication theory, produce band limit random signal as digital reference signal (can produce by SPW software, and storage hereof) with the BPSK baseband signal generator.The digital reference signal that to store earlier before calibration hereof is written in the hardware memory by DLL (dynamic link library) (I2C interface or SPI interface), as built-in reference signal.Adopt signal generator or high-precision, the built-in reference signal of the synchronous loading of DAC at a high speed simultaneously, its simulation output is sent into the TIADC system as external reference signal.If the TIADC system is desirable, then the output of TIADC system and built-in reference signal should be in full accord.
Because there is mismatch error in actual TIADC system, there is certain difference in the output of external analog reference signal after TIADC system analog-to-digital conversion with built-in reference signal as optimization aim.The design synchronous circuit, synchronous circuit is adjusted the phase place of local built-in reference signal according to the synchronizing signal in the TIADC system output signal, makes TIADC system output signal and built-in reference signal time unifying; And the two is asked poor, difference feeds back to the self-adapting reconstruction filter and carries out adaptive calibration, constantly self adaptation is adjusted the coefficient of filter, the output of TIADC system is approached to built-in reference signal, reach required precision until the two output error and finish calibration, thereby obtain the calibration filters coefficient, and with this coefficient storage.
After calibration is finished, with the input and the external reference signal disconnection of TIADC system, the input signal when being connected to operate as normal; Output also no longer feeds back to subtractor circuit and asks poor, but directly output, this moment, system entered normal mode of operation.By external control signal the TIADC system is switched between calibration mode and normal mode of operation mutually, so that the calibration once more under the different service condition.
When actual hardware was realized, along with the raising that the TIADC system accuracy requires, the reference signal that therefore also just needs magnanimity just can make system's output converge to desired precision as synchronous training signal.The reference signal of storing these magnanimity needs the very large memory of specification, and hardware consumption is very big.In order to address this problem, consider that reference signal is made of random noise sequences, except bandwidth, there is no specific (special) requirements, this paper adopts very little memory stores small number of synchronous signal of specification and pseudorandom band-limited signal, under the control of read-write control circuit, the circulation reading of data constitutes synchronous training signal from memory, and hardware consumption sharply reduces
A kind of scheme of external reference signal is to produce by signal generator, built-in reference signal is loaded into signal generator synchronously, the clock of signal generator adopts external clock, promptly adopt the clock of TIADC system then can satisfy synchronous requirement, this moment, signal generator can be used as the DAC use of high-precision high-speed.Another kind of scheme is to connect on the pcb board of calibration usefulness that a slice is high-precision, the high-speed DAC chip, and built-in reference signal is read through memory and sent into DAC and serve as external reference source through digital-to-analogue conversion.Another scheme is directly to add a DAC in the TIADC system design, because under identical technology and the technology, design realizes that the DAC of identical speed and precision is easy more than ADC.Can select concrete implementation according to the requirement of different costs, different application.
For 4 passage TIADC systems among Fig. 1, suppose that each passage needs the adaptive calibration filter on N=64 rank, then the filter on each 64 rank can equivalence be the subfilter concurrent working on 4 16 rank, 4 subfilters receive the dateout (sampling rate fs=100MHz) of 4 road ADC respectively, can guarantee that therefore the operating rate of each subfilter still is 100MHz.Among Fig. 1 the structure of the sef-adapting filter # 1 of first passage as shown in Figure 6, registers group 51 is used for data sync with each passage to the clock CLK_SP1 of the first via, 4 parallel subfilter (eq_fir_16 in the subfilter group 52
Th#1, eq_fir_16
Th#2, eq_fir_16
Th#3, eq_fir_16
Th#4) receive the audio data AD C_OUT_1 to ADC_OUT_4 of four passages respectively, behind adaptive-filtering, the output addition of 4 subfilters obtains the output yn_1 after the first via calibration.ADC_STD_1 is the desired output of the first via, from built-in reference signal, asks difference back (difference is err_1) to be sent in each subfilter with yn_1, carries out adaptive calibration, until reaching required precision.The tap coefficient of 4 subfilters is stitched together, as the tap coefficient of the adaptive calibration filter on 64 rank of first passage.Structure and Fig. 6 of the sef-adapting filter of other 3 passages are similar, just the expectation input value difference of each passage.When the passage number M increased, the number that only needs to increase subfilter got final product, and when reaching the effect of signal reorganization, can not improve requirement to adaptive calibration filter process speed, had guaranteed the hardware realizability.MUX is merged into one tunnel output with the output of M reconstruct filter group, and sampling rate improves M doubly simultaneously.
Utilizing sampling rate is 12 ADC IP kernel for 100MHz, resolution, the chip of the TIADC system of 400MHz has been produced in flow on TSMC 0.18 μ m1.8V/3.3V 1P5M CMOS technology, and utilize the calibrating installation in the utility model to calibrate, can well suppress harmonic wave by the mismatch error introducing, harmonic attenuation below noise floor, has been proved the validity of this calibrating installation.
Claims (5)
1. the adaptive calibration device of a time-interleaved analog-digital converter mismatch error comprises M passage TIADC (1), signal reorganization (2), digital reference signal memory (3), analog generator (4), self-adapting reconstruction bank of filters (5), clock generation circuit (6), asks poor device (7); It is characterized in that:
Described signal reorganization (2) is lined up a sample value sequence in time with the dateout of M ADC, signal sampling speed after the reorganization is enhanced Mfs, the bandwidth of analog input signal is extended to the dateout that Mfs/2 utilizes other passage, with the dateout equivalence reorganization of M passage ADC, each reconfigurable filter is still worked under lower speed fs when guaranteeing calibration;
Described digital reference signal memory (3) is used for storing the digital reference signal of calibration usefulness, digital reference signal guarantees that for the bandwidth that is produced by the BPSK baseband signal generator is the band limit pseudo-random signal of Mfs/2 bandwidth is that the interior analog input signal of Mfs/2 is covered as far as possible comprehensively; Employing is built-in small-scale memory in the TIADC System on Chip/SoC, memory stores small number of synchronous signal and band limit pseudo-random signal, under the control of read-write control circuit, circulation reading of data formation synchronous reference signal serves as the synchronous training signal of self-adapting reconstruction bank of filters (3) from memory;
Described analog generator (4) is used for producing the analog source of calibration usefulness, and the analog source of generation is corresponding one by one with digital reference signal in the digital reference signal memory (3), and has synchronized relation; By sampling rate is that the digital to analog converter DAC of Mfs constitutes, DAC the embedded digital reference signal through the analog of digital-to-analogue conversion as the TIADC system;
Described self-adapting reconstruction bank of filters (5) is used for calibrating the mismatch error of M passage TIADC (1), analog is through after having M passage TIADC (1) analog-to-digital conversion of mismatch error, there is error with the digital signal in the digital reference signal memory (3), through asking Error Feedback that poor device (7) tries to achieve to self-adapting reconstruction bank of filters (5), coefficient by each sef-adapting filter in the LMS algorithm optimization self-adapting reconstruction bank of filters (5), make that the output of self-adapting reconstruction bank of filters (5) is close to built-in reference signal gradually, reach the requirement of system accuracy until the two error;
The described poor device (7) of asking is realized that by a subtracter output of digital reference signal generator (4) and the output of self-adapting reconstruction bank of filters (5) are asked poor, and the Error Feedback of obtaining is to reconfigurable filter group (5);
Adaptive calibration device has two kinds of mode of operations, calibration mode of operation and normal mode of operation; After calibration mode of operation is finished, the output of self-adapting reconstruction bank of filters (5) disconnects with the input of asking poor device (7), the coefficient of self-adapting reconstruction bank of filters (5) remains unchanged, and the input of importing M passage TIADC (1) this moment is connected to input signal and enters normal mode of operation.
2. the adaptive calibration device of time-interleaved analog-digital converter mismatch error according to claim 1, it is characterized in that: described calibration mode of operation, the reference signal that the input of M passage TIADC (1) generates from reference signal generator, after signal reorganization (2) and self-adapting reconstruction filtering (5) are carried out in the output of M passage TIADC (1), send into and ask poor device (7) and the reference signal in the digital reference signal memory (3) to ask poor, the Error Feedback of gained to self-adapting reconstruction bank of filters (5) is carried out adaptive calibration, meets the demands until the order of magnitude of error.
3. the adaptive calibration device of time-interleaved analog-digital converter mismatch error according to claim 1, it is characterized in that: described self-adapting reconstruction bank of filters (5) comprises M self-adapting reconstruction filter, each self-adapting reconstruction filter adopts parallel organization, the self-adapting reconstruction filter on each L rank is split into the subfilter on M L/M rank, receive the parallel data of M passage, each reconfigurable filter is still with the speed work of fs when guaranteeing to calibrate; The tap coefficient of the subfilter on M L/M rank is spliced to form the tap coefficient of each channel adaptive reconfigurable filter; The output addition of the subfilter on M L/M rank constitutes the output of each channel adaptive reconfigurable filter.
4. the adaptive calibration device of time-interleaved analog-digital converter mismatch error according to claim 1, it is characterized in that: described clock generation circuit (6) produces M speed and is respectively 0 °, 2 π/M °, 2 * 2 π/M °, 3 * 2 π/M ° for the fs phase place ... (M-1) * and the clock of 2 π/M °, send into first passage ADC, second channel ADC, third channel ADC respectively ... the alternation of M passage ADC multi-channel parallel.
5. the adaptive calibration device of time-interleaved analog-digital converter mismatch error according to claim 1, it is characterized in that: it is the clock of Mfs that described clock generation circuit (6) produces speed, send into analog generator (4) be used for digital reference signal synchronously, also can produce M speed and be respectively 0 ° for the fs phase place, 2 π/M °, 2 * 2 π/M °, 3 * 2 π/M ° ... (M-1) * and the clock of 2 π/M °, send into M passage TIADC (1) first passage respectively, second channel, third channel ... each self-adapting reconstruction filter of the ADC of M passage and self-adapting reconstruction bank of filters (5).
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1729420A1 (en) * | 2005-01-11 | 2006-12-06 | Anritsu Corporation | Analog-to-digital converter device of improved time interleaving type, and high-speed signal processing system using the device |
| CN1976235A (en) * | 2005-11-28 | 2007-06-06 | 日立通讯技术株式会社 | Time-interleaved AD converter |
| US20080024338A1 (en) * | 2006-07-27 | 2008-01-31 | Realtek Semiconductor Corp. | Calibration apparatus for mismatches of time-interleaved analog-to-digital converter |
| CN101136633A (en) * | 2006-08-28 | 2008-03-05 | 瑞昱半导体股份有限公司 | Correcting device for time interleaving type analog-digital converter |
-
2010
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1729420A1 (en) * | 2005-01-11 | 2006-12-06 | Anritsu Corporation | Analog-to-digital converter device of improved time interleaving type, and high-speed signal processing system using the device |
| CN1976235A (en) * | 2005-11-28 | 2007-06-06 | 日立通讯技术株式会社 | Time-interleaved AD converter |
| US20080024338A1 (en) * | 2006-07-27 | 2008-01-31 | Realtek Semiconductor Corp. | Calibration apparatus for mismatches of time-interleaved analog-to-digital converter |
| CN101136633A (en) * | 2006-08-28 | 2008-03-05 | 瑞昱半导体股份有限公司 | Correcting device for time interleaving type analog-digital converter |
Non-Patent Citations (4)
| Title |
|---|
| NAOKI KUROSAWA: "Explicit Analysis of Channel Mismatch Effects in Time-Interleaved ADC Systems", 《IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS》, vol. 48, no. 3, 31 March 2001 (2001-03-31), XP011012283 * |
| SHAHZAD SALEEM: "LMS-based identification and compensation of timing mismatches in a two-channel time-interleaved analog-to-digital converter", 《PROCEEDING OF NORCHIP,2007》, 4 April 2008 (2008-04-04) * |
| 潘卉青: "高速TIADC并行采样系统综合校正技术研究", 《电子科技大学博士学文论文》, 1 March 2010 (2010-03-01) * |
| 邓琳: "并行采集系统通道失配误差测量及校正", 《电子科技大学学报》, vol. 35, no. 3, 30 June 2006 (2006-06-30) * |
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