CN105959005B - The digital background calibration device of pipeline ADC - Google Patents
The digital background calibration device of pipeline ADC Download PDFInfo
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- CN105959005B CN105959005B CN201610248384.8A CN201610248384A CN105959005B CN 105959005 B CN105959005 B CN 105959005B CN 201610248384 A CN201610248384 A CN 201610248384A CN 105959005 B CN105959005 B CN 105959005B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
- H03M1/1009—Calibration
- H03M1/1014—Calibration at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error
- H03M1/1023—Offset correction
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
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Abstract
The present invention provides a kind of digital background calibration devices of pipeline ADC.The device includes the subflow waterline and calibration circuit composition of multi-stage cascade, every grade of subflow waterline includes sample/hold circuit, surplus amplifier, Sub-ADC and Sub-DAC, analog signal passes sequentially through every level-one subflow waterline of pipeline ADC, while analog input is calibrated grade subflow waterline, the pseudo-random sequence that calibration circuit generates, which is input into, to be calibrated in grade Sub-DAC of subflow waterline, calibration circuit utilizes the digital quantity after the calibration of pseudo-random sequence and the sub- pipeline conversion of all rear classes for being calibrated grade subflow waterline, the digital quantity for being calibrated the sub- pipeline conversion of grade is calibrated, obtain being calibrated the digital quantity after the calibration of the sub- pipeline conversion of grade.The present invention overcomes modification of the existing calibration algorithm to analog circuit, the error as caused by capacitance mismatch and amplifier finite gain can be calibrated simultaneously, and it does not interrupt ADC and normally works, original Analog Circuit Design is not changed, especially preferably improve the error introduced due to calibration algorithm itself, it is small to calibrate cost, calibration accuracy is high.
Description
Technical field
The present invention relates to ADC (Analog-to-Digital Converter, analog-digital converter) collimation technique fields, especially
It is related to a kind of digital background calibration device of pipeline ADC.
Background technique
ADC is the circuit module for converting analog signals into digital signal, it is widely used in various fields, such as sound
Frequency video acquisition, high-definition image processing, communication system etc..And different fields also proposed different requirements to the performance of ADC,
Therefore the ADC of different structure is developed.Wherein, pipeline ADC has taken into account the important spy in this two big ADC application of speed and precision
Property, therefore it is using relatively broad.
Nowadays, with the progress of manufacturing process, transistor feature size is further decreased, high speed, high-precision adc design
The difficulties such as device is scaled, supply voltage reduces are faced, this will lead to non-ideal effects increase, Bandwidth-Constrained, stability
The problems such as reduction, dynamic range are deteriorated.Traditional design method compared to high-precision analog circuit is faced with stern challenge, number
Word circuit constantly benefits in the lasting diminution of transistor size, and performance significantly improves, and manufacturing cost constantly reduces.Due to number
Integrated circuit has the characteristics that high reliablity, low in energy consumption and flexible design, and can preferably utilize CMOS (Complementary
Metal Oxide Semiconductor, complementary metal oxide semiconductor) technique progress bring advantage, digital circuit and
Digital calibration techniques can be used to be calibrated and compensated the error of analog circuit.This kind of technology is difficult by the precision in Analog Circuit Design
The problem of to improve, is transferred in digital circuit and solves, and replaces original complicated height with the simply low precision circuits of structure
Precision circuits are calibrated and compensated simulation error in numeric field, guarantee analog circuit using digital circuit computer aided simulation circuit design
With higher speed, more low-power consumption and more Larger Dynamic range etc..Digital calibration techniques are applied to the design of pipeline ADC, reduce
The complexity of its analog portion design, improves the performance indicator of ADC, is more and more widely used.
Pipeline ADC is cascaded using the sub- ADC (sub-ADC) of a series of similar high speed of structures, low precision.It is right
In every level-one, after inputting quilt ADC sampling with quantization, output surplus is amplified the input for being suitable for next stage.It is so multistage
Connection, works at the same time, to realize the conversion between the analog signal of high-speed, high precision and digital signal.
It is made of in pipeline ADC existing the cascade of 7 grades of subflow waterlines, wherein first 6 grades are 1.5bit structure, the 7th grade
For 2bit structure, 8bit digital quantity is exported altogether after dislocation is added.Every primary structure of pipeline ADC by sample/hold circuit,
Sub-ADC, Sub-DAC, subtracter and surplus amplifier are constituted.After analog signal is input to the first level structure, signal is through adopting
Digital output of the digital code D1 as the same level is quantified as by Sub-ADC after sample holding, subsequent digital code D1 is restored by Sub-ADC
Subtracted each other for analog quantity and with the analog signal of input, residual error is amplified the mould after circuit amplifies twice as next level structure
Quasi- input.Every level structure is all made of same mode and works, and final digital quantities at different levels are input into digital calibration circuit and are prolonged
When alignment with misplace be added, obtain final 8 bit digital quantity.
For every primary structure, ideal input and output formula are as follows:
Vres=2Vin-bVref(formula 1)
Wherein, b represents the digital output of the level structure assembly line.But when the limited increasing in view of capacitance mismatch and amplifier
After the main source of error of this beneficial two pipeline ADCs, actual input and output formula becomes:
Vres=(1+ δ) [(2+ α) Vin-(1+α)bVref] (formula 2)
Wherein, α and δ respectively represent the coefficient that capacitor be excuse me, but I must be leaving now with non-ideal factor caused by amplifier finite gain.Due to drawing
This two non-ideal factors are entered, the entire effect to pipeline ADC is as shown in Fig. 2, cause the output of pipeline ADC to generate
Linear and nonlinear distortion, influences its performance indicator.
Based on this reason, digital background calibration technology is introduced into pipeline ADC, can calibrate simultaneously by capacitance mismatch with
Error caused by amplifier finite gain, and do not interrupt ADC and normally work, while improving the performance indicator of ADC.
It now for the collimation technique of pipeline ADC, can generally change simulation circuit structure, become original circuit design
Complexity, while not accounting for influence of the calibration algorithm to pipeline ADC itself yet.
Summary of the invention
The embodiment provides a kind of digital background calibration devices of pipeline ADC, to realize to pipeline ADC
Effectively calibrated.
The present invention provides following schemes:
A kind of digital background calibration device of pipeline ADC, comprising:
The pipeline ADC is made of the subflow waterline and calibration circuit of multi-stage cascade, every grade of subflow waterline include sampling/
Holding circuit, surplus amplifier, Sub-ADC and Sub-DAC, the calibration circuit and every level-one subflow waterline circuit connection；
Analog signal passes sequentially through every level-one subflow waterline of pipeline ADC, is calibrated a grade subflow water in analog input
While line, the pseudo-random sequence that the calibration circuit generates be input into it is described be calibrated in grade Sub-DAC of subflow waterline,
Grade analog quantity of subflow waterline output that is calibrated enters rear stage after surplus amplifier jointly with pseudo-random sequence
Subflow waterline；
The calibration circuit is turned using pseudo-random sequence and all rear class subflow waterlines for being calibrated grade subflow waterline
Digital quantity after the calibration changed calibrates the digital quantity for being calibrated the sub- pipeline conversion of grade, obtains described be calibrated
Digital quantity after the calibration of the sub- pipeline conversion of grade.
Further, the calibration circuit includes PN sequencer, selector, control signaling module, error compensation mould
Block, digital calibration block and digital quantity summation module, the digital calibration block include the son being arranged in each subflow waterline
Calibration module；
The PN sequencer, for generating pseudo-random sequence；
The selector, for and the PN sequencer, control signaling module connect and subflow waterline at different levels in
Sub-DAC connection；
The control signaling module, for control the selector certain grade of subflow waterline prover time to certain described grade
Subflow waterline injects pseudo-random sequence, simultaneously closes off the channel to other grade of subflow waterline injection pseudo-random sequence；It controls simultaneously
Error compensation module provides and is calibrated grade corresponding error compensation value of subflow waterline；
The error compensation module, according to control signal control, output is calibrated grade corresponding error compensation of subflow waterline
Value, the error compensation value are pseudo-random sequence multiplied by related coefficient；
The sub- calibration module being calibrated in grade subflow waterline is used to connect with the Sub-ADC being calibrated in grade subflow waterline,
It is right using the digital quantity after the calibration of pseudo-random sequence and the sub- pipeline conversion of all rear classes for being calibrated grade subflow waterline
The digital quantity of Sub-ADC conversion is calibrated, and obtains described being calibrated the digital quantity after the calibration of the sub- pipeline conversion of grade；
The digital quantity summation module carries out dislocation phase for the digital quantity after the calibration to sub- pipeline conversions at different levels
Add, obtains the digital quantity of entire pipeline ADC output.
Further, it is mutually staggered in time by the pseudo-random sequence that selector is exported to subflow waterlines at different levels.
Further, the sub- calibration module being calibrated in grade subflow waterline described is calibrated a grade subflow for receiving
The feedback signal of all rear class subflow waterlines of waterline, after the feedback signal includes the calibration of the sub- pipeline conversion of all rear classes
Digital quantity, the feedback signal is calibrated the pseudo-random sequence that grade subflow waterline receives and is multiplied with described, is calculated
Value, then the calculated value repeatedly obtained is subjected to cumulative summation and is averaged, obtain it is described be calibrated a grade margin of error for subflow waterline,
The margin of error is multiplied with the Sub-ADC digital quantity converted, obtains the calibration for being calibrated the sub- pipeline conversion of grade
Digital quantity afterwards.
Further, the sub- calibration module being calibrated in grade subflow waterline is also used to from calibration grade subflow waterline
The digital quantity of all sub- pipeline conversions of rear class subtracts and is calibrated grade error compensation value of subflow waterline and is calibrated a grade subflow water
The product of the margin of error of line, thus in the digital quantity of the sub- pipeline conversion of all rear classes of calibration grade subflow waterline to pseudorandom
The quantization of sequence subtracts, and restores original digital quantity, and the digital quantity of reduction is added for misplacing.
Further, the digital quantity summation module, for adding from afterbody subflow waterline when misplacing addition
It rises, after being added to the digital quantity for being calibrated grade subflow waterline output, with the margin of error of this grade to obtained long number amount
Linear calibration is carried out again, and the margin of error is calibrated in grade subflow waterline for described in excuse me, but I must be leaving now and amplifier finite gain institute by capacitor
Caused error.
Further, the sample/hold circuit being calibrated in grade subflow waterline, for receiving the simulation of prime input
Signal Vin, to the analog signal VinAfter being sampled, it is transferred to the Sub-ADC being calibrated in grade subflow waterline and remaining
Measure amplifier；
The Sub-ADC being calibrated in grade subflow waterline, the simulation for transmitting the sample/hold circuit
Signal VinDigital quantity is converted to, the digital quantity is transferred to the sub- calibration module and Sub- being calibrated in grade subflow waterline
DAC；
The Sub-DAC being calibrated in grade subflow waterline, for receiving digital quantity and the calibration of the Sub-ADC output
The pseudo-random sequence PN of circuit output exports analog signal Vres,
Vres=(1+ δ) [(2+ α) Vin-(1+α)(bVref-PN·Vcal)]
=(1+ δ) [(2+ α) Vin-(1+α)bVref]+PN·Vcal(1+α)(1+δ)
Wherein, VcalAnd VrefFor constant, α and δ respectively represent capacitor excuse me, but I must be leaving now with caused by amplifier finite gain it is non-ideal because
The coefficient of element；
The surplus amplifier being calibrated in grade subflow waterline, for receiving the analog signal V of Sub-DAC outputresWith
The analog signal V of sample/hold circuit outputin, to analog signal VinSubtract analog signal VresValue amplify after, transmission
Give rear stage subflow waterline.
Further, the sub- calibration module being calibrated in grade subflow waterline is calibrated a grade subflow water for calculating
The margin of error of line
Wherein E () indicates that the multiple data calculated in bracket are carried out with summation is averaged, VresIt is defeated for the surplus that is calibrated grade
Out, PN is pseudo-random sequence, VrefWith VcalFor constant, according to pseudo-random sequence characteristic,This
Summation tends to 0 after being averaged, and PN2=1, PN2(1+δ)(1+α)VrefThis summation is (1+ δ) (1+ α) after being averaged
Vref, therefore obtain being calibrated grade corresponding margin of error of subflow waterline.
As can be seen from the technical scheme provided by the above-mentioned embodiment of the present invention, the embodiment of the invention provides a kind of applications
In the ADC digital background calibration algorithm of assembly line, modification of the existing calibration algorithm to analog circuit is overcome, can calibrate simultaneously by electricity
Hold error caused by mismatch and amplifier finite gain, and do not interrupt ADC and normally work, does not change original Analog Circuit Design,
It is small to calibrate cost, calibration accuracy is high.
Detailed description of the invention
In order to illustrate the technical solution of the embodiments of the present invention more clearly, required use in being described below to embodiment
Attached drawing be briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for this
For the those of ordinary skill of field, without any creative labor, it can also be obtained according to these attached drawings other
Attached drawing.
Fig. 1 is a kind of structural block diagram of the digital background calibration device for pipeline ADC that the embodiment of the present invention one provides；
Fig. 2 is the structural block diagram of a kind of calibration circuit and subflow waterline that the embodiment of the present invention one provides；
After Fig. 3 is a kind of number of pipeline ADC being made of the cascade of 7 grades of subflow waterlines provided by Embodiment 2 of the present invention
The structure chart of platform calibrating installation；
Fig. 4 is the pipeline ADC transfer curve schematic diagram before a kind of calibration provided by Embodiment 2 of the present invention；Show；
Fig. 5 is the pipeline ADC transfer curve schematic diagram after a kind of calibration provided by Embodiment 2 of the present invention；Show；
Fig. 6 is preceding 4 grades of schematic diagrames calibrated of a kind of pair of pipeline ADC provided by Embodiment 2 of the present invention.
Specific embodiment
Embodiments of the present invention are described below in detail, the example of the embodiment is shown in the accompanying drawings, wherein from beginning
Same or similar element or element with the same or similar functions are indicated to same or similar label eventually.Below by ginseng
The embodiment for examining attached drawing description is exemplary, and for explaining only the invention, and is not construed as limiting the claims.
Those skilled in the art of the present technique are appreciated that unless expressly stated, singular " one " used herein, " one
It is a ", " described " and "the" may also comprise plural form.It is to be further understood that being arranged used in specification of the invention
Diction " comprising " refer to that there are the feature, integer, step, operation, element and/or component, but it is not excluded that in the presence of or addition
Other one or more features, integer, step, operation, element, component and/or their group.It should be understood that when we claim member
Part is " connected " or when " coupled " to another element, it can be directly connected or coupled to other elements, or there may also be
Intermediary element.In addition, " connection " used herein or " coupling " may include being wirelessly connected or coupling.Wording used herein
"and/or" includes one or more associated any cells for listing item and all combinations.
Those skilled in the art of the present technique are appreciated that unless otherwise defined, all terms used herein (including technology art
Language and scientific term) there is meaning identical with the general understanding of those of ordinary skill in fields of the present invention.Should also
Understand, those terms such as defined in the general dictionary, which should be understood that, to be had and the meaning in the context of the prior art
The consistent meaning of justice, and unless defined as here, it will not be explained in an idealized or overly formal meaning.
In order to facilitate understanding of embodiments of the present invention, it is done by taking several specific embodiments as an example below in conjunction with attached drawing further
Explanation, and each embodiment does not constitute the restriction to the embodiment of the present invention.
Embodiment one
The embodiment of the invention provides a kind of digital background calibration devices of pipeline ADC, and the structural block diagram of the device is such as
Shown in Fig. 1, it is made of the subflow waterline and calibration circuit of multi-stage cascade, every grade of subflow waterline includes sample/hold circuit, surplus
Amplifier, Sub-ADC and Sub-DAC, the calibration circuit and every level-one subflow waterline circuit connection.
Analog signal passes sequentially through every level-one subflow waterline of pipeline ADC, is calibrated a grade subflow water in analog input
While line, it is described calibration circuit generate PN sequence (Pseudo-noise Sequence, pseudo-random sequence) be input by
In the Sub-DAC for calibrating grade subflow waterline, grade analog quantity of subflow waterline output and pseudo-random sequence are calibrated jointly through excess enthalpy
Rear stage subflow waterline is entered after amount amplifier；
The calibration circuit is turned using pseudo-random sequence and all rear class subflow waterlines for being calibrated grade subflow waterline
Digital quantity after the calibration changed calibrates the digital quantity for being calibrated the sub- pipeline conversion of grade, obtains described be calibrated
Digital quantity after the calibration of the sub- pipeline conversion of grade.
The structural block diagram schematic diagram of a kind of calibration circuit and subflow waterline provided in an embodiment of the present invention is as shown in Fig. 2, institute
Stating calibration circuit includes PN sequencer, selector, control signaling module, error compensation module, digital calibration block and number
Word amount summation module, the digital calibration block include the sub- calibration module being arranged in each subflow waterline；
The PN sequencer, for generating pseudo-random sequence；
The selector, for and the PN sequencer, control signaling module connect and subflow waterline at different levels in
Sub-DAC connection is mutually staggered in time by the pseudo-random sequence that selector is exported to subflow waterlines at different levels；
The control signaling module, for control the selector certain grade of subflow waterline prover time to certain described grade
Subflow waterline injects pseudo-random sequence, simultaneously closes off the channel to other grade of subflow waterline injection pseudo-random sequence；It controls simultaneously
Error compensation module provides and is calibrated grade corresponding error compensation value of subflow waterline；
The error compensation module, according to control signal control, output is calibrated grade corresponding error compensation of subflow waterline
Value, the error compensation value are pseudo-random sequence multiplied by related coefficient；According to the error compensation value of setting, for being calibrated a grade subflow
Error caused by waterline compensation calibration algorithm itself；
The digital quantity summation module carries out dislocation phase for the digital quantity after the calibration to sub- pipeline conversions at different levels
Add, obtains the digital quantity of entire pipeline ADC output.Misplace be added when, from adding afterbody subflow waterline, when being added to
After being calibrated grade digital quantity of subflow waterline output, obtained long number amount is carried out again with the margin of error of this grade linear
Calibration, the margin of error are that described be calibrated in grade subflow waterline be excuse me, but I must be leaving now and error caused by amplifier finite gain as capacitor.
The sample/hold circuit being calibrated in grade subflow waterline, for receiving the analog signal V of prime inputin, right
The analog signal VinAfter being sampled, it is transferred to the Sub-ADC and surplus amplifier being calibrated in grade subflow waterline；
The Sub-ADC being calibrated in grade subflow waterline, the analog signal for transmitting the sample/hold circuit
VinDigital quantity is converted to, the digital quantity is transferred to the sub- calibration module and Sub-DAC being calibrated in grade subflow waterline；
The Sub-DAC being calibrated in grade subflow waterline, for receiving digital quantity and the calibration of the Sub-ADC output
The pseudo-random sequence PN of circuit output exports analog signal Vres.Due to only considering to excuse me, but I must be leaving now and the limited increasing of amplifier in circuit by capacitor
Error caused by benefit, the input and output formula for being calibrated level production line are become after pseudo-random sequence is added from formula (2):
Wherein, VcalAnd VrefFor constant, α and δ respectively represent capacitor excuse me, but I must be leaving now with caused by amplifier finite gain it is non-ideal because
The coefficient of element.By formula (3) as can be seen that after pseudo-random sequence is added, output is equivalent to original surplus by this grade and believes
Number it is superimposed with one relevant to pseudo-random sequence.Wherein, PNVcal(1+ α) (1+ δ) this carry error coefficient (1+
α)(1+δ).Later, it exports after after the quantization of level production line, multiplied by the pseudorandom series signal itself injected.According to
Its characteristic carries out cumulative summation to result and is averaged, the error term of this obtained grade.
The surplus amplifier being calibrated in grade subflow waterline, for receiving the analog signal V of Sub-DAC outputresWith
The analog signal V of sample/hold circuit outputin, to analog signal VinSubtract analog signal VresValue amplify after, transmission
Give rear stage subflow waterline.
The sub- calibration module being calibrated in grade subflow waterline is used to connect with the Sub-ADC being calibrated in grade subflow waterline,
It is right using the digital quantity after the calibration of pseudo-random sequence and the sub- pipeline conversion of all rear classes for being calibrated grade subflow waterline
The digital quantity of Sub-ADC conversion is calibrated, and obtains described being calibrated the digital quantity after the calibration of the sub- pipeline conversion of grade.
Concrete processing procedure includes: to receive the feedback signal for all rear class subflow waterlines for being calibrated grade subflow waterline, the feedback letter
Number include the sub- pipeline conversion of all rear classes calibration after digital quantity, by the feedback signal and described be calibrated a grade subflow water
The pseudo-random sequence that line receives is multiplied, and obtains calculated value, then the calculated value repeatedly obtained is carried out cumulative summation and is averaged,
It is calibrated a grade margin of error for subflow waterline described in obtaining, the margin of error is multiplied with the Sub-ADC digital quantity converted, is obtained
Digital quantity to after the calibration for being calibrated the sub- pipeline conversion of grade.
The sub- calibration module being calibrated in grade subflow waterline is also used to all rear classes from calibration grade subflow waterline
The digital quantity of pipeline conversion subtracts and is calibrated grade error compensation value of subflow waterline and is calibrated a grade margin of error for subflow waterline
Product, thus the quantization in the digital quantity of the sub- pipeline conversion of all rear classes of calibration grade subflow waterline to pseudo-random sequence
It subtracts, restores original digital quantity, the digital quantity of reduction is added for misplacing.
It is above-mentioned to be calibrated a grade margin of error for subflow waterlineCalculating process include:
In actual circuit, if assuming, being calibrated grade rear class is ideally VresAs it is calibrated the institute of grade subflow waterline
The respective value of digital quantity after having the calibration of rear class subflow waterline.
Wherein E () indicates that the multiple data calculated in bracket are carried out with summation is averaged, VresIt is defeated for the surplus that is calibrated grade
Out, PN is pseudo-random sequence, VrefWith VcalFor constant, according to pseudo-random sequence characteristic,This
Summation tends to 0 after being averaged, and PN2=1, PN2(1+δ)(1+α)VrefThis summation is (1+ δ) (1+ α) after being averaged
Vref, therefore available it is calibrated grade corresponding margin of error of subflow waterline.
Embodiment two
A kind of digital background calibration device for pipeline ADC being made of 7 grades of subflow waterline cascades that the embodiment provides
Structure chart as shown in figure 3, first 6 grades every grade of generation 1.5bit digit order numbers, the 7th grade of generation 2bit digit order number.Analog signal is successively
By every primary structure of pipeline ADC, and the digital quantity of 1.5bit (afterbody 2bit) is generated, finally by dislocation phase
Add to arrive last 8bit digital quantity.
Calibration only calibrates first 4 grades, and the object of calibration is that excuse me, but I must be leaving now and mistake caused by amplifier finite gain as capacitor
Difference.When needing to calibrate certain level structure, while the analog input level structure, the pseudorandom sequence that is generated by PN sequencer
Column can be input into the Sub-DAC for being calibrated grade.The analog quantity that this grade is entered is put by surplus jointly with pseudo-random sequence
Rear stage is entered after big device, and is sequentially completed the conversion of remaining digit amount.Using the characteristic of pseudo-random sequence, grade will be calibrated
The digital quantity of rear class conversion, that is, be added the digital quantity of the conversion of pseudo-random sequence, be multiplied with itself, then carried out to result tired
Add summation to be averaged, obtains the margin of error that excuse me, but I must be leaving now together with the finite gain of amplifier by capacitor that pseudo-random sequence carries out, benefit
The digital quantity for being calibrated grade conversion is calibrated with this margin of error, the result after calibration is the real output valve of the grade.Quilt
Grade is calibrated by the fourth stage, the rear class data calibration previous stage of calibrated mistake is successively utilized, calibrates and finishes until the first order, most
The output digital quantity of every grade of 1.5bit is obtained eventually.
To obtain final 8bit output valve, misplace be added when, from afterbody plus, when being added to, to be calibrated grade defeated
After digital quantity out, the margin of error of this grade is subjected to linear calibration to obtained long number amount again.
When calibrating to the pipeline ADC first order, control signal control selections device can be to it in this grade of prover time
Sub-DAC injects the pseudo-random sequence that PN sequencer generates, and simultaneously closes off to other pipeline stages and injects pseudo-random sequence
Channel.
The embodiment provide a kind of calibration before pipeline ADC transfer curve as shown in figure 4, calibration after assembly line
ADC transfer curve is as shown in figure 5, error has been calibrated.Here calibration be to capacitance mismatch and amplifier finite gain the two
The piece calibration of error component does not consider that two error components are individually worth.Digital quantity after calibration is the reality of the same level
Digital output, during dislocation after participating in is added.
Due to needing to calibrate the digital quantity of the same level, the remaining difference of rear level production line quantization includes two parts, that is, is really needed
The pseudo-random sequence of the remaining difference and superposition of quantization.Level production line quantized value after true in order to obtain, need to be superimposed into puppet
The value of random sequence balances out.Contrast equation (2) and formula (3) can be seen that this PNV in formula (3)cal(1+α)(1
+ δ) it is superposition item, as long as this is balanced out, so that it may real digital quantization value of the level production line to surplus after reduction.By
In PNVcalValue it is known that and the value of (1+ α) (1+ δ) we passed through formula (4) and obtained, so we are by PNVcal(1+
α) (1+ δ) corresponding digital quantity is subtracted from the digital output that rear level production line quantifies, and has just obtained rear level production line quantization
The true value of digital quantity.Here it should be particularly noted that, PNVcal(1+ α) (1+ δ) corresponding digital quantity be following stage relative to
The digital quantity that calibration grade quantifies the value, due to the amplification between grade, after addition value not at the same level, corresponding digital quantity
Value is also different.For the first order, which is latter 7 grades 128 quantizations to it；For the second level, which is then latter 6 grades to it
64 quantizations, and so on.
During calibrating entire pipeline ADC, due to the amplification between pipeline stages, in higher preceding series,
Influence of the error to entire pipeline ADC is bigger.In view of calibration effect and prover time, here only to before pipeline ADC 4
Grade is calibrated.Fig. 6 is preceding 4 grades of schematic diagrames calibrated of a kind of pair of pipeline ADC provided by Embodiment 2 of the present invention, school
Quasi- sequence are as follows: successively calibrated forward from the 4th grade, until being calibrated to the first order.After having calibrated certain grade, after being calibrated of this grade
Digital output just replace former output, participate in next calibration.By control signaling module control selections device by PN sequence
The pseudo-random sequence that column generator generates is input to calibration grade, successively controls the sequence of calibration.After the calibration of every level-one requires
Data and the corresponding pseudo-random sequence of grade quantization.For the 4th grade of calibration, just only need last 3 grades of digital quantity with it is corresponding
Pseudo-random sequence；For 3rd level, then last 3 grades of digital quantity is needed, with the 4th grade of digital quantity calibrated；For the 2nd grade,
Last 3 grades of digital quantity is then needed, with the 3rd calibrated, 4 grades of digital quantities；For the 1st grade, then last 3 grades of number is needed
Amount, with all data calibrated in front.When calibrating this 1-4 grades, shared four states, each state calibration level-one, each other not
Conflict.For each state, the rear class data after having calibrated are added with error compensation, remove the pseudo-random sequence of addition, reduction
Digital quantity originally.
To obtain final numeral output, rear class digital quantity is needed, three Xiang Zucheng of position and error compensation is calibrated.5-7
Grade data, due to itself be not involved in the problems, such as calibration, can be directly added and be obtained with error compensation by the digital quantity quantified, then with it is preceding
Grade data are added to obtain final digital quantity；If 4-7 grades of data are by by missing in the align mode for carrying out the 4th grade
Rear 3 grades of data of difference compensation are added with the 4th grade of data being calibrated and obtain, and after carrying out once linear calibration, then with preceding series
According to being added to obtain final digital quantity；If 4-7 grades of data by error by mending in the align mode for carrying out 3rd level
The rear 4 grades of data repaid, the 4th grade of data have been calibrated that (it belongs to the rear class of 3rd level, therefore also contains and missed at this time
The part of difference compensation) and 4 grades of data be also carried out linear gauging, then be added to obtain final number with prime data
Amount；And so on, obtain the digital quantity of the final output under each state.
The purpose of linear gauging is to correct the linearity error that data after certain grade of calibration generate.Error is previously mentioned due to above-mentioned
Influence, every level-one it is remaining difference amplification be no longer accurate 2 times, the resolution ratio of practical pipeline ADC is (with 8 bit stream described in example
For waterline ADC) it is also no longer 256 grades, but it is 256 grades for standard that actual digital output, which is still with 8, so needing to be added
Error caused by linear gauging amendment thus.Same principle is also applied for the amendment of rear class data needed for being calibrated grade.
In conclusion overcoming the embodiment of the invention provides a kind of ADC digital background calibration algorithm applied to assembly line
Modification of the existing calibration algorithm to analog circuit can calibrate the error as caused by capacitance mismatch and amplifier finite gain simultaneously, and
ADC is not interrupted normally to work, does not change original Analog Circuit Design, and calibration cost is small, and calibration accuracy is high.
Those of ordinary skill in the art will appreciate that: attached drawing is the schematic diagram of one embodiment, module in attached drawing or
Process is not necessarily implemented necessary to the present invention.
As seen through the above description of the embodiments, those skilled in the art can be understood that the present invention can
It is realized by the mode of software plus required general purpose hardware unit.Based on this understanding, technical solution of the present invention essence
On in other words the part that contributes to existing technology can be embodied in the form of software products, the computer software product
It can store in storage medium, such as ROM/RAM, magnetic disk, CD, including some instructions are used so that a computer equipment
(can be personal computer, server or the network equipment etc.) executes the certain of each embodiment or embodiment of the invention
Method described in part.
All the embodiments in this specification are described in a progressive manner, same and similar portion between each embodiment
Dividing may refer to each other, and each embodiment focuses on the differences from other embodiments.Especially for device or
For system embodiment, since it is substantially similar to the method embodiment, so describing fairly simple, related place is referring to method
The part of embodiment illustrates.Apparatus and system embodiment described above is only schematical, wherein the conduct
The unit of separate part description may or may not be physically separated, component shown as a unit can be or
Person may not be physical unit, it can and it is in one place, or may be distributed over multiple network units.It can root
According to actual need that some or all of the modules therein is selected to achieve the purpose of the solution of this embodiment.Ordinary skill
Personnel can understand and implement without creative efforts.
The foregoing is only a preferred embodiment of the present invention, but scope of protection of the present invention is not limited thereto,
In the technical scope disclosed by the present invention, any changes or substitutions that can be easily thought of by anyone skilled in the art,
It should be covered by the protection scope of the present invention.Therefore, protection scope of the present invention should be with scope of protection of the claims
Subject to.
Claims (7)
1. a kind of digital background calibration device of pipeline ADC characterized by comprising
The pipeline ADC is made of the subflow waterline and calibration circuit of multi-stage cascade, and every grade of subflow waterline includes sampling/holding
Circuit, surplus amplifier, Sub-ADC and Sub-DAC, the calibration circuit and every level-one subflow waterline circuit connection；
Analog signal passes sequentially through every level-one subflow waterline of pipeline ADC, is calibrated grade subflow waterline in analog input
Meanwhile the pseudo-random sequence that generates of the calibration circuit be input into it is described be calibrated in grade Sub-DAC of subflow waterline, it is described
It is calibrated grade analog quantity of subflow waterline output and pseudo-random sequence enters rear stage subflow after surplus amplifier jointly
Waterline；
The calibration circuit utilizes pseudo-random sequence and the sub- pipeline conversion of all rear classes for being calibrated grade subflow waterline
Digital quantity after calibration calibrates the digital quantity for being calibrated the sub- pipeline conversion of grade, obtains described being calibrated grade
Digital quantity after the calibration of pipeline conversion；
The calibration circuit includes PN sequencer, selector, control signaling module, error compensation module, digital calibration mould
Block and digital quantity summation module, the digital calibration block includes the sub- calibration module being arranged in each subflow waterline；
The PN sequencer, for generating pseudo-random sequence；
The selector, for and the PN sequencer, control signaling module connect and subflow waterline at different levels in Sub-
DAC connection；
The control signaling module, for control the selector certain grade of subflow waterline prover time to certain grade of subflow
Waterline injects pseudo-random sequence, simultaneously closes off the channel to other grade of subflow waterline injection pseudo-random sequence；Error is controlled simultaneously
Compensating module provides and is calibrated grade corresponding error compensation value of subflow waterline；
The error compensation module, according to control signal control, output is calibrated grade corresponding error compensation value of subflow waterline, should
Error compensation value is pseudo-random sequence multiplied by related coefficient；
The sub- calibration module being calibrated in grade subflow waterline is used to connect with the Sub-ADC being calibrated in grade subflow waterline, utilizes
Digital quantity after the calibration of pseudo-random sequence and the sub- pipeline conversion of all rear classes for being calibrated grade subflow waterline, to described
The digital quantity of Sub-ADC conversion is calibrated, and obtains described being calibrated the digital quantity after the calibration of the sub- pipeline conversion of grade；
The digital quantity summation module carries out dislocation addition for the digital quantity after the calibration to sub- pipeline conversions at different levels, obtains
The digital quantity exported to entire pipeline ADC.
2. the digital background calibration device of pipeline ADC according to claim 1, which is characterized in that defeated by selector
It is mutually staggered in time to the pseudo-random sequence of subflow waterlines at different levels out.
3. the digital background calibration device of pipeline ADC according to claim 2, it is characterised in that:
The sub- calibration module being calibrated in grade subflow waterline, for receiving all rear classes for being calibrated grade subflow waterline
The feedback signal of subflow waterline, the feedback signal include the digital quantity after the calibration of the sub- pipeline conversion of all rear classes, by institute
It states feedback signal to be calibrated the pseudo-random sequence that grade subflow waterline receives with described and be multiplied, obtains calculated value, then will be multiple
To the calculated value carry out cumulative summation and be averaged, obtain it is described be calibrated a grade margin of error for subflow waterline, by the margin of error
With the Sub-ADC conversion digital quantity is multiplied, obtain described in be calibrated the digital quantity after the calibration of the sub- pipeline conversion of grade.
4. the digital background calibration device of pipeline ADC according to claim 3, it is characterised in that:
The sub- calibration module being calibrated in grade subflow waterline is also used to all rear class subflow water from calibration grade subflow waterline
The digital quantity of line conversion, subtracts and is calibrated grade error compensation value of subflow waterline and is calibrated multiplying for grade margin of error of subflow waterline
It accumulates, to subtract in the digital quantity the sub- pipeline conversion of all rear classes of calibration grade subflow waterline to the quantization of pseudo-random sequence
It goes, restores original digital quantity, the digital quantity of reduction is added for misplacing.
5. the digital background calibration device of pipeline ADC according to claim 3, it is characterised in that:
The digital quantity summation module, for misplace be added when, from adding afterbody subflow waterline, when being added to by school
After the digital quantity of quasi- grade subflow waterline output, linear school is carried out again to obtained long number amount with the margin of error of this grade
Standard, the margin of error are described be calibrated in grade subflow waterline as capacitance mismatch and error caused by amplifier finite gain.
6. the digital background calibration device of pipeline ADC according to claim 3, it is characterised in that:
The sample/hold circuit being calibrated in grade subflow waterline, for receiving the analog signal V of prime inputin, to described
Analog signal VinAfter being sampled, it is transferred to the Sub-ADC and surplus amplifier being calibrated in grade subflow waterline；
The Sub-ADC being calibrated in grade subflow waterline, the analog signal for transmitting the sample/hold circuit
VinDigital quantity is converted to, the digital quantity is transferred to the sub- calibration module and Sub-DAC being calibrated in grade subflow waterline；
The Sub-DAC being calibrated in grade subflow waterline, for receiving the digital quantity and calibration circuit of the Sub-ADC output
The pseudo-random sequence P N of output exports analog signal Vres,
Vres=(1+ δ) [(2+ α) Vin-(1+α)(b Vref-P N·Vcal)]
=(1+ δ) [(2+ α) Vin-(1+α)b Vref]+P N·Vcal(1+α)(1+δ)
Wherein, VcalAnd VrefFor constant, α and δ respectively represent non-ideal factor caused by capacitance mismatch and amplifier finite gain
Coefficient, b indicate the digital output of the level structure assembly line；
The surplus amplifier being calibrated in grade subflow waterline, for receiving the analog signal V of Sub-DAC outputresWith adopt
Sample/holding circuit output analog signal Vin, to analog signal VinSubtract analog signal VresValue amplify after, be transferred to
Rear stage subflow waterline.
7. the digital background calibration device of pipeline ADC according to claim 6, it is characterised in that:
The sub- calibration module being calibrated in grade subflow waterline is calibrated a grade margin of error for subflow waterline for calculating
Wherein E () indicates that the multiple data calculated in bracket are carried out with summation is averaged, VresIt is exported to be calibrated the surplus of grade,
PN is pseudo-random sequence, VrefWith VcalFor constant, according to pseudo-random sequence characteristic,This
Summation tends to 0 after being averaged, and PN2=1, PN2(1+δ)(1+α)VrefThis summation is (1+ δ) (1+ α) V after being averagedref,
Therefore it obtains being calibrated grade corresponding margin of error of subflow waterline.
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| CN106656180A (en) * | 2016-10-18 | 2017-05-10 | 东南大学 | Calibration circuit and calibration method applied to input kickback non-linearity of SHA-less analog-to-digital converter |
| CN106506005B (en) * | 2016-10-26 | 2019-04-09 | 东南大学 | Eliminate the background calibration circuit and method of production line analog-digital converter transmission curve breakpoint |
| CN107994903B (en) * | 2017-12-15 | 2021-07-16 | 北京特邦微电子科技有限公司 | Analog-to-digital conversion circuit and pipeline analog-to-digital converter |
| CN110971235B (en) * | 2019-10-29 | 2022-11-15 | 东南大学 | Background calibration method for capacitor mismatch and interstage gain error of pipeline SAR ADC |
| CN111740742A (en) * | 2020-05-29 | 2020-10-02 | 红鼎互联(广州)信息科技有限公司 | High-speed and high-precision image signal analog-to-digital conversion circuit |
| CN111740740B (en) * | 2020-06-22 | 2022-06-21 | 同济大学 | Pipeline successive approximation analog-digital converter background gain calibration circuit and method |
| CN113114247B (en) * | 2021-04-19 | 2022-05-24 | 电子科技大学 | Pipeline ADC interstage gain calibration method based on comparison time detector |
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| CN204216883U (en) * | 2014-12-04 | 2015-03-18 | 上海贝岭股份有限公司 | The background calibration circuit of pipeline ADC |
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| US6606042B2 (en) * | 2001-05-23 | 2003-08-12 | Texas Instruments Incorporated | True background calibration of pipelined analog digital converters |
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| CN102025373A (en) * | 2009-09-16 | 2011-04-20 | 复旦大学 | Digital background calibration circuit |
| CN204216883U (en) * | 2014-12-04 | 2015-03-18 | 上海贝岭股份有限公司 | The background calibration circuit of pipeline ADC |
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