CN102082578B - General ultra-wideband reception method - Google Patents
General ultra-wideband reception method Download PDFInfo
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- CN102082578B CN102082578B CN 201110053267 CN201110053267A CN102082578B CN 102082578 B CN102082578 B CN 102082578B CN 201110053267 CN201110053267 CN 201110053267 CN 201110053267 A CN201110053267 A CN 201110053267A CN 102082578 B CN102082578 B CN 102082578B
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Abstract
The invention relates to a general ultra-wideband reception method. The method comprises the processes of switch selection, bandpass filtering, parallel and alternate sampling of a high-speed analog-digital (A/D) converter and the like, wherein the whole receiving frequency band is divided into a plurality of frequency subbands; a corresponding bandpass filter is selected through a selector switch at the front end of a radio frequency and used for filtering; and then sampling is carried out on bandpass signals by utilizing parallel and alternate sampling way of multichip A/D phases; and therefore, the purpose of ultra-wideband reception is achieved.
Description
Technical field
The present invention relates to a kind of universal broadband method of reseptance, relate in particular to a kind of general ultra broadband method of reseptance.
Background technology
Receiver based on software radio requires to have broadband coverage, sensitivity preferably, performances such as the ability of real time signal processing usually.Its design philosophy is that A/D converter (the A/D converter is the semiconductor element that analog quantity is changed into digital quantity) is simulated link near antenna, the minimizing of trying one's best as far as possible, and radio function as much as possible is realized with software.Optimal no more than directly carrying out the A/D conversion at radio-frequency front-end, work such as thereafter channel separation, demodulation are all finished with software.
Receiver structure based on software radio can be divided into three kinds at present: radio frequency low pass sampled digital structure, radio frequency bandpass sampling digitlization structure and Wideband Intermediate Frequency band lead to the digitlization structure.
Radio frequency low pass sample mode will carry out from the signal that antenna is come in just carry out sampled digitalization after wideband low pass filtering is amplified.This mode is close to desirable software radio, but it not only has very high requirement to the performance of A/D converter such as switching rate, bandwidth of operation, dynamic range etc., also high especially to the processing speed requirement of follow-up DSP or ASIC simultaneously, because the required sampling rate of radio frequency low pass sampling is the twice of radio frequency operation bandwidth highest frequency at least.With current device level, realizability is not high.
The main difference point of radio frequency bandpass sampling software radio architecture and low pass sampling software radio architecture is, adopted the electrically tunable filter of bandwidth relative narrower before the A/D, carries out bandpass sampling according to required processing bandwidth then.Just not high to the requirement of sampling rate like this, also can reduce greatly the processing speed of follow-up DSP thereupon.But it is pointed out that this radio frequency bandpass sampling software radio architecture to the requirement (in fact mainly being the rate request to sampling holder among the A/D) of A/D bandwidth of operation still or than higher.
The structure of Wideband Intermediate Frequency bandpass sampling software radio architecture and present Intermediate Frequency Digital Receiver is similarly, has all adopted repeatedly mixing system or has been the superhet system.The main feature of this Wideband Intermediate Frequency bandpass sampling software radio architecture is that intermediate-frequency bandwidth is wideer, and functions such as all modulation are all realized by software.Obviously, this Wideband Intermediate Frequency bandpass sampling software radio architecture is the easiest realization in above-mentioned three kinds of structures, and is minimum to the performance requirement of device, but it from the requirement of desirable software radio farthest, and extensibility, flexibility also are the poorest.
Because it is wideer that the frequency range that covers of software radio generally all requires, for example from 0 GHz to 2.2GHz, as software radio, only in this way wide frequency range just has adaptability widely.At least need be greater than 4.4GHz but so wide frequency range adopts the Nyquist low pass to sample required sampling rate, except A/D device factor, the signal of rear end is handled and also can't be satisfied so high processing requirements, and this obviously is unpractical at present.
Summary of the invention
Signal at the rear end that exists in the prior art is handled the high frequency sampling rate that can't satisfy front end, therefore need provide a kind of general ultra broadband method of reseptance.
The invention discloses a kind of general ultra broadband method of reseptance, it may further comprise the steps:
A. the radiofrequency signal that receives is divided into N frequency sub-band, the bandpass sampling law is satisfied in the division of described frequency range, i.e. centre frequency f
0=(2n+1) B/2;
B. bank of filters is made of N band pass filter, the passband of n band pass filter is (n-1) B to nB, frequency range according to the signal place is selected n corresponding band pass filter by processing module control selector switch, useful signal is passed through and the inhibition zone external noise, the back signal aliasing prevents from sampling;
C. according to parallel sampling A/D converter quantity signal is carried out the merit branch: be provided with M sheet A/D parallel sampling, then signal carried out 1:M merit branch, M=2B/ f
s, the phase place of the necessary inhibit signal of signal after merit is divided is consistent with amplitude;
D. utilize the A/D converter to divide the mode of phase alternation sampling that bandpass signal is sampled, the phase difference of every A/D sampling clock is 2 π/M, and then the equivalent sampling speed of sheet A/D is M * f
s, the result of bandpass sampling be positioned at signal on (nB, (n+1) B) different frequency bands all use and is positioned at (0, B) on identical base-band signal spectrum represent;
E. the data after the sampling are sent into FPGA, according to the sequencing of sampling data are rearranged combination;
Wherein, the frequency sub-band bandwidth of B for dividing, N is the frequency sub-band number, n=0,1 ... N-1, f
sBe monolithic A/D sampling rate.
Preferably, the A/D converter divides phase alternation sampling needs to produce different phase clocks among the above-mentioned steps D, described phase clock adopts digital frequency synthesizer PLL and clock adjustment chip to constitute, PLL produces the sampling reference clock, and clock adjustment chip distributes and regulate the phase place of each road sampling clock to reference clock.
Beneficial effect of the present invention is: general ultra broadband method of reseptance disclosed by the invention is divided into a plurality of frequency sub-band with whole reception frequency range, select corresponding band pass filter to carry out filtering by the selector switch of radio-frequency front-end, utilize the mode of multi-disc A/D phase-splitting parallel-by-bit alternating sampling that bandpass signal is sampled then, thereby reach the purpose that ultra broadband receives.Compare with current super-heterodyne architecture commonly used, this method has reduced simulation links such as down-conversion, avoided the influence of simulation link to signal, the A/D that utilizes the relative low speed of multi-disc has well solved the problem that the high sampling rate of A/D device and high-resolution are difficult to take into account in the mode of parallel alternating sampling to the radio frequency Direct Sampling, receive that signal bandwidth is wide, flexibility is strong, simple in structure, have good versatility and realizability.
Description of drawings
Fig. 1 is that ultra broadband of the present invention receives the processing procedure block diagram.
Fig. 2 is high-speed AD converter parallel sampling schematic diagram of the present invention.
Embodiment
Describe the specific embodiment of the present invention in detail below in conjunction with Figure of description.
Ultra broadband of the present invention as shown in Figure 1 receives the processing procedure block diagram, the invention discloses a kind of general ultra broadband method of reseptance, and it may further comprise the steps:
A. the radiofrequency signal that receives is divided into N frequency sub-band, the bandpass sampling law is satisfied in the division of described frequency range, i.e. centre frequency f
0=(2n+1) B/2(wherein, the frequency sub-band bandwidth of B for dividing, N is the frequency sub-band number, establishing the input radio frequency signal bandwidth is B
In, frequency range number and frequency sub-band bandwidth need satisfy N=B
In/ B, n=0,1 ... N-1).
B. bank of filters constitutes (N is the frequency sub-band number) by N band pass filter, the passband of n band pass filter is (n-1) B to nB (n=1,2 ... N), frequency range according to the signal place is selected n corresponding band pass filter by processing module control selector switch, useful signal is passed through and the inhibition zone external noise, the back signal aliasing prevents from sampling.
C. according to parallel sampling A/D converter quantity signal being carried out the merit branch (is provided with M sheet A/D parallel sampling, then signal is carried out 1:M merit branch, M=2B/ monolithic AD sampling rate f
s), the phase place of the necessary inhibit signal of signal after merit is divided is consistent with amplitude.
D. utilize the A/D converter to divide the mode of phase alternation sampling that bandpass signal is sampled, the sampling rate of establishing monolithic A/D is f
s, the phase difference of every A/D sampling clock is 2 π/M, then the equivalent sampling speed of sheet A/D is M * f
sThe result of bandpass sampling be positioned at (nB, (n+1) B) (n=0,1,2 ...) signal on the different frequency bands all use and be positioned at (0, B) go up identical base-band signal spectrum and represent.
E. the data after the sampling are sent into FPGA, according to the sequencing of sampling data are rearranged combination.
Preferably, the A/D converter divides phase place sampling needs to produce different phase clocks among the above-mentioned steps D, described phase clock adopts digital frequency synthesizer PLL and clock adjustment chip to constitute, PLL produces the sampling reference clock, clock adjustment chip distributes and regulates the phase place of each road sampling clock to reference clock, the clock track lengths must strictly equate, avoids clock phase error.
Further describe embodiments of the present invention below for example, in this real-time example, suppose that receiving coverage is that 0GHz is to 2.2GHz, whole frequency range is divided into 5 sections, every section bandwidth 440MHz, in conjunction with the bandpass sampling law, need the sampling ability of 880MSPS at least, realized by 4 220MSPS A/D parallel samplings.If useful signal appears at 880MHz～1320MHz frequency range, at first selecting passband is that 880MHz～1320MHz band pass filter carries out filtering to signal, useful signal is passed through and the inhibition zone external noise, be divided into 4 the tunnel through the power splitter merit then, 4 road signals need the phase place of inhibit signal consistent with amplitude, send 4 A/D parallel samplings.The generation of out of phase clock is key of the present invention, can adopt digital frequency synthesizer PLL to add clock adjustment chip finishes, PLL produces the sampling reference clock, clock adjustment chip distributes and regulates the phase place of each road sampling clock to reference clock, the clock track lengths must strictly equate, avoid clock phase error, as shown in Figure 2, PLL produces the 220MHz clock, clock adjustment chip with clock be divided into 4 the tunnel and the sampling clock of every A/D differ pi/2 successively, the equivalent sampling speed of such 4 A/D is 880MSPS, and the data after the sampling are sent FPGA to carry out amalgamation and handled.
Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of making, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (1)
1. general ultra broadband method of reseptance, it may further comprise the steps:
A. the radiofrequency signal that receives is divided into N frequency sub-band, the bandpass sampling law is satisfied in the division of described frequency range, i.e. centre frequency f
0=(2n+1) B/2;
B. bank of filters is made of N band pass filter, the passband of n band pass filter is (n-1) B to nB, frequency range according to the signal place is selected n corresponding band pass filter by processing module control selector switch, useful signal is passed through and the inhibition zone external noise, the back signal aliasing prevents from sampling;
C. according to parallel sampling A/D converter quantity signal is carried out the merit branch: be provided with M sheet A/D parallel sampling, then signal carried out 1:M merit branch, M=2B/ f
s, the phase place of the necessary inhibit signal of signal after merit is divided is consistent with amplitude;
D. utilize the A/D converter to divide the mode of phase alternation sampling that bandpass signal is sampled, the phase difference of every A/D sampling clock is 2 π/M, and then the equivalent sampling speed of sheet A/D is M * f
s, the result of bandpass sampling be positioned at signal on (nB, (n+1) B) different frequency bands all use and is positioned at (0, B) on identical base-band signal spectrum represent;
E. the data after the sampling are sent into FPGA, according to the sequencing of sampling data are rearranged combination;
Wherein, the frequency sub-band bandwidth of B for dividing, N is the frequency sub-band number, n=0,1 ... N-1, f
sBe monolithic A/D sampling rate;
The A/D converter divides phase alternation sampling needs to produce different phase clocks among the described step D, described phase clock adopts digital frequency synthesizer PLL and clock adjustment chip to constitute, PLL produces the sampling reference clock, and clock adjustment chip distributes and regulate the phase place of each road sampling clock to reference clock.
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| CN102655417B (en) * | 2012-04-20 | 2015-01-21 | 华为技术有限公司 | Wireless local area network (WLAN) equipment and method for suppressing interference of wireless local area network equipment |
| CN103441770B (en) * | 2013-08-26 | 2015-07-08 | 上海航天测控通信研究所 | Wideband receiving channels, receiver and receiving method with amplitude and phase compensation |
| CN106031046B (en) | 2014-03-20 | 2019-01-11 | 华为技术有限公司 | Compressed sensing based signal processing method and device |
| CN104022745B (en) * | 2014-06-03 | 2017-01-25 | 成都嘉晨科技有限公司 | ultra-wideband high-power power amplifier device |
| CN107810606B (en) * | 2015-05-01 | 2020-09-08 | 安德鲁无线系统有限公司 | Non-duplexer architecture for telecommunications systems |
| CN105846835B (en) * | 2016-03-16 | 2018-03-02 | 中国矿业大学 | A kind of more bandpass signal method of reseptances of software radio |
| CN106849950A (en) * | 2016-12-29 | 2017-06-13 | 中国电子科技集团公司第五十研究所 | Radiofrequency signal A/D conversion system and method based on multi tate parallel sampling |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1567732A (en) * | 2003-07-02 | 2005-01-19 | 电子科技大学 | A novel method for receiving ultra wideband signal |
| CN101587498A (en) * | 2009-06-24 | 2009-11-25 | 北京理工大学 | Dual-mode signal acquiring board |
| CN101888247A (en) * | 2010-07-02 | 2010-11-17 | 北京工业大学 | Self-adoptive correcting device of mismatch error of time-interleaved analog-digital converter |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1567732A (en) * | 2003-07-02 | 2005-01-19 | 电子科技大学 | A novel method for receiving ultra wideband signal |
| CN101587498A (en) * | 2009-06-24 | 2009-11-25 | 北京理工大学 | Dual-mode signal acquiring board |
| CN101888247A (en) * | 2010-07-02 | 2010-11-17 | 北京工业大学 | Self-adoptive correcting device of mismatch error of time-interleaved analog-digital converter |
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