CN104007300B - Digital fluorescence oscilloscope stochastical sampling disturbs circuitry phase method for designing - Google Patents

Abstract

The invention belongs to electronic measuring instrument field, the digital fluorescence oscilloscope stochastical sampling of the present invention disturbs circuitry phase method for designing, comprise the steps: that (1) adopts measured signal as trigger source, when signal level is increased beyond rising edge triggering level or signal level descends below trailing edge triggering level, trigger circuit and produce a triggering pulse, this pulse activation data acquisition circuit, and once sample under sampling clock effect, thus obtaining the value in signal a certain moment；(2) owing to sampling clock and signal are independent from, this phase contrast will be a random value, sampled value and this phase difference value are stored simultaneously, arrange according to phase difference value size order, when stacking fold is sufficiently large, the waveform sampling process of all measured signals will be spread all over, thus reconstructing the complete sample waveform of echo signal.The precise phase realizing optional position in the clock cycle controls, and is especially suitable for sequential fine setting application, to arranging and keeping sequential alignment very crucial.

Description

Digital fluorescence oscilloscope stochastical sampling disturbs circuitry phase method for designing

Technical field

The invention belongs to electronic measuring instrument field, what particularly relate to that a kind of digital fluorescence oscilloscope stochastical sampling disturbs circuitry phase realizes method.

Background technology

In high-speed data acquistion system, the capture ability of signal is received the restriction of the highest sampling rate of A/D by real-time sampling.According to Nyquist sampling thheorem, if input signal highest frequency is fs, then systematic sampling rate fc must is fulfilled for the condition of waveform reconstruction, i.e. fc >=2fs, for meeting the needs of actual acquisition system, generally should meet fc >=5fs.Visible, along with the raising of frequency input signal, the requirement of A/D converter is also harsher.

Stochastical sampling system, by the multiple repairing weld to periodic signal, is resequenced the data obtained of sampling in signal different cycles, it is achieved the signal waveform of reconstruction.Working in the high-speed data acquistion system of stochastical sampling pattern, signal frequency can be significantly high, and sample frequency can be relatively low.

What random sampling technique realized it is critical only that: sampling instant is random relative to the time delay of trigger point every time, and namely this length of delay is uniformly distributed within a sampling period.But it is found that along with the raising of frequency input signal, the randomness between trigger point and sampling instant weakens in actual application, directly result in an equivalent sampling time increase, reduced the waveform turnover rate of data collecting system.For this, by sampling clock artificially adds disturbance, make sampling instant tend to random distribution relative to the delay of trigger point, it is possible to improve waveform turnover rate.

Summary of the invention

The technique effect of the present invention can overcome drawbacks described above, it is provided that a kind of digital fluorescence oscilloscope stochastical sampling disturbs circuitry phase method for designing, in fact shows the precise phase of optional position in the clock cycle and controls.

For achieving the above object, the present invention adopts the following technical scheme that it comprises the steps:

(1) adopt measured signal as trigger source, when signal level is increased beyond rising edge triggering level or signal level descends below trailing edge triggering level, trigger circuit and produce a triggering pulse, this pulse activation data acquisition circuit, and once sample under sampling clock effect, thus obtaining the value in signal a certain moment, by measuring the phase contrast of each ADC sample sequence starting point and signal trigger instants, just can determine that this sample sequence position in signal waveform；

(2) owing to sampling clock and signal are independent from, this phase contrast will be a random value, sampled value and this phase difference value are stored simultaneously, arrange according to phase difference value size order, when stacking fold is sufficiently large, the waveform sampling process of all measured signals will be spread all over, thus reconstructing the complete sample waveform of echo signal.

Owing to sampling clock and signal are independent from, this phase contrast will be a random value, sampled value and this phase difference value are stored simultaneously, according to difference size order arrangement, when stacking fold n is sufficiently large, all possible waveform sampling process can being spread all over, thus reconstructing the complete sample waveform of echo signal, being namely equal to a complete waveform sampling.See that accompanying drawing 2 is that the waveform of different sampling instant discharge according to the size order of phase contrast, composition complete waveform process.

ADC sample sequence and the phase contrast triggering original position are a random value, and minimum is 0, is a sampling period T to the maximum.Difference according to required equivalent sampling rate, need to be done the division of different accuracy one sampling period, only drop on the sample data sequence side in different demarcation interval and participate in final arrangement, thus can ensure that the final group of waveform gone out has spread all over each several part in a cycle.If required equivalent sampling rate is far above sample frequency, such as, when ADC real-time sampling rate is 125MHz, in order to realize the equivalent sampling rate of 25GHz, mono-sampling period (8ns) of ADC must be divided into 200 intervals, when all intervals are all spread all over then, group a frame complete waveform can be gone out.

In the ideal case, sampling clock is likely located at any position of signal, and namely the interval (trigger phase difference) between sampled point and trigger point is a random value, and such addition of waveforms regrouping process can be quickly completed.But the raising along with frequency input signal, the randomness of this phase contrast weakens, it is possible to have quite a few phase difference value cannot traverse in for a long time, and its direct result is exactly the turnover rate affecting signal restructuring, cause whole data collecting system delay of response, affect overall performance.For this, we utilize the FPGA sampling clock being ADC to add and disturb phase module.Producing to trigger pulse when triggering circuit, after sampling process is taken turns in activation one, the data of collection according to the difference of respective phase contrast, can be sent into FPGA and carry out waveform restructuring.In this processing procedure, if sampling clock is carried out well-regulated phase shift, when next round triggering collection will be made to start, the phase contrast of ADC sample sequence starting point and signal trigger instants has bigger change, thus increasing the randomness of phase contrast between sampled point and trigger point.

Disturbing ADC sampling clock to have mutually and multiple realize method, as adopted discrete component to realize, but there is the shortcomings such as circuit complexity, poor reliability in this method.The present invention utilizes the massive parallelism feature of FPGA device, is carrying out in the process of subsequent treatment to the data under gathering, it is achieved that the fine time delay of ADC sampling clock, has that circuit is simple, function strong, amendment is convenient and high reliability.Virtex4 Series FPGA is the main flow PLD of Xilinx company, every device has 4～12 digital dock manager DCM (DigitalClockManager), each DCM has been provided which clock de-skewing, frequency synthesis and phase shift, even applied range, the powerful Clock management function such as dynamic recognition.It utilizes delay-locked loop DLL, eliminating the swing between clock pad and internal clocking pin, it also provides for multiple clock control technology simultaneously, it is achieved in the clock cycle, the precise phase of optional position controls, it is especially suitable for sequential fine setting application, to arranging and keeping sequential alignment very crucial.

Accompanying drawing explanation

Fig. 1 is trigger phase difference and the restructuring waveform position graph of a relation of the present invention；

Fig. 2 is the stochastical sampling waveform regrouping process figure of the present invention；

Fig. 3 is for disturbing circuitry phase workflow diagram；

Fig. 4 is Dcm controlled state machine；

Fig. 5 is that Phase_Disturbence disturbs phase module simulation waveform；

Fig. 6 is the trigger phase difference distribution of unperturbed phase module；

Fig. 7 is that after phase module is disturbed in interpolation, trigger phase difference is distributed.

Detailed description of the invention

The digital fluorescence oscilloscope stochastical sampling of the present invention disturbs circuitry phase method for designing, comprises the steps:

(1) adopt measured signal as trigger source, when signal level is increased beyond rising edge triggering level or signal level descends below trailing edge triggering level, trigger circuit and produce a triggering pulse, this pulse activation data acquisition circuit, and once sample under sampling clock effect, thus obtaining the value in signal a certain moment, by measuring the phase contrast of each ADC sample sequence starting point and signal trigger instants, just can determine that this sample sequence position in signal waveform；

(2) owing to sampling clock and signal are independent from, this phase contrast will be a random value, sampled value and this phase difference value are stored simultaneously, arrange according to phase difference value size order, when stacking fold is sufficiently large, the waveform sampling process of all measured signals will be spread all over, thus reconstructing the complete sample waveform of echo signal.

ADC sample sequence and the phase contrast triggering original position are a random value, and minimum is 0, is a sampling period T to the maximum.

The input/output control signal disturbing circuitry phase is as follows: clk_main_control is circuit master control and Phaseshift controlling clock, is also clock simultaneously；Clk_sample_in is input ADC sampling clock；Clk_sample_out is the output DAC sampling clock through phase shift；Disturb_en_edge is the input signal cable controlling the phase shift beginning and ending time；Lock_ready is prime DCM locking signal.See accompanying drawing 3: disturb circuitry phase workflow diagram.

Namely the standard output port of DCM has tetra-kinds of phase outputs of CLK0_OUT, CLK90_OUT, CLK180_OUT, CLK270_OUT, has variable phase shift and fixed phase drift both of which simultaneously.In the present invention, in order to obtain PHASE DISTRIBUTION evenly, have employed variable phase shift pattern.In variable phase shift pattern, phase place dynamically can be moved the 1/256 of input clock cycle by user repeatedly forward or backward, and its Phaseshift controlling pin is as shown in table 1.When PSEN signal is effective, the big I of phase shift is determined to increase or reduce by the level value of the PSINCDEC signal Tong Bu with controlling clock PSCLK.

Control signal under table 1.DCM_ADV phase shifting modes

The output signal PSDONE of DCM is Tong Bu with phase shifted clock, and the high level in its one phase shifted clock cycle of output represents that phase shift is complete, and represents that a new phase shift can start simultaneously.During input, clk_sample_in is after DCM phase-shift circuit phase shift, obtain the clock output clk_out1 of respective phase contrast 90 ＇, clk_out2, clk_out3, clk_out4, Jiang Ci tetra-road signal carries out after timesharing switching through Disturb_clk_mux_4 module, obtains the required sampling clock clk_sample_out through disturbing phase.Whole system control flow is as shown in Figure 4:

When being operated in variable phase shift pattern due to DCM, control signal is complex, and the dephasing processes of sampling clock can not be had influence on normal sampling process, uses special module Dcm_control_gen that it is controlled for this.After system reset, state machine enters original state state 1, generation phase shift DCM reset signal after prime DCM locking signal is received until state machine, to be checked measure phase shift DCM locking after, enter state 2, and detect disturb_en_edge signal, state 3 is entered when disturb_en_edge is effective, and to the high level that PSEN, PSINC compose a phase shifted clock cycle, make DCM carry out a phase shift；When phase shifted clock rising edge arrives, then unconditionally proceed to state 4；When PSDONE output DCM being detected becomes 1, if judging, whether count value arrives default NUM value and reaches, after phase shifted clock rising edge arrives, then return state 2, otherwise then give PSEN again, PSINC composes the high level in a phase shifted clock cycle, after phase shifted clock rising edge arrives, return state 4.See that accompanying drawing 4:Disturb_clk_mux_4 module is to through dephased four tunnel clock signal clk_out1, clk_out2, clk_out3, clk_out4 carries out timesharing selection, specific works flow process is as follows: enter state 0 after system reset, detection disturb_en_edge signal enters state 1 time effective simultaneously, carries out CNT counting simultaneously, reaches entrance state 2 after predetermined value；Continue CNT counting, reach second predetermined value and enter state 3；Continuing counting, reach entrance state 4 after last predetermined value, this Count of Status returns state 0 after 255, and CNT is reset.Use status signal as the chip selection signal of a MUX simultaneously, select the clock signal of out of phase to export as clk_sample_out.So, as long as NUM, the CNT in Dcm_control_gen and Disturb_clk_mux_4 module is selected suitable value, just according to designing requirement, sampling clock can be shifted accurately, thus what realize sampling clock disturbs phase process.

Adopting IDE in design is ISE8.2, completes to utilize ModelSimSE6.3d that module is carried out Post-RouteSimulation simulation result as shown in Figure 5 after placement-and-routing until software.Wherein module master clock clk_main_control frequency is 50MHz,；Disturb_en_edge is the input signal cable controlling the phase shift beginning and ending time；Lock_ready is systematic reset signal；Clk_sample_in is input ADC sample clock frequency 100MHz；Clk_sample_out is the output DAC sampling clock through phase shift, it is seen that the phase contrast between this moment input and output clock is more than 270 degree.The resource situation that this module takies is as follows: Silices59, bondedIOBs5, DCM_ADVs1, GCLKs4 bar.

Accompanying drawing 6, accompanying drawing 7 are that in the side circuit utilizing fluorescence oscillograph to record, the actual effect figure of trigger phase difference between ADC sample sequence original position and trigger point is disturbed after phase module in non-scrambling phase module and interpolation, the wherein sine wave of ADC sampling clock f=125MHz, incoming frequency 230MHz.In figure, yellow dash area is the distribution of trigger phase difference, adds after disturbing phase module, and the distribution of phase contrast more uniformly (is uniformly distributed in the scope of 0-T), so that stochastical sampling waveform reconstruction is rapider.

The random equivalent method of sampling is to widen the ADC sample frequency effective means to tens of GHz in ultra-high-speed data acquisition process system, digital storage oscilloscope, wide-band frequency spectrum analyser.The multiple differed between equivalent sampling rate with ADC real-time sampling rate is more big, and required phase-triggered difference is distinguished more fine, under high-frequency signal, needs the long period can form complete waveform.The stochastical sampling realized in the present invention is utilized to disturb phase module, it is possible to effectively to realize this process, system waveform turnover rate can be significantly improved.

Claims (2)

1. a digital fluorescence oscilloscope stochastical sampling disturbs circuitry phase method for designing, it is characterised in that comprise the steps:

(1) adopt measured signal as trigger source, when signal level is increased beyond rising edge triggering level or signal level descends below trailing edge triggering level, trigger circuit and produce a triggering pulse, this pulse activation data acquisition circuit, and once sample under sampling clock effect, thus obtaining the value in signal a certain moment, by measuring the phase contrast of each ADC sample sequence starting point and signal trigger instants, just can determine that this sample sequence position in signal waveform；

(2) owing to sampling clock and signal are independent from, this phase contrast will be a random value, sampled value and this phase difference value are stored simultaneously, arrange according to phase difference value size order, when stacking fold is sufficiently large, the waveform sampling process of all measured signals will be spread all over, thus reconstructing the complete sample waveform of echo signal.

2. digital fluorescence oscilloscope stochastical sampling according to claim 1 disturbs circuitry phase method for designing, it is characterised in that ADC sample sequence and the phase contrast triggering original position are a random value, and minimum is 0, is a sampling period T to the maximum.