CN104535918B - A kind of cross clock domain lock unit internal constant test circuit and method - Google Patents

Abstract

A circuit and method for testing internal constants of a cross-clock domain synchronizer. The test circuit includes: an asynchronous data unit, a unit to be detected, a first metastable state counting unit, a second metastable state counting unit, a mode selection unit and a timing unit. The invention discloses a test circuit and method for the internal constant of the synchronizer used when evaluating the MTBF of the cross-clock domain synchronizer. It includes the design and implementation of the internal constant test circuit of the synchronizer, test operation and data calculation. The invention solves the problem that it is difficult to accurately obtain the internal constant of the synchronizer when evaluating the MTBF of the cross-clock domain synchronizer, and can be applied to a synchronizer composed of registers with different process parameters of the master-slave latch, and improves the test of the internal constant of the synchronizer reliability of the results.

Description

A circuit and method for testing internal constants of a cross-clock domain synchronizer

technical field

The invention belongs to the field of electronic technology, in particular to a circuit and method for testing internal constants of a cross-clock domain synchronizer.

Background technique

With the increase of electronic hardware design scale and the appearance of System On Chip (SOC, System On Chip), cross-clock domain The number of signal circuits also increases accordingly, resulting in an increase in the probability of metastability caused by crossing clock domains in the circuit. Therefore, a synchronous circuit composed of two registers cascaded or more registers cascaded is widely used, as shown in Figure 1, this paper calls this circuit a synchronizer. However, the continuous progress of FPGA and ASIC technology has a negative impact on the solution of the metastable state, which greatly deteriorates the performance of the existing synchronizer. The increase of cross-clock domain signals in the same design and the reduction of the efficiency of the devices used to solve the metastable state will reduce the overall reliability of the FPGA circuit and increase the risk of design failure. Therefore, it is particularly important to evaluate whether the synchronizer used in the FPGA can meet the reliability requirements of the design.

Currently the main formula used Perform synchronizer reliability evaluation (where F _d is the data conversion frequency of the input synchronizer, F _c is the clock frequency of the receiving clock domain, T is the clock cycle of the receiving clock domain, i+1 is the number of registers in the synchronizer, C ₁ and C ₂ are internal constants of the synchronizer: C ₁ is a window constant, and C ₂ is a time constant). The synchronizer composed of two-level registers uses Evaluate (where C _2M is the time constant of the master latch of the register in the synchronizer, C _2S is the time constant of the slave latch of the register in the synchronizer, and λ is the duty cycle of the destination clock domain clock). It can be seen from the above formula that in order to evaluate the mean time between failure (MTBF) of the synchronizer, in addition to the four external influencing parameters known from the specific application, F _d , F _c , T, λ, it is also necessary to measure C ₁ , C ₂ Two internal constants related to the device. Currently, the test circuit shown in Figure 2 can be used to obtain internal constants C ₁ and C ₂ , where CLK1 is the clock signal in the first clock domain, CLK2 is the clock signal in the second clock domain, and the register to be tested is Register B; the output of register B to be tested is sampled by register C and register D after a full cycle and a half cycle of CLK2, respectively. Metastable states are detected when the sampled values of the two registers are different. Since unit B to be tested is sampled by register D after half a CLK2 clock period, only the main latch of register B to be tested performs metastable recovery during the high level of the clock, so this circuit can only measure the register The time constant C _2M of the master latch cannot measure the complete time constant C ₂ of the register. According to the formula When C _2M and C _2s in the register are equal, the value of time constant C ₂ can be replaced by the value of C _2M measured. If the process parameters of the master latch and the slave latch of this register are different, replacing C ₂ with the value of C _2M will lead to inaccurate test results of the internal constant of the synchronizer, thereby affecting the accuracy of the synchronizer MTBF evaluation.

Contents of the invention

In order to solve the above problems, the object of the present invention is to provide a circuit and method for testing internal constants of a cross-clock domain synchronizer.

In order to achieve the above object, the cross-clock domain synchronizer internal constant test circuit and method provided by the present invention include: an asynchronous data unit, a unit to be detected, a first metastable counting unit, a second metastable counting unit, a mode selection unit and Timing unit; wherein: the asynchronous data unit is connected to the unit to be detected, the unit to be detected is respectively connected to the first metastable counting unit and the second metastable counting unit, the first metastable counting unit is connected to the mode selection unit, The second metastable counting unit is connected with the mode selection unit, and the mode selection unit is connected with the timing unit; the asynchronous data unit is connected with the first clock input signal CLK1; the mode selection unit is respectively connected with the mode selection signal SEL and the second clock input signal CLK2_M1 is connected to the third clock input signal CLK2_M2.

The first clock input signal CLK1 and the second clock input signal CLK2_M1 are asynchronous clocks from two different sources, and the first clock input signal CLK1 and the third clock input signal CLK2_M2 are also asynchronous clocks from two different sources. The clock input signal CLK2_M1 and the third clock input signal CLK2_M2 do not exist at the same time; the second clock input signal CLK2_M1 is a clock with a slower frequency; the third clock input signal CLK2_M2 is a clock with a faster frequency, and the clock period of the third clock input signal CLK2_M2 is set as the first Half of the second clock input signal CLK2_M1.

The asynchronous data unit 1 includes a first register and a first inverter, and the output port of the first register returns to the input port of the first register through the first inverter.

The mode selection unit mainly includes a first multiplexer and a second multiplexer.

The first metastable counting unit includes a second register and a third register, a first configurable phase delay module, a first exclusive OR gate, a sixth register and a first metastable counter.

The second metastable counting unit includes a fourth register, a fifth register, a second configurable phase delay module, a second exclusive OR gate, a seventh register and a second metastable counter.

The method for testing internal constants of cross-clock domain synchronizers provided by the present invention includes the following steps executed in sequence:

Step 1) S1 stage of generating an asynchronous signal: the asynchronous data unit generates a digital signal in the first clock domain that is asynchronous with the second clock domain, that is, the output signal of the output terminal Q of the first register;

Step 2) Select the S2 stage of the first mode: select mode one by the mode selection signal SEL of the mode selection unit, and carry out the main latch time constant test for the main latch of the unit to be detected, and now the first metastable counting unit works It is valid, and the second clock domain clock signal is selected as the second clock input signal CLK2_M1 with a slower clock frequency;

Step 3) Stage S3 of configuring the initial value of the first delay time: setting the initial value of the delay time of the first configurable phase delay module in the first metastable counting unit, that is, using the main latch of the unit to be detected initial value of the solution time t for metastable processing;

Step 4) The first metastable counting unit counts to the S4 stage of the expected sampling number N1: the first metastable counting unit counts the metastable state, and when the first metastable counter reaches the expected sampling number N1, the third The counter stops working;

Step 5) record the current delay time and the S5 stage of the value in the timing unit: record the value of the third counter and the delay time value of the corresponding first configurable phase delay module (Y1);

Step 6) S6 stage of judging whether the number of tests reaches the expected number of samples N2: whether the times of judging the main latch time constant test reaches the expected number of samples N2 times, that is, whether the current sampling reaches the expected number of samples N2; if the judgment result is "Yes ", then enter the next step S8 stage, otherwise the next step enters the S7 stage;

Step 7) S7 stage of configuring the new value of the first delay time: reset the delay time value of the first configurable phase delay module in the first metastable counting unit, and then re-enter the S4 stage in the next step to continue the next cycle test ;

Step 8) process the test data, obtain the time constant C of the master _latch S8 stage: process the test data, pass the value of the expected sampling times N2 timing units of the record and the corresponding first configurable phase delay module delay Time, measure and calculate the time constant C _2M of the main latch for the register to be tested in the unit to be tested;

Step 9) select the S9 stage of mode two: select mode two by the mode selection signal SEL of mode selection unit, carry out to-be-detected unit from latch time constant and synchronizer window constant test, now the second metastable counting unit work It is valid, and the second clock domain clock signal is selected as the third clock input signal CLK2_M2 with a faster clock frequency;

Step 10) S10 stage of configuring the second delay time initial value: setting the initial value of the delay time of the second configurable phase delay module in the second metastable state counting unit, that is, using the unit to be detected to carry out from the latch initial value of the solution time t for metastable processing;

Step 11) The second metastable counting unit counts to the S11 stage of the expected sampling number N1: the second metastable counting unit counts the metastable state, and when the second metastable counter reaches the expected sampling number N1, the first Three counters stop working;

Step 12) S12 stage of recording the current delay time and the value in the timing unit: record the value of the third counter and the delay time value of the corresponding second configurable phase delay module;

Step 13) S13 stage of judging whether the number of tests reaches the expected number of sampling times N2: judging whether the number of times of the slave latch time constant test reaches the expected number of sampling times N2 times, if the judgment result is "yes", then enter the next step S15 stage, otherwise The next step is to enter the S14 stage;

Step 14) Stage S14 of configuring the new value of the second delay time: reset the delay time value of the second configurable phase delay module in the second metastable counting unit, and then re-enter the S11 stage in the next step to continue the next cycle test ;

Step 15) process the test data, obtain the synchronizer internal constant C ₁ , the S15 stage of C ₂ : process the test data, pass the value of the expected sampling times N2 timing units recorded and the corresponding second configurable phase delay module delay The internal constants C ₂ and C ₁ are measured and calculated for the register to be tested in the synchronizer; this process ends here.

In the S8 stage, the calculation method of the time constant C _2M of the master latch is as follows: According to the formula Among them, t is the solution time of the main latch, that is, the value of the first configurable phase delay module Y1, taking the natural logarithm on both sides of the above formula at the same time, then it can be obtained The MTBF at this time can be calculated by multiplying the value of the third counter by the clock period of the second clock input signal CLK2_M1 divided by the expected sampling number N1 value of the first metastable counter; the delay time of the first configurable phase delay module t is the horizontal axis, ln(MTBF) is the vertical axis, and N2 points are determined on the coordinate axis; a straight line is drawn with N2 sampling points, and the reciprocal of the slope k1 obtained is C _2M .

In the S15 stage, the calculation method of the internal constants C ₁ and C ₂ of the synchronizer is as follows: according to Where t is the resolution time from the latch, that is, the value of the second configurable phase delay module, and λT is the high-level time of the third clock input signal CLK2_M2 of the destination clock domain clock. Taking the natural logarithm on both sides of the above formula at the same time, it can be get where C _2M can be calculated by step 8), so lnF _d and lnF _c are known; the MTBF at this time can be calculated by multiplying the value of the third counter by the clock period of the third clock input signal CLK2_M2 divided by the expected sampling number N1 value of the second metastable counter; 2. The delay time t of the configurable phase delay module is the horizontal axis, ln(MTBF) is the vertical axis, determine N2 points, draw a straight line with N2 sampling points, and the reciprocal k2 of the obtained slope is the time constant of the slave latch C _2S ; and the intersection point value Yc of the drawn line and the y-axis can be obtained, then the window constant C ₁ can be obtained by Calculated, the time constant _C2 can be given by figured out.

The invention discloses a test circuit and method for the internal constant of the synchronizer used when evaluating the MTBF of the cross-clock domain synchronizer. It includes the design and implementation of the internal constant test circuit of the synchronizer, test operation and data calculation. The invention solves the problem that it is difficult to accurately obtain the internal constant of the synchronizer when evaluating the MTBF of the cross-clock domain synchronizer, and can be applied to a synchronizer composed of registers with different process parameters of the master-slave latch, and improves the test of the internal constant of the synchronizer The accuracy and applicability of the results.

Description of drawings

FIG. 1 is a circuit schematic diagram of a cross-clock domain synchronizer in the prior art.

FIG. 2 is a schematic diagram of an internal constant test circuit of a cross-clock domain synchronizer in the prior art.

FIG. 3 is a block diagram of an internal constant test circuit of a cross-clock domain synchronizer provided by the present invention.

FIG. 4 is a schematic diagram of an internal constant test circuit of a cross-clock domain synchronizer provided by the present invention.

FIG. 5 is a flowchart of a method for testing internal constants of a cross-clock domain synchronizer provided by the present invention.

detailed description

The circuit and method for testing the internal constant of a cross-clock domain synchronizer provided by the present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments.

As shown in Figure 3, the internal constant test circuit of the cross-clock domain synchronizer provided by the present invention includes: an asynchronous data unit 1, a unit to be detected 2, a first metastable counting unit 3, a second metastable counting unit 4, a mode Selection unit 5 and timing unit 6; wherein: the asynchronous data unit 1 is connected with the unit 2 to be detected, and the unit 2 to be detected is connected with the first metastable counting unit 3 and the second metastable counting unit 4 respectively, and the first substable The stable counting unit 3 is connected with the mode selection unit 5, the second metastable counting unit 4 is connected with the mode selection unit 5, and the mode selection unit 5 is connected with the timing unit 6; the asynchronous data unit 1 is connected with the first clock input signal CLK1 Connection; the mode selection unit 5 is connected to the mode selection signal SEL and the second clock input signal CLK2_M1 and the third clock input signal CLK2_M2 respectively.

The asynchronous data unit 1 belongs to the first clock domain; the mode selection unit 5 is a combinational logic and does not need to be driven by a clock; the unit to be detected 2, the first metastable counting unit 3, the second metastable counting unit 4 and the timing unit 6 belong to The second clock domain; the mode selection unit 5 selects a clock device for units in the second clock domain, and selects the output of the first metastable counting unit 3 or the output of the second metastable counting unit 4 to be connected to the timing unit 6 .

As shown in Figure 4, the first clock input signal CLK1 and the second clock input signal CLK2_M1 are asynchronous clocks from two different sources, and the first clock input signal CLK1 and the third clock input signal CLK2_M2 are also asynchronous clocks from two different sources. , the second clock input signal CLK2_M1 and the third clock input signal CLK2_M2 do not exist at the same time; in the case of testing the master latch in mode one, the second clock input signal CLK2_M1 with a slower clock frequency is selected as the input clock; in order to improve metastability In the case of testing the slave latch in mode 2, the third clock input signal CLK2_M2 with a faster clock frequency is selected as the input clock, and the clock period of the third clock input signal CLK2_M2 can be set to be that of the second clock input signal CLK2_M1 half.

The asynchronous data unit 1 includes a first register A1 and a first inverter M1, the output port of the first register A1 returns to the input port of the first register A1 through the first inverter M1; it is used to generate the first clock The data signal of the field, that is, the output signal of the output terminal Q of the first register A1.

The mode selection unit 5 mainly includes a first multiplexer X1 and a second multiplexer X2, which are used to determine the selection between the master latch test mode and the slave latch test mode according to the mode selection signal SEL; The first multiplexer X1 selects the second clock input signal CLK2_M1 or the third clock input signal CLK2_M2 as the input clock CLK2 of the second clock domain; the second multiplexer X2 selects the first metastable counter J1 or the second substable counter J1 The output signal of the steady-state counter J2 when it reaches the expected sampling number N1 serves as an enabling signal for the third counter J3 to stop counting.

The unit 2 to be tested is the register B to be tested.

The first metastable counting unit 3 includes a second register A2 and a third register A3, a first configurable phase delay module Y1, a first XOR gate M3, a sixth register A6 and a first metastable counter J1 ; This unit works effectively in mode 1, and uses the main latch of the register B to be tested to carry out statistics on the number of metastable states after the delay time recovery of the first configurable phase delay module Y1; the output signal of the unit 2 to be detected is in the second The inverse clock of the original clock in the clock domain and the original clock delay in the second clock domain The rising edge of the first configurable phase delay module Y1 clock is sampled through the third register A3 and the second register A2 respectively, and the output result is passed through the first After the exclusive OR logic of the exclusive OR gate M3, it is input to the sixth register A6 triggered by the rising edge of the first configurable phase delay module Y1 clock delayed by the original clock of the second clock domain, and then the first metastable counter J1 performs substable steady state count.

The second metastable counting unit 4 includes a fourth register A4, a fifth register A5, a second configurable phase delay module Y2, a second XOR gate M4, a seventh register A7 and a second metastable counter J2 ; This unit works effectively in mode 2, and uses half of the third clock input signal CLK2_M2 clock cycle to solve the time recovery of the master latch of the register B to be tested and its second configurable phase delay module Y2 delay time from the latch After recovery, the number of metastable states is counted; the output signal of the unit 2 to be detected is delayed by the original clock of the second clock domain and the reverse clock of the original clock of the second clock domain. The rising edge of the second configurable phase delay module Y2 clock respectively Sampling is carried out through the fifth register A5 and the fourth register A4, and the output result is input to the clock rising edge triggered by the reverse clock delay of the original clock of the second clock domain and the second configurable phase delay module Y2 after passing through the exclusive OR logic After the seventh register A7, the metastable counting is performed by the second metastable counter J2.

Timing unit 6 includes a third counter J3, which clocks the time required for sampling to the expected sampling number N1 metastable states in mode one and mode two respectively; The third counter J3 performs an addition operation, and when the value of the metastable counter in the metastable counting unit in the corresponding mode reaches the expected sampling number N1, the generated enable signal to stop counting causes the third counter J3 to stop counting, And keep the original value unchanged until the next test.

In the first metastable state counting unit 3, the first metastable state counter J1 counts the number of metastable states generated in the first mode, and when the metastable state reaches the expected sampling number N1, the first metastable state counter J1 stops work, the generated enable signal to stop counting will make the third counter J3 stop working through the mode selection unit 5 .

In the second metastable state counting unit 4, the second metastable state counter J2 counts the number of metastable states generated under the mode two, and when the metastable state reaches the expected sampling number N1, the second metastable state counter J2 To stop working, the generated enabling signal for stopping counting will cause the third counter J3 to stop working through the mode selection unit 5 .

As shown in Figure 5, the method for testing the internal constants of the cross-clock domain synchronizer provided by the present invention using the above-mentioned internal constant test circuit of the cross-clock domain synchronizer includes the following steps executed in order:

Step 1) S1 stage of generating asynchronous signal: the asynchronous data unit 1 generates a digital signal in the first clock domain asynchronous to the second clock domain, that is, the output signal of the output terminal Q of the first register A1;

Step 2) select the S2 stage of the first mode: select mode one by the mode selection signal SEL of the mode selection unit 5, and carry out the main latch time constant test for the main latch of the detection unit 2, and now the first metastable state counts Unit 3 works effectively, and selects the second clock domain clock signal as the second clock input signal CLK2_M1 with a slower clock frequency;

Step 3) Stage S3 of configuring the initial value of the first delay time: set the initial value of the delay time of the first configurable phase delay module Y1 in the first metastable counting unit 3, which is to use the main lock of the unit 2 to be detected The initial value of the resolution time t of the metastable state processing of the memory;

Step 4) The first metastable state counting unit counts to the S4 stage of the expected sampling number N1: the first metastable state counting unit 3 counts the metastable state, and when the first metastable state counter J1 reaches the expected sampling number N1, The third counter J3 stops working;

Step 5) S5 stage of recording the current delay time and the value in the timing unit: record the value of the third counter J3 and the corresponding delay time value of the first configurable phase delay module Y1;

Step 6) S6 stage of judging whether the number of tests reaches the expected number of samples N2: whether the times of judging the main latch time constant test reaches the expected number of samples N2 times, that is, whether the current sampling reaches the expected number of samples N2; if the judgment result is "Yes ", then enter the next step S8 stage, otherwise the next step enters the S7 stage;

Step 7) The S7 stage of configuring the new value of the first delay time: reset the delay time value of the first configurable phase delay module Y1 in the first metastable state counting unit 3, the next step re-enters the S4 stage, and continues to the next step cycle test;

Step 8) process the test data, obtain the time constant C of the master _latch S8 stage: process the test data, pass the value of the expected sampling times N2 timing units 6 of the record and the corresponding first configurable phase delay module Y1 delay time, the measurement and calculation of the time constant C _2M of the main latch is carried out for the register B to be tested in the unit 2 to be tested;

Step 9) select the S9 stage of mode two: select mode two by the mode selection signal SEL of mode selection unit 5, carry out to-be-detected unit 2 from latch time constant and synchronizer window constant test, now the second metastable count Unit 4 works effectively, and selects the second clock domain clock signal as the third clock input signal CLK2_M2 with a faster clock frequency;

Step 10) S10 stage of configuring the second delay time initial value: setting the initial value of the delay time of the second configurable phase delay module Y2 in the second metastable state counting unit 4, which is to use the unit to be detected 2 from the lock The initial value of the resolution time t of the metastable state processing of the memory;

Step 11) The second metastable state counting unit counts to the S11 stage of the expected sampling number N1: the second metastable state counting unit 4 counts the metastable state, and when the second metastable state counter J2 reaches the expected sampling number N1, Make the third counter J3 stop working;

Step 12) S12 stage of recording the current delay time and the value in the timing unit: record the value of the third counter J3 and the delay time value of the corresponding second configurable phase delay module Y2;

Step 13) S13 stage of judging whether the number of tests reaches the expected number of sampling times N2: judging whether the number of times of the slave latch time constant test reaches the expected number of sampling times N2 times, if the judgment result is "yes", then enter the next step S15 stage, otherwise The next step is to enter the S14 stage;

Step 14) S14 stage of configuring the new value of the second delay time: reset the delay time value of the second configurable phase delay module Y2 in the second metastable state counting unit 4, the next step re-enters the S11 stage, and continues to the next step cycle test;

Step 15) process the test data to obtain the internal constant _C1 of the synchronizer, the S15 stage of _C2 : process the test data, pass the value of the expected sampling times N2 timing units 6 recorded and the corresponding second configurable phase delay module The Y2 delay time is used to measure and calculate the internal constants C ₂ and C ₁ of the register B to be tested in the synchronizer; this process ends here.

In the S7 stage and the S14 stage, the specific method of resetting the delay time value is based on the principle of increasing successively, and the final delay time should not exceed half a cycle of the second clock domain clock.

The first configurable phase delay module Y1 in the first metastable counting unit 3 is used to implement configurable different delays for the clock signal in the second clock domain, and the first metastable phase delay module in the second metastable counting unit 4 The second configurable phase delay module Y2 is used to implement configurable different delays for the clock signal with the reverse phase of the second clock domain; in the actual test, the loop test method is adopted; in each test, the delay time is gradually increased, But the final delay time should not exceed half cycle of the second clock domain clock.

In the S8 stage, the calculation method of the time constant C _2M of the master latch is as follows: According to the formula (t is the solution time of the master latch, that is, the value of the first configurable phase delay module Y1), taking the natural logarithm on both sides of the above formula at the same time, it can be obtained The MTBF at this time can be calculated by multiplying the value of the third counter J3 by the clock period of the second clock input signal CLK2_M1 divided by the expected sampling number N1 value of the first metastable counter J1; the first configurable phase delay module Y1 The delay time t is the horizontal axis, ln(MTBF) is the vertical axis, and N2 points are determined on the coordinate axis; a straight line is drawn with N2 sampling points, and the reciprocal of the slope k1 obtained is C _2M .

In the S15 stage, the calculation method of the internal constants C ₁ and C ₂ of the synchronizer is as follows: according to (t is the resolution time of the slave latch, that is, the value of the second configurable phase delay module Y2, and λT is the high-level time of the third clock input signal CLK2_M2 of the destination clock domain clock), taking the natural logarithm on both sides of the above formula at the same time, then you can get where C _2M can be calculated by step 8), so lnF _d and lnF _c are known; the MTBF at this time can be calculated by multiplying the value of the third counter J3 by the clock period of the third clock input signal CLK2_M2 divided by the expected sampling number N1 value of the second metastable counter J2; Take the delay time t of the second configurable phase delay module Y2 as the horizontal axis, ln(MTBF) as the vertical axis, determine N2 points, draw a straight line with N2 sampling points, and the reciprocal k2 of the obtained slope is the slave latch The time constant C _2S of ; and the intersection point value Yc of the drawn line and the y-axis can be obtained, then the window constant C ₁ can be obtained by Calculated, the time constant _C2 can be given by calculate;

In order to ensure the accuracy and validity of the test data, the test can be carried out at different positions of the same device, and the average value of the internal constants C ₁ and C ₂ of the synchronizer at different test positions can be used for MTBF calculation.

The internal constant test circuit and method of the cross-clock domain synchronizer provided by the present invention solve the problem that the internal constant of the synchronizer required for MTBF calculation is difficult to be fully and accurately measured when the process parameters of the master latch and the slave latch of the register in the synchronizer are different. ; Provide a general synchronizer internal constant test circuit and test method, which can accurately measure and calculate the synchronizer internal constant.

Claims (9)

1. a kind of cross clock domain lock unit internal constant test circuit, it is characterised in that：Which includes：Asynchronous data unit (1), treat Detector unit (2), the first metastable state counting unit (3), the second metastable state counting unit (4), mode selecting unit (5) and timing Unit (6)；Wherein：Asynchronous data unit (1) is connected with unit to be detected (2), unit (2) to be detected respectively with the first metastable state Counting unit (3) is connected with the second metastable state counting unit (4), the first metastable state counting unit (3) and mode selecting unit (5) connect, the second metastable state counting unit (4) is connected with mode selecting unit (5), mode selecting unit (5) and timing unit (6) it is connected；Asynchronous data unit (1) is connected with the first clock input signal CLK1；Mode selecting unit (5) respectively with mould Formula selection signal SEL and second clock input signal CLK2_M1 and the 3rd clock input signal CLK2_M2 are connected.

2. cross clock domain lock unit internal constant test circuit according to claim 1, it is characterised in that：Described first Clock input signal CLK1 and second clock input signal CLK2_M1 are two not homologous asynchronous clocks, and the first clock is input into Signal CLK1 and the 3rd clock input signal CLK2_M2 are also two not homologous asynchronous clocks, second clock input signal Exist when CLK2_M1 and the 3rd clock input signal CLK2_M2 is different；Second clock input signal CLK2_M1 is that frequency is slower Clock；3rd clock input signal CLK2_M2 is the very fast clock of frequency, arranges the 3rd clock input signal CLK2_M2 clocks week Half of the phase for second clock input signal CLK2_M1.

3. cross clock domain lock unit internal constant test circuit according to claim 1, it is characterised in that：Described is asynchronous Data cell (1) includes the first depositor (A1) and the first phase inverter (M1), and the output port of the first depositor (A1) passes through the One phase inverter (M1) returns to the input port of the first depositor (A1).

4. cross clock domain lock unit internal constant test circuit according to claim 1, it is characterised in that：Described pattern Select unit (5) mainly includes the first MUX (X1) and the second MUX (X2).

5. cross clock domain lock unit internal constant test circuit according to claim 1, it is characterised in that：Described first Metastable state counting unit (3) includes the second depositor (A2) and the 3rd depositor (A3), the first configurable phase delay module (Y1), the first XOR gate (M3), the 6th depositor (A6) and the first metastable state enumerator (J1).

6. cross clock domain lock unit internal constant test circuit according to claim 1, it is characterised in that：Described second Metastable state counting unit (4) includes the 4th depositor (A4), the 5th depositor (A5), the second configurable phase delay module (Y2), the second XOR gate (M4), the 7th depositor (A7) and the second metastable state enumerator (J2).

7. the cross clock domain synchronization that the cross clock domain lock unit internal constant test circuit described in a kind of utilization claim 1 is carried out Device internal constant method of testing, it is characterised in that：Described method includes the following steps for executing in order：

Step 1) generate asynchronous signal the S1 stages：When generating first asynchronous with second clock domain by asynchronous data unit (1) Clock domain digital signal, the i.e. output signal of the outfan Q of the first depositor (A1)；

Step 2) select first mode the S2 stages：Pattern is selected by the mode select signal SEL of mode selecting unit (5) One, treating detector unit (2) main latch carries out main latch time constant test, now the first metastable state counting unit (3) Work effectively, and selects second clock domain clock signal for slower second clock input signal CLK2_M1 of clock frequency；

Step 3) configuration first time delay initial value the S3 stages：First set in the first metastable state counting unit (3) can The initial value of the time delay of configuration phase Postponement module (Y1), is as carried out using unit to be detected (2) main latch metastable The initial value of the solution time t of state process；

Step 4) the first metastable state counting unit counts to expected number of samples N1 the S4 stages：First metastable state counting unit (3) metastable state is counted, when the first metastable state enumerator J1 reaches expected number of samples N1, the 3rd enumerator (J3) stops Only work；

Step 5) record current delay times and timing unit in numerical value the S5 stages：Record the 3rd enumerator (J3) numerical value and The delay time value of the corresponding first configurable phase delay module (Y1)；

Step 6) judge whether testing time reaches the S6 stages of expected sampling number N2：Judge that main latch time constant is tested Number of times whether reach expected sampling number N2 time, i.e. whether present sample reaches expected sampling number N2；If it is judged that For "Yes", then the next step S8 stage is entered, otherwise next step enters the S7 stages；

Step 7) configuration the first time delay new value the S7 stages：Reset first in the first metastable state counting unit (3) The delay time value of configurable phase delay module (Y1), next step reenter the S4 stages, continue subsequent cycle test；

Step 8) process test data, obtain time constant C of main latch_2MThe S8 stages：Test data is processed, is led to The value of N2 timing unit of the expected sampling number (6) of overwriting and corresponding first configurable phase delay module (Y1) postpone Time, treating the depositor to be measured (B) in test cell (2) carries out time constant C of main latch_2MSurvey calculation；

Step 9) select pattern two the S9 stages：Pattern two is selected by the mode select signal SEL of mode selecting unit (5), Carry out unit to be detected (2) to test from latch time constant and lock unit window constant, now the second metastable state counting unit (4) work effectively, and second clock domain clock signal is selected for clock frequency the 3rd clock input signal CLK2_ faster M2；

Step 10) configuration second time delay initial value the S10 stages：Set second in the second metastable state counting unit (4) The initial value of the time delay of configurable phase delay module (Y2), as carries out Asia using unit to be detected (2) from latch The initial value of the solution time t of steady state process；

Step 11) the second metastable state counting unit counts to expected number of samples N1 the S11 stages：Second metastable state counting unit (4) metastable state is counted, when the second metastable state enumerator (J2) reaches expected number of samples N1, makes the 3rd enumerator (J3) quit work；

Step 12) record current delay times and timing unit in numerical value the S12 stages：Record the numerical value of the 3rd enumerator (J3) And corresponding second configurable phase delay module (Y2) delay time value；

Step 13) judge whether testing time reaches the S13 stages of expected sampling number N2：Judge to survey from latch time constant Whether the number of times of examination reaches expected sampling number N2 time, if it is judged that being "Yes", then enters the next step S15 stage, otherwise Next step enters the S14 stages；

Step 14) configuration the second time delay new value the S14 stages：Reset in the second metastable state counting unit (4) The delay time value of two configurable phase delay modules (Y2), next step reenter the S11 stages, continue subsequent cycle test；

Step 15) process test data, obtain lock unit internal constant C₁, C₂The S15 stages：Test data is processed, is led to The value of N2 timing unit of the expected sampling number (6) of overwriting and corresponding second configurable phase delay module (Y2) postpone Time to lock unit in depositor to be measured (B) carry out internal constant C₂And C₁Survey calculation；This flow process so far terminates.

8. cross clock domain lock unit internal constant method of testing according to claim 7, it is characterised in that：In the S8 stages In, time constant C of described main latch_2MComputational methods as follows：According to formula Wherein t is the value that main latch solves the configurable phase delay module Y1 of time, i.e., first, and above-mentioned formula both sides are taken from simultaneously So logarithm, then be obtainedMTBF now can pass through the 3rd enumerator (J3) Value is multiplied by expected number of samples N1 value of the second clock input signal CLK2_M1 clock cycle divided by the first metastable state enumerator J1 Calculate；With the first configurable phase delay module (Y1) time delay t as transverse axis, ln (MTBF) is the longitudinal axis, in coordinate N2 point is determined on axle；With N2 sampling point-rendering straight line, the inverse of the slope k 1 for obtaining is C_2M.

9. cross clock domain lock unit internal constant method of testing according to claim 7, it is characterised in that：In the S15 stages In, described lock unit internal constant C₁, C₂Computational methods as follows：According to Wherein t is to solve the value that time, i.e., second can configure phase delay module (Y2), λ from latch_TFor purpose clock zone clock Above-mentioned formula both sides are taken natural logrithm, are then obtained by three clock input signal CLK2_M2 high level times simultaneouslyWherein C_2MCan be by step 8) calculate, thereforelnF_d, lnF_cFor known；MTBF now can be multiplied by the 3rd clock input signal by the value of the 3rd enumerator (J3) The CLK2_M2 clock cycle is calculated divided by the expected number of samples N1 value of the second metastable state enumerator (J2)；Can match somebody with somebody with second Phase delay module (Y2) t time delay is put for transverse axis, ln (MTBF) is the longitudinal axis, determines N2 point, paints with N2 sampled point Straight line processed, the k2 reciprocal of the slope for obtaining are time constant C from latch_2S；And the friendship that can obtain drawing straight line and y-axis Point value Yc, then window constant C₁Can be byCalculate, time constant C₂Can ByCalculate.