CN102621383B - Method and system for measuring nanosecond ultra-narrow pulse - Google Patents
Method and system for measuring nanosecond ultra-narrow pulse Download PDFInfo
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Abstract
The invention provides a method and system for measuring nanosecond ultra-narrow pulse, which relates to the field of signal detection. The system mainly comprises a high-speed pulse measuring module, a field programmable gate array (FPGA) control module and a human-computer interaction module. According to the size of a programmable time sheet and different measuring modes, a maximum pulse amplitude and the quantity of pulses surpassing a certain set comparison threshold value in each time sheet are detected. The high-speed characteristic of the FPGA is utilized, a software algorithm which has high time consumption is realized by using hardware, the executing efficiency of a program is increased, high-speed processing capability is ensured, and high instantaneity and reliability are achieved.
Description
Technical field
The invention belongs to input field, relate in particular to the super burst pulse measuring method of a kind of novel nanosecond and system.
Background technology
Narrow pulse signal is measured and is had a wide range of applications and demand in fields such as communication, navigation, electronic countermeasure, radars, also needs the relevant information of obtaining narrow pulse signal to realize the effective control to system at aspects such as nuclear reactor decay, effluve detection, noise processed.At present, the research of most burst pulse measuring system all concentrates on pulse signals more than tens to tens nanoseconds, and the research detecting for the burst pulse of several nanosecond is relatively less, and this is also a technical barrier of narrow pulse signal fields of measurement.
The scheme of traditional pulse measure mainly contains following two kinds:
1) AD sampling plan.This scheme is sampled by AD pulse signals, obtains the relevant information such as overall waveform and amplitude of pulse signal, thereby further pulse signals is carried out analyzing and processing.Pulse signal for pulsewidth more than hundreds of nanosecond, this scheme is feasible, can obtain complete sample waveform and the pulse amplitude size of pulse signal by AD, and finally obtains exceeding the pulse number of pulse compare threshold.But for a few nanosecond narrow pulse signal, this mode needs AD to have high sampling rate, the data that sampling obtains also will sharply increase, and it is very difficult that data processing also will become.As adopting the AD device of hypervelocity, price is high.Therefore, adopt the problems such as AD sampling plan measurement nanosecond narrow pulse signal exists cost high, and system complexity is large.
2) peak value keeps scheme.First this scheme adopts peak holding circuit to catch the peak value of pulse signal, and then pulse signals is carried out subsequent treatment.The pulse signal more than hundreds of nanosecond for pulsewidth equally, the pulse number that can be good at detecting the amplitude of pulse signal and exceed pulse compare threshold.For the narrow pulse signal of even several nanoseconds of tens nanoseconds, because pulse width, dutycycle are low, add the interference of outside noise, adopt peak holding circuit to be difficult to accurately catch nanosecond narrow pulse signal, and to testing amount in fact.
In view of above situation, the present invention adopts parallel relatively hypervelocity ECL comparer and the ECL flip-flop array of type to realize seizure and the latch to narrow signal of nanosecond, and in conjunction with correlation module, the maximum amplitude of pulse in setting-up time sheet and the pulse number that exceedes pulse compare threshold is measured.
Summary of the invention
Technical matters to be solved by this invention is: for overcome prior art nanosecond narrow pulse signal measure time sampled data output large, data processing difficulty, and the problem such as pulse capture difficulty, the present invention proposes one nanosecond burst pulse measuring method, high-speed pulse measurement module and FPGA control module are as measurement and the control section of system, check measurement result and initialization system running parameter by human-computer interaction module, and measurement result is preserved with document form.The object of the invention is to set according to trigger pip and timeslice the pulse number that detects pulse maximum amplitude in each timeslice and exceed pulse compare threshold.
The technical scheme that the present invention solves the problems of the technologies described above is the Embedded System Structure adopting based on FPGA, introduce trigger pip by the periodicity of measured pulse signal, and can cut apart carrying out timeslice whole measuring period according to the care of measured signal is estimated, taking timeslice as unit, the maximum amplitude of pulse signal in timeslice and the pulse number that exceedes setting amplitude are measured.System is utilized the hypervelocity feature of ECL device, is used in combination ECL comparator array and ECL flip-flop array pulse signals and catches the high speed performance that ensures system with latch, and realize the high-acruracy survey of burst pulse amplitude in conjunction with pulse height algorithm for estimating.
The present invention proposes the super burst pulse measuring system of a kind of nanosecond, this system comprises high-speed pulse measurement module, FPGA control module, human-computer interaction module, human-computer interaction module is used for checking impulsive measurement result and system operational parameters is set, high-speed pulse measurement module comprises 3 road high-speed A/D converters, resistance pressure-dividing network, hypervelocity emitter-coupled logic ECL comparator array and hypervelocity ECL flip-flop array, wherein two-way high-speed A/D converter DAL_H and DAC_L provide for ECL comparator array, lower limit reference voltage, resistance pressure-dividing network is upper, in lower limit reference voltage range, carry out multistage network dividing potential drop, be respectively ECL comparator array reference comparison voltages is provided, ECL comparator array and ECL d type flip flop array pulse signals catch and latch, maximum amplitude to pulse in setting-up time sheet is measured, another road high-speed A/D converter DAC_T provide pulse compare threshold, measure the reference comparison voltages of comparer as pulse number, thereby the output saltus step that exceedes the pulse enable signal ECL comparer of pulse compare threshold triggers the upset of ECL T trigger, FPGA control module counts to get the umber of pulse in timeslice to the T trigger output signal in Measuring Time sheet.
The present invention also proposes the super burst pulse measuring method of a kind of nanosecond, high-speed pulse measurement module is measured the maximum amplitude of pulse in setting-up time sheet and the pulse number that exceedes pulse compare threshold, the output level generation saltus step of comparer in the time that pulse amplitude exceedes the reference voltage level of comparer, make the set of ECL d type flip flop, ECL d type flip flop output signal is given FPGA after level conversion, then wait for that next timeslice measurement starts, the input pulse amplitude maximal value realizing in each timeslice is measured; In each Measuring Time sheet, in the time that pulse amplitude exceedes the reference voltage of threshold value comparer, comparer output level generation saltus step, thus trigger the upset of ECL T trigger, after level conversion, give FPGA counting by signal output, realize input pulse number and measure.
Pulse height measure portion, FPGA control module to two high-speed A/D converter DAL_H and DAC_L be configured produce high, low two-way reference voltage, obtaining one group of reference voltage by resistance pressure-dividing network inputs as ECL comparator C MP array Yi road respectively, pulse signal is by another road input as CMP array after limiter protection circuit, in the time that Measuring Time sheet starts, ECL d type flip flop DFF array is resetted, when input pulse signal becomes while being greater than reference voltage from being less than reference voltage, there is saltus step and cause trigger set thereafter in corresponding comparer output, in the time that Measuring Time sheet finishes, FPGA reads the output of ECL d type flip flop DFF array, and according to the pulse height maximal value in reference voltage level computation and measurement timeslice, level shifting circuit is Transistor-Transistor Logic level input FPGA by the ECL level conversion of ECL d type flip flop output, step-by-step counting measure portion, in the time that Measuring Time sheet starts, FPGA configurable number weighted-voltage D/A converter DAC_T arranges step-by-step counting compare threshold, step-by-step counting compare threshold, pulse signal input pulse number is measured comparer generation saltus step pulse and is entered ECL T trigger TFF, make T trigger continuous overturning, FPGA counts to get the umber of pulse in timeslice to the T trigger output signal in Measuring Time sheet.
The present invention, by parallel mode relatively, adopts hypervelocity ECL comparer and ECL flip-flop array to realize seizure and the latch to narrow signal of nanosecond, and the maximum amplitude of burst pulse in setting-up time sheet and the pulse number that exceedes pulse threshold value are measured.Utilize the high speed characteristics of FPGA, realize large software algorithm consuming time with hardware, improved the execution efficiency of program, ensured high speed processing ability of the present invention, there is fine real-time and reliability.Cost of the present invention is low, and working stability, reliable is easy to expansion and upgrading, and comprises multiple measurement pattern and interactive mode.Show that through practical application patent of the present invention can effectively detect the maximum amplitude and the pulse number that exceedes pulse compare threshold of narrow pulse signal in each timeslice, for periodic signal more than 50mV or the stronger signal amplitude error range of other regularity, in 5%, temporal resolution reaches as high as 10nS.
Brief description of the drawings
Fig. 1 nanosecond of the present invention super burst pulse measuring system general structure block diagram;
Fig. 2 nanosecond of the present invention super burst pulse measuring system scheme theory diagram.
Embodiment
For accompanying drawing and instantiation, enforcement of the present invention is elaborated below.
Figure 1 shows that nanosecond of the present invention super burst pulse measuring system general structure block diagram, system comprises high-speed pulse measurement module, FPGA control module, and PS/2 keyboard, the human-computer interaction module such as LCDs and Ethernet interface, wherein, high-speed pulse measurement module comprises 3 road high-speed A/D converters (DAC), resistance pressure-dividing network, hypervelocity emitter-coupled logic (ECL) comparator array and hypervelocity ECL flip-flop array, two-way high-speed DAC provides for ECL comparator array, lower limit reference voltage, resistance pressure-dividing network is upper, in lower limit reference voltage range, carry out multistage network dividing potential drop, for each comparer in ECL comparator array provides reference comparison voltages, ECL comparator array and ECL d type flip flop array pulse signals catch and latch, maximum amplitude to pulse in setting-up time sheet is measured, an other road high-speed DAC provides pulse compare threshold, measure the reference comparison voltages of comparer as pulse number, thereby the upset that the pulse signal that exceedes pulse compare threshold can cause the output saltus step of ECL comparer to trigger ECL T trigger realizes the pulse number measurement that exceedes pulse compare threshold, FPGA control module is responsible for the management of system operation control and each peripheral hardware, adopts the mode that embeds Nios II soft-core processor in FPGA, forms the structure that embedded system adds parallel user logic module.The peripheral hardwares such as embedded system management PS/2 keyboard, LCDs, Ethernet interface, and configure DAC control module, impulsive measurement control module is carried out concurrent working by designated mode.Wherein DAC control module arranges the output valve of configuration high-speed DAC according to system triggers cycle and timeslice, and for ECL comparator array upper and lower limit reference voltage is provided, impulsive measurement control module is for impulsive measurement process control; The human-computer interaction modules such as PS/2 keyboard, LCDs and Ethernet interface are used for checking measurement result and system operational parameters are set.
Figure 2 shows that nanosecond of the present invention super burst pulse measuring system theory diagram, be divided into pulse height measure portion and step-by-step counting measure portion according to systemic-function.Pulse height measure portion: FPGA to two high-speed A/D converter (DAC) DAL_H and DAC_L be configured produce high, low two-way reference voltage, then obtain one end input of one group of reference voltage as ECL comparator C MP array by precision resister potential-divider network, after pulse signal input by giving ECL comparator array after limiter protection circuit and each reference voltage compares, in the time that Measuring Time sheet starts, ECL d type flip flop DFF array is resetted, in input signal amplitude change procedure, input signal can cause the comparer output on corresponding road that saltus step occurs to the process that is greater than reference voltage forming rising edge skip signal and cause comparer set thereafter (due to the hypervelocity characteristic of ECL device from being less than reference voltage, the burst pulse of nS level also can be caught by secondary circuit), in the time that Measuring Time sheet finishes, read the result of final ECL d type flip flop array and can calculate pulse height maximal value in Measuring Time sheet in conjunction with the reference voltage level of setting by FPGA, because FPGA is Transistor-Transistor Logic level, and ECL d type flip flop is output as ECL level, therefore increased the level shifting circuit of ECL to TTL.System is also carried out step-by-step counting measurement in the process of ranging pulse amplitude simultaneously, step-by-step counting measure portion: FPGA configurable number weighted-voltage D/A converter DAC_T arranges step-by-step counting compare threshold in the time that Measuring Time sheet starts, input pulse signal produces saltus step pulse by comparer and enters ECL T trigger, due to the continuous overturning characteristic of T trigger, FPGA can be by counting to get the umber of pulse in timeslice to the T trigger output signal after level shifting circuit in Measuring Time sheet.
The concrete timeslice of system is set and is carried out as follows: using in outer triggering signal situation, system starts to be undertaken by the timeslice length of setting the measurement (pulse height completing in very first time sheet is measured and pulse number measurement) of first timeslice after trigger pip arrives, after first timeslice finishes, proceed the measurement of second timeslice, restart the measurement of first timeslice until next trigger pip arrives successively.Do not using in outer triggering signal situation, system produces an internal trigger signal according to the timeslice number of the measuring-signal cycle of setting and the distribution of each signal period, and the time of calculating each timeslice, by above-mentioned use outer triggering signal situation the same manner, timeslice is measured in turn.
Pressing Fig. 1 structure by pulse signal and trigger pip (optional, whether to use outer triggering signal to determine according to default) access measuring system, is illustrating of measuring process below:
1. first system carries out initialization and self-inspection to peripherals such as PS/2 keyboard, LCDs, Ethernet interfaces after powering on;
2. complete after initialization and self-inspection, the configuration data that system reads in Flash storer carries out the setting of every measurement parameter, the timeslice number that parameter comprises whether using outer triggering signal, measuring-signal cycle (optional, to use in the time not using outer triggering signal), each signal period distribute or timeslice length, pulse amplitude are measured the upper limit, pulse amplitude measurement lower limit, step-by-step counting compare threshold, system ip address and measurement pattern etc.After completing setting, system starts to measure according to the parameter of configuration;
3. in measuring process, can reset systematic parameter by PS/2 keyboard and LCDs, the parameter resetting, by storing in the Flash storer of system, to system is configured while again start for next time;
4. system arranges and forms Measuring Time sheet according to parameter.Using in outer triggering signal situation, system starts to be undertaken by the timeslice length of setting the measurement of pulse height and pulse number in first timeslice after trigger pip arrives, after first timeslice finishes, proceed the measurement of the interior pulse height of second timeslice and pulse number, restart the measurement of first timeslice until next trigger pip arrives successively.Do not using in outer triggering signal situation, system produces an internal trigger signal according to the measuring-signal cycle of setting and the timeslice number of dividing of each signal period, and the time of calculating each timeslice, measure in turn by timeslice by above-mentioned the same manner.
5. system is used different modes to carry out the measurement of pulse height according to measurement pattern is different, mainly contains common survey pattern, high-acruracy survey pattern and intelligent measure pattern for different pulse signals and measurement demand.The concrete measuring process of each pattern is as follows:
1) common survey pattern.This pattern is less demanding for measuring accuracy or a kind of measurement pattern of the irregular situation design of pulse signal.This pattern in advance manually the upper and lower reference voltage of allocating and measuring circuit within the zone of reasonableness of pulse amplitude, and the upper and lower reference voltage level of each timeslice keeps respectively setting value constant in a pulse signal cycle, system is according to the maximum direct computation and measurement result of upper and lower reference voltage level that triggers sum of series configuration of the EDL d type flip flop in timeslice.Because relatively progression is limited, measurement result precision is lower, but a recurrence interval of the method can record result, reaction velocity is fast.For the comparator array that adopts N road, as upper and lower reference voltage is set to VH, VL situation, its resolution is
, measuring error is
.
2) high-acruracy survey pattern.This pattern is a kind of high-acruracy survey pattern of taking areal survey mode to realize for periodic signal or the stronger signal of other regularity.This pattern manually the upper and lower reference voltage of pre-configured metering circuit within the zone of reasonableness of pulse amplitude, then by upper and lower reference voltage N decile, (N can be set by the user, N is natural number), distinguish upper and lower reference voltage N time of allocating and measuring circuit by DAC, and the upper and lower reference voltage level at every turn configuring in a rear pulse signal cycle remains unchanged.Getting I is 1 to N, and while measurement for the I time, upper and lower reference voltage settings are respectively:
(1)
(2)
Wherein: the upper limit reference voltage of metering circuit when H_I is the I time measurement, the lower limit reference voltage of metering circuit when L_I is the I time measurement, VH is initial upper limit reference voltage, VL is initial lower limit reference voltage.
In the each timeslice of measurement through a N continuous pulse signal cycle, obtain N measurement data, reject the measurement result of carrying out average treatment after the data of upper and lower limit voltage that exceed setting and obtain last each timeslice to obtaining measurement data, measuring accuracy be approximately described common survey pattern N doubly.
3) intelligent measure pattern.This pattern is a kind of measurement pattern of predicting pulse amplitude values by software algorithm for periodic signal or the stronger Design of Signal of other regularity.Thereby this pattern need to predict that pulse amplitude values arranges upper and lower reference voltage pulse signals amplitude and approaches according to the design of pulse signal feature, thereby realize the automatic, high precision measurement of pulse height.In measuring process, need according to the upper and lower reference voltage of metering circuit in each timeslice of pulse height predicted value dynamic-configuration.As the signal to periodically stronger, first the upper and lower reference voltage of allocating and measuring circuit is the possible maximum range scope of signal manually, obtain in the trigger pip cycle amplitude of narrow pulse signal in each timeslice by one-shot measurement, then in next period measurement, use the measurement result estimated signal amplitude in corresponding timeslice to carry out the configuration of upper and lower reference voltage level, thereby so repeatedly approach contract measurement scope, improve measuring accuracy.
For the narrow pulse signal that ensures system catches performance, the hypervelocity ECL comparator array in circuit and ECL flip-flop array are selected the ECL device of propagation delay in 500pS, ensure the pulse signal of the above width of 2nS to catch and latch.
For ensureing measuring accuracy, must ensure the precision of the one group of ECL comparator reference voltage obtaining through resistance pressure-dividing network, in circuit design, select high conformity, precision ensures the high precision characteristic of resistance pressure-dividing network higher than 0.5% resistance, select in addition DAC and the ultra-low noise (1 μ Vp-p) of 10 precision, high precision (± 1mV), the reference voltage chip of Low Drift Temperature (3 ppm/ DEG C) ensures the precision of the upper and lower reference voltage configuring by DAC.
For ensureing the temporal resolution of system, the DAC in circuit can select the high-speed DAC of 100 MSPS renewal rates to ensure in timeslice handoff procedure, to realize fast reshuffling of upper and lower reference voltage, makes the large I of system minimum timeslice be set to 10nS.
Claims (6)
1. the super burst pulse measuring system of nanosecond, this system comprises high-speed pulse measurement module, FPGA control module, human-computer interaction module, human-computer interaction module is used for checking impulsive measurement result and system operational parameters is set, it is characterized in that, high-speed pulse measurement module comprises 3 road high-speed A/D converters, resistance pressure-dividing network, hypervelocity emitter-coupled logic ECL comparator array and hypervelocity ECL flip-flop array, wherein two-way high-speed A/D converter DAL_H and DAC_L provide for ECL comparator array, lower limit reference voltage, resistance pressure-dividing network is upper, in lower limit reference voltage range, carry out multistage network dividing potential drop, be respectively ECL comparator array reference comparison voltages is provided, ECL comparator array and ECL d type flip flop array pulse signals catch and latch, maximum amplitude to pulse in setting-up time sheet is measured, another road high-speed A/D converter DAC_T provide pulse compare threshold, measure the reference comparison voltages of comparer as pulse number, thereby the pulse enable signal pulse number that exceedes pulse compare threshold is measured the output saltus step of comparer and is triggered the upset of ECL T trigger, FPGA control module counts to get the umber of pulse in timeslice to the ECL T trigger output signal in Measuring Time sheet,
High-speed pulse measurement module is measured the maximum amplitude of pulse in setting-up time sheet and the pulse number that exceedes pulse compare threshold, the output level generation saltus step of comparer in the time that pulse amplitude exceedes the reference voltage level of comparer, make the set of ECL d type flip flop array, ECL d type flip flop array output signal is given FPGA control module after level conversion, then wait for that next timeslice measurement starts, the pulse height maximal value realizing in each timeslice is measured; In each Measuring Time sheet, in the time that pulse amplitude exceedes the reference voltage of threshold value comparer, comparer output level generation saltus step, thus trigger the upset of ECL T trigger, after level conversion, give FPGA control module counting by signal output, realize pulse number and measure;
Pulse height measure portion, FPGA control module to two high-speed A/D converter DAL_H and DAC_L be configured produce high, low two-way reference voltage, obtaining one group of reference voltage by resistance pressure-dividing network inputs as ECL comparator array Yi road respectively, pulse signal is by another road input as ECL comparator array after limiter protection circuit, in the time that Measuring Time sheet starts, ECL d type flip flop array is resetted, when input pulse signal becomes while being greater than reference voltage from being less than reference voltage, there is saltus step and cause trigger set thereafter in corresponding ECL comparator array output, in the time that Measuring Time sheet finishes, FPGA control module reads the output of ECL d type flip flop array, and according to pulse height maximal value in reference voltage level computation and measurement timeslice, level shifting circuit is Transistor-Transistor Logic level input FPGA by the ECL level conversion of ECL d type flip flop array output, step-by-step counting measure portion, in the time that Measuring Time sheet starts, FPGA control module configurable number weighted-voltage D/A converter DAC_T arranges step-by-step counting compare threshold, step-by-step counting compare threshold, pulse signal input pulse number are measured comparer generation saltus step pulse and are entered ECL T trigger, make ECL T trigger continuous overturning, FPGA counts to get the umber of pulse in timeslice to the ECL T trigger output signal in Measuring Time sheet.
2. the super burst pulse measuring system of nanosecond according to claim 1, it is characterized in that, in the time using outer triggering signal, system is carried out the measurement of first timeslice after trigger pip arrives, after first timeslice finishes, carry out the measurement of second timeslice, restart the measurement of first timeslice until next trigger pip arrives successively.
3. the super burst pulse measuring system of nanosecond according to claim 1, it is characterized in that, in the time not using outer triggering signal, system produces an internal trigger signal according to the timeslice number of the measuring-signal cycle of setting and the distribution of each signal period, and calculate each timeslice, measure in turn according to timeslice.
4. the super burst pulse measuring system of nanosecond described in one of them according to claim 1-3, is characterized in that, to high-acruracy survey pattern, by upper and lower reference voltage N decile, while measurement for the I time, upper and lower reference voltage settings H_I, L_I are respectively:
,
, wherein, VH, VL are respectively initial upper and lower limit reference voltage, and N is natural number, I=1,2 ... N.
5. the super burst pulse measuring system of nanosecond described in one of them according to claim 1-3, it is characterized in that, high-speed pulse measurement module high speed DAC provides for ECL comparator array, lower limit reference voltage, pulse compare threshold, resistance pressure-dividing network is upper, in lower limit reference voltage range, carry out Multilevel partial-pressure, for each comparer in ECL comparator array provides reference comparison voltages, ECL comparator array and ECL d type flip flop array pulse signals catch and latch, the maximum amplitude of pulse in setting-up time sheet and the pulse number that exceedes pulse compare threshold are measured.
6. the super burst pulse measuring system of nanosecond described in one of them according to claim 1-3, it is characterized in that, described FPGA control module arranges and trigger pip one-period is divided into multiple timeslice pulse signals measures according to system time sheet, and according to system the value of the estimation dynamic-configuration reference comparison voltages high-speed DAC to each timeslice pulse height.
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| US9407278B1 (en) * | 2015-07-01 | 2016-08-02 | Analog Devices Global | Digital to analog converter |
| CN108627743B (en) * | 2018-05-15 | 2020-05-05 | 国网江苏省电力有限公司电力科学研究院 | Lossless capture method for partial discharge nanosecond narrow pulse sequence |
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