CN102904551A - Constant fraction timing discriminator circuit - Google Patents
Constant fraction timing discriminator circuit Download PDFInfo
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- CN102904551A CN102904551A CN2012103774429A CN201210377442A CN102904551A CN 102904551 A CN102904551 A CN 102904551A CN 2012103774429 A CN2012103774429 A CN 2012103774429A CN 201210377442 A CN201210377442 A CN 201210377442A CN 102904551 A CN102904551 A CN 102904551A
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Abstract
The invention discloses a constant fraction timing discriminator circuit, and aims to improve the timing accuracy and the reliability. The constant fraction timing discriminator circuit consists of a buffer, a pre-discriminator, a constant fraction timing discriminator and a signal synthesizer; the buffer outputs VB to the pre-discriminator and the constant fraction timing discriminator after performing power amplification and drive capability enhancement on VIN; the pre-discriminator judges the VB, and outputs a result VP to the signal synthesizer; the constant fraction timing discriminator determines a timing point according to the VB, and outputs a timing signal VC to the signal synthesizer; the signal synthesizer generates a timing signal VOUT according to the VP and the VC; the constant fraction timing discriminator consists of a delayer, a low-pass filter and a first comparator; the low-pass filter adopts a first-order, multi-order resistance-capacitance (RC) or resistance-inductance-capacitance (RLC) low-pass filter; the delayer adopts a multi-level inductance-capacitance (LC) or resistance-inductance-capacitance (RLC) network; and the low-pass filter and the delayer set the timing point at a peak point of a reference signal or at the slope maximal point of a rising edge of a delay signal. The constant fraction timing discriminator circuit is high in stability, reliability and accuracy, small in size, easy to integrate and convenient to adjust.
Description
Technical field
The present invention relates to a kind of timing discriminator circuit, especially refer to a kind of constant fraction discriminator discriminator circuit of constantly differentiating for pulse signal.
Background technology
In range finder using laser and three-dimensional imaging laser radar based on the range finding of laser pulse flight time, because the variations such as distance, reflectivity and attitude of target can cause the echo laser pulse signal amplitude of target to change, thereby the electric impulse signal amplitude that causes photoelectric detective circuit to detect produces corresponding the variation.Differentiate if adopt fixed threshold timing discriminator circuit that electric impulse signal is carried out timing, pulse amplitude changes the timing error that can produce greatly.Fig. 1 is the principle schematic that fixed threshold timing discriminator circuit pulse signals is differentiated, among Fig. 1, signal is that amplitude is respectively V
P1, V
P2, V
P3Time dependent pulse voltage signal, if adopt fixed threshold voltage V
TCarry out timing and differentiate, the timing point that obtains (intersection point of threshold voltage and pulse signal) is respectively t
1, t
2, t
3, the timing point of visible three kinds of different amplitude pulses signals is different, has larger timing error.When the rise time of pulse signal be 10ns, when rangeability is 10 times, timing error is about 5ns, corresponding range measurement error based on the range finding of laser pulse flight time is about the product that 0.75m(range measurement error equals timing error and the light velocity).
In order to realize the high-precision laser range-finding of centimetre magnitude, need to adopt the high accuracy moment discriminator circuit of subnanosecond level, usually adopt the constant fraction discriminator discriminator circuit.The core of constant fraction discriminator discriminator circuit is the constant fraction discriminator discriminator, and Fig. 2 is the principle schematic that constant fraction discriminator discriminator pulse signals is differentiated, it adjusts threshold voltage automatically according to signal amplitude, thereby avoids signal amplitude to change the time drift that causes.In Fig. 2, be V to amplitude
P1, V
P2, V
P3Three kinds of pulse signals to adopt respectively threshold voltage be V
T1, V
T2, V
T3, and satisfy respectively and concern V
T1=pV
P1, V
T2=pV
P2, V
T3=pV
P3(p is the constant less than 1), the timing point that then obtains three kinds of range signals all is t
TAs seen adopt the constant fraction discriminator discriminator can effectively overcome signal amplitude and change the timing error that causes, its key is automatically to adjust threshold voltage according to signal amplitude.
Existing constant fraction discriminator discriminator is made of delayer, attenuator and comparator usually, and its primary structure as shown in Figure 3.Input signal V
INBe input to simultaneously delayer and attenuator, the signal after the time-delay is V
D, the signal after the decay is V
T, signal V
DAnd V
TBe input to respectively in-phase input end and the inverting input of comparator.Attenuator output signal V
TWith input signal V
INBecome fixed proportion, namely satisfy V
T=pV
IN(p is the constant less than 1).Signal V
TThe reference signal of device (threshold voltage) makes its size change with input signal amplitude by the constant fraction discriminator circuit as a comparison, has therefore realized the constant fraction discriminator identification function.Comparator output timing signal V
OUT, the signal leading edge represents the timing point that constant fraction discriminator is differentiated constantly.
Chinese patent CN102073051A discloses a kind of pulse laser distance measuring device that adopts the constant fraction discriminator discriminator, and this constant fraction discriminator discriminator also is made of delayer, attenuator and comparator.Attenuator adopts resistance pressure-dividing network, can not reduce the equivalent noise bandwidth of reference signal.Delayer adopts the resistance capacitance low pass filter, have a volume little, simple in structure and be easy to the advantages such as integrated, but the relative delay line of the distortion of time delayed signal is larger, can increase timing error.
Introduced a kind of constant fraction discriminator discriminator for laser ranging in " Shanghai Observatory, CAS's annual " magazine nineteen eighty-two the 4th interim " application of constant fraction discriminator discriminator in laser ranging " literary composition, it also is made of delayer, attenuator and comparator.Delayer adopts delay line to realize, has a time delayed signal distortion little and be conducive to improve the advantage such as timing accuracy, but have volume large, use not the shortcomings such as aspect and integrated difficulty are large.Attenuator adopts resistance pressure-dividing network to realize, can not reduce the equivalent noise bandwidth of reference signal.
" nuclear electronics and Detection Techniques " magazine was introduced a kind of constant fraction discriminator discriminator of non delay line in 2002 the 3rd in interim " a kind of constant fraction discriminator device of non delay line " literary composition, it is made of delayer, attenuator and comparator.The low pass filter that delayer adopts inductance and electric capacity to consist of realizes, have a volume little, simple in structure and be easy to the advantages such as integrated, but the relative delay line of the distortion of time delayed signal is larger, can increase timing error.Attenuator adopts resistance pressure-dividing network to realize, can not reduce the equivalent noise bandwidth of reference signal.
" laser and infrared " magazine was introduced a kind of constant fraction discriminator discriminator circuit in interim " high-precision laser range-finding technical research " literary composition in 2007 the 7th, and this constant fraction discriminator discriminator also is made of delayer, attenuator and comparator.Delayer adopts the snakelike cabling on circuit board to realize, has a time delayed signal distortion little and be conducive to improve the advantage such as timing accuracy, is subjected to the circuit board size restrictions, takies circuit area more greatly and the shortcoming such as easily is disturbed but have time-delay.
In the constant fraction discriminator discriminator, final timing accuracy and reliability and timing point method to set up are closely related.In present disclosed constant fraction discriminator discriminator, usually adopt mode shown in Figure 4 that timing point is set, wherein reference signal V
TBe attenuator output signal among Fig. 3, time delayed signal V
DBe delayer output signal among Fig. 3.Timing point t among Fig. 4
TBe arranged on signal V
TRising edge and signal V
DRising edge (intersection points of two rising edges), can reduce signal V like this
DWith respect to input signal V
INBetween time-delay, namely reduce the delay requirement to delayer.In addition, existing constant fraction discriminator discriminator does not illustrate concrete timing point method to set up usually, does not illustrate that namely timing point is at the particular location of reference signal and time delayed signal rising edge.
As seen, disclosed various constant fraction discriminator discriminators are made of attenuator, delayer and comparator usually at present.Delayer adopts delay line usually, perhaps adopts the linear networks such as resistance inductance low pass filter, resistance capacitance low pass filter or high pass filter.Attenuator adopts resistance pressure-dividing network usually.Adopt delay line to realize that delayer has distorted signals little and constantly differentiate the precision advantages of higher, but have volume greatly, not easy of integration with adjust the shortcoming such as relative difficulty.Adopt the linear networks such as resistance inductance low pass filter, resistance capacitance low pass filter or high pass filter replace delay lines have volume little, be easy to the advantages such as integrated and easy to adjust, but there is distortion in time delayed signal, has reduced timing accuracy.
How to make the constant fraction discriminator discriminator both had volume little, be easy to the advantages such as integrated and easy to adjust, have again higher timing accuracy and reliability, be the technical problem that those skilled in the art very pay close attention to.
Summary of the invention
The technical problem to be solved in the present invention is to propose a kind of novel constant fraction discriminator discriminator circuit, make its both had volume little, be easy to the advantages such as integrated and easy to adjust, have again higher timing accuracy and reliability.
Constant fraction discriminator discriminator circuit of the present invention is made of buffer, pre-discriminator, constant fraction discriminator discriminator and signal synthesizer.Buffer is from outside return pulse signal V
IN, to V
INCarry out obtaining signal V after power amplification and driving force strengthen
B, to pre-discriminator and constant fraction discriminator discriminator output signal V
BPre-discriminator obtains signal V from buffer
B, to V
BJudge, define pulse-free signal, with judging result signal V
PExport to signal synthesizer.The constant fraction discriminator discriminator obtains signal V from buffer
B, according to V
BDetermine timing point, with timing signal V
CExport to signal synthesizer.Signal synthesizer obtains signal V from pre-discriminator
P, obtain signal V from the constant fraction discriminator discriminator
C, obtaining reset signal RST from the outside, signal synthesizer is according to signal V
PWith signal V
CProduce final timing signal V
OUT, reset according to RST.
Buffer adopts the aanalogvoltage buffer of wideband low noise.Buffer is to V
INCarry out power amplification and driving force and strengthen rear output signal V
B, signal V
BWith signal V
INShape is identical.The band of buffer is wider than V
INBandwidth, the noise of buffer is less than V
INNoise, the delay jitter of buffer is less than the timing error of constant fraction discriminator discriminator circuit expectation, the output current of buffer is greater than the input current sum of pre-discriminator and constant fraction discriminator discriminator, and the output resistance of buffer is less than the parallel connection value of the input resistance of pre-discriminator and constant fraction discriminator discriminator.
The constant fraction discriminator discriminator is the core of constant fraction discriminator discriminator circuit, is made of delayer, low pass filter and the first comparator.Delayer receives V from buffer
B, to V
BDelay time, obtain time delayed signal V
D, and with V
DExport the in-phase input end of the first comparator to.Low pass filter receives signal V from buffer
B, to V
BDecay, noise reduction, broadening and time-delay obtain reference signal V
T, with V
TExport the inverting input of the first comparator to.The first comparator is to V
DAnd V
TVoltage compare output signal V
CTo signal synthesizer.The first comparator also can adopt another kind of connected mode: signal V
DBe connected to inverting input, signal V
TBe connected to in-phase input end, when the first comparator adopts this mode to connect, output signal V
C' with the V of the first connected mode
CShape is identical, polarity is opposite.
Low pass filter belongs to passive low ventilating filter, can adopt single order commonly used or multistage RC(resistance, electric capacity) low pass filter, also can adopt single order commonly used or multistage RLC(resistance, inductance, electric capacity) low pass filter.Low pass filter is not only to signal V
BCarry out constant ratio decay, and by the compression noise Bandwidth Reduction signal V
BNoise, also to signal V
BBroadening and time-delay have been carried out.Low pass filter need meet the following conditions:
(1) the bandwidth f of low pass filter
PLess than signal V
INBandwidth f
S
(2) the attenuation coefficient p of low pass filter should be so that the reference signal V that obtains after the decay
TCrest voltage equal V
BThe voltage of rising edge slope maximum point;
(3) each resistance of low pass filter, capacitance parameter (RC low pass filter) or each resistance, inductance, capacitance parameter (RLC low pass filter) are according to the bandwidth f that determines
P, attenuation coefficient p, low-pass filter structure and exponent number arrange, the method for 191～273 pages of introductions is analyzed and is arranged in " analysis of engineering circuits " sixth version of can write with reference to William H.Hayt etc., translation, the Electronic Industry Press such as Wang Dapeng publishing in 2002.
Delayer is to input signal V
BDelay time, the signal after the time-delay is V
DDelayer adopts multistage LC network or multistage RLC network.This delayer both can reach or near the distorted signals level of delay line, had again that time-delay is easy to adjust, volume is little and be easy to the advantages such as integrated.Delayer need meet the following conditions:
(1) the delay parameter T of delayer
DSatisfy: T
D=T
D1+ T
D2T
D1Be the time-delay of low pass filter, i.e. signal V
TWith signal V
BBetween time-delay, obtain by oscilloscope measurement; T
D2Be signal V
BIn the time interval between rising edge slope maximum point and the peak point, also obtain by oscilloscope measurement.
(2) delayer structure and progression N(N are for greater than 1 constant) according to discriminating precision, the area of circuit, became original and comprehensively determined, adopt N level LC network or RLC network.The LC network refers to the network that the identical lc unit of a plurality of structures consists of, and each unit comprises 1 inductance L and 1 capacitor C.One end of inductance L is the lc unit input, is connected with output or the external input signal of a upper unit; The other end is the lc unit output, is connected with input or the external output signal of next lc unit.One end of capacitor C is connected with the output of lc unit, and the other end is connected to ground.The RLC network refers to the RLC cell formation network that a plurality of structures are identical, and each unit comprises 1 resistance, 1 inductance L and 1 capacitor C.One end of resistance R is the input of RLC unit, is connected with output or the external input signal of a upper RLC unit; The other end connects inductance L.Inductance L one end is RLC unit output, is connected inductance L other end contact resistance R with input or the external output signal of next RLC unit.One end of capacitor C is connected with the output of RLC unit, and the other end is connected to ground.
(3) each inductance of delayer, capacitance parameter (LC network) or each resistance, inductance, capacitance parameter (RLC network) are according to the delay parameter T that determines
D, delayer structure and progression N arrange, the method for 236～273 pages of introductions is analyzed and is arranged in " analysis of engineering circuits " sixth version of can write with reference to William H.Hayt etc., translation, the Electronic Industry Press such as Wang Dapeng publishing in 2002.Because the time-delay T of delayer
D=T
D1+ T
D2, and the reference signal V after the low pass filter decay
TCrest voltage equal V
BThe voltage of rising edge slope maximum point is so examine signal V
TPeak point and V
BRising edge slope maximum point overlaps (this point is timing point).
The first comparator is to reference signal V
TWith time delayed signal V
DCompare, as time delayed signal V
DGreater than reference signal V
TTime output high level, otherwise output low level; The output signal of the first comparator is V
C, the timing point of the rising edge respective pulses signal of this signal.In order to improve the reliability and stability of whole constant fraction discriminator device, the first comparator adopts the comparator with hysteresis comparing function, and the hysteresis comparative voltage can arrange flexibly.The response time of the first comparator is less than signal V
INRise time, noise is less than signal V
INNoise, delay jitter is less than the timing error of constant fraction discriminator discriminator circuit expectation.
Above-mentioned low pass filter and delayer have been realized a kind of timing point method to set up of new constant fraction discriminator discriminator, and timing point is arranged on the peak point of reference signal and the rising edge slope maximum point of time delayed signal.This timing point method to set up can obviously improve timing accuracy and reliability, main cause has: low pass filter carries out broadening to input signal and obtains reference signal, near this reference signal rate of change timing point is less and stabilization time is long, and this mode can improve stability and the reliability of constant fraction discriminator discriminator; Timing point is arranged on the slope maximum point of time delayed signal rising edge, and is arranged on peak point rather than the rising edge of reference signal, the rate of rise that this mode can increase between time delayed signal and the reference signal is poor, thus the timing error that noise decrease causes.
Pre-discriminator is made of resistance pressure-dividing network and the second comparator.The resistor network that resistance pressure-dividing network adopts variable resistor and fixed resistance to consist of is realized dividing potential drop, the reference voltage V that the input of resistance pressure-dividing network is connected and fixed
REFResistance pressure-dividing network is according to V
REFProduce threshold voltage V
R, with V
RExport the reverse input end of the second comparator to.Make the threshold voltage V of the output of resistance pressure-dividing network by regulating variable resistor
RGreater than signal V
BNoise.The in the same way input of the second comparator receives signal V
B, the second comparator is to V
BAnd V
RCompare and export pre-distinguishing signal V
PWork as V
BGreater than V
RThe time pre-distinguishing signal V
PBe high level (expression has pulse signal), otherwise pre-distinguishing signal V
PBe low level (expression does not have pulse signal).The second comparator also can adopt another kind of connected mode: signal V
BBe connected to inverting input, threshold voltage V
RBe connected to in-phase input end.When the second comparator adopts this mode to connect, pre-distinguishing signal V
P' with the V of the first connected mode
PShape is identical, polarity is opposite.
Signal synthesizer adopts the d type flip flop with reset function, and the delay jitter of this d type flip flop is less than the timing error of constant fraction discriminator discriminator circuit expectation.The data input pin D of d type flip flop receives V from pre-discriminator
P, the input end of clock CLK of d type flip flop receives V from the constant fraction discriminator discriminator
C, the RESET input of d type flip flop receives the reset signal RST of outside input, and the d type flip flop output is the final timing signal V of constant fraction discriminator discriminator circuit output
OUTSignal synthesizer is according to V
PAnd V
CProduce final timing signal V
OUT, can reset to signal synthesizer the output signal V after resetting by reset signal RST
OUTBe low level.As pre-distinguishing signal V
PBe high level (expression has pulse signal) and signal V
CSignal V when rising edge (timing point of corresponding constant fraction discriminator discriminator) occurring
OUTBecome high level by low level, signal V
OUTThe timing point of the corresponding constant fraction discriminator discriminator of rising edge.Before the next pulse signal arrived, RST resetted to signal synthesizer by reset signal.When not having pulse signal, pre-distinguishing signal V
PBe always low level, even the constant fraction discriminator discriminator is because noise or interference cause false triggering, the output of signal synthesizer is always low level, can obviously improve the reliability and stability of whole constant fraction discriminator discriminator circuit.
Compare with existing constant fraction discriminator discriminator circuit, adopt the present invention can reach following technique effect:
(1) replaces attenuator in the existing constant fraction discriminator discriminator with low pass filter, produced the reference signal V that changes with input signal amplitude except input signal having been carried out the fixed proportion decay
T, also have advantages of two aspects: make that near reference signal rate of change timing point is less and stabilization time is long thereby input signal is carried out broadening, improved stability and the reliability of constant fraction discriminator discriminator; Reduce the noise equivalent bandwidth of reference signal by low pass filter, reduced the noise of reference signal, reduced the timing error that noise causes;
(2) low pass filter of constant fraction discriminator discriminator and and the parameter of each components and parts of delayer satisfy timing point be arranged on the slope maximum point of time delayed signal rising edge and the peak point of reference signal, the rate of rise that can increase between time delayed signal and the reference signal is poor, thus the timing error that noise decrease causes;
(3) delayer adopts multistage LC or RLC network, has both had advantages of that the time delayed signal distortion was little and constantly differentiate that precision is high, have again volume little, be easy to the advantages such as integrated and easy to adjust;
(4) pre-discriminator and signal synthesizer can effectively be eliminated the false triggering that noise causes the constant fraction discriminator discriminator, obviously improve the reliability and stability of whole constant fraction discriminator discriminator circuit.
Description of drawings
Fig. 1 is the schematic diagram that the employing fixed threshold of background technology announcement is regularly differentiated pulse signal;
Fig. 2 is the schematic diagram of the employing constant fraction discriminator discriminator pulse signal of background technology announcement;
Fig. 3 is the building-block of logic of the existing constant fraction discriminator discriminator of background technology announcement;
Fig. 4 is that the timing point of the existing constant fraction discriminator discriminator of background technology announcement arranges schematic diagram;
Fig. 5 is the building-block of logic of constant fraction discriminator discriminator circuit of the present invention;
Fig. 6 is the building-block of logic of constant fraction discriminator discriminator of the present invention;
Fig. 7 is the delayer structure chart of the multistage LC network that adopts of the present invention;
Fig. 8 is the delayer structure chart of the multistage RLC network that adopts of the present invention;
Fig. 9 is that timing point of the present invention arranges schematic diagram;
Figure 10 is the building-block of logic of the pre-discriminator of the present invention.
Embodiment
Fig. 5 is the building-block of logic of constant fraction discriminator discriminator circuit of the present invention.This constant fraction discriminator discriminator circuit is made of buffer, pre-discriminator, constant fraction discriminator discriminator and signal synthesizer.The input of buffer and outside input pulse signal V
INConnect, buffer is to V
INCarry out power amplification and driving force and strengthen rear output signal V
BThe output of buffer and pre-discriminator are connected input and are connected with the constant fraction discriminator discriminator.The input of pre-discriminator connects signal V
BWith reference voltage V
REF, pre-discriminator is to signal V
BJudge, define pulse-free signal.The output signal of pre-discriminator is judging result signal V
P, the output of pre-discriminator is connected with the input of signal synthesizer.The input of constant fraction discriminator discriminator connects signal V
B, the constant fraction discriminator discriminator is according to signal V
BDetermine timing point, output timing signal V
CThe output of constant fraction discriminator discriminator is connected with the input of signal synthesizer.Signal synthesizer has three inputs and an output, and first input connects signal V
P, second input connects signal V
C, the 3rd input connects the reset signal RST of outside input.Signal synthesizer is according to signal V
PWith signal V
CProduce final timing signal V
OUTSignal RST is the control signal of outside input, by this signal signal synthesizer is resetted.
Fig. 6 is the building-block of logic of constant fraction discriminator discriminator of the present invention.This constant fraction discriminator discriminator is made of delayer, low pass filter and the first comparator.Delayer receives signal V from buffer
B, to signal V
BDelay time, obtain time delayed signal V
D, and with signal V
DExport the in-phase input end of the first comparator to.Low pass filter receives signal V from buffer
B, to signal V
BDecay, noise reduction, broadening and time-delay obtain reference signal V
T, low pass filter is with reference to signal V
TExport the inverting input of the first comparator to.The first comparator is to signal V
DWith signal V
TVoltage compare output signal V
CTo signal synthesizer.The first comparator also can adopt another kind of connected mode: signal V
DBe connected to inverting input, signal V
TBe connected to in-phase input end.When the first comparator adopted this mode to connect, the shape of output signal was identical, polarity is opposite.
Fig. 7 is the delayer structure chart of multistage LC network.The LC network refers to the network that the identical lc unit of a plurality of structures consists of, and each unit comprises 1 inductance L and 1 capacitor C.One end of inductance L is the lc unit input, is connected with output or the external input signal of a upper unit; The other end is the lc unit output, is connected with input or the external output signal of next lc unit.One end of capacitor C is connected with the output of lc unit, and the other end is connected to ground.
Fig. 8 is the delayer structure chart of multistage RLC network.The RLC network refers to the RLC cell formation network that a plurality of structures are identical, and each unit comprises 1 resistance, 1 inductance L and 1 capacitor C.One end of resistance R is the input of RLC unit, is connected with output or the external input signal of a upper RLC unit; The other end connects inductance L.Inductance L one end is RLC unit output, is connected inductance L other end contact resistance R with input or the external output signal of next RLC unit.One end of capacitor C is connected with the output of RLC unit, and the other end is connected to ground.
Fig. 9 is that the timing point that the present invention proposes arranges schematic diagram.Utilize low pass filter and delayer to realize a kind of timing point method to set up of new constant fraction discriminator discriminator, timing point is arranged on reference signal V
TPeak point and time delayed signal V
DRising edge slope maximum point.Constant fraction discriminator discriminator output signal V
CThe timing point t of rising edge respective pulses signal
T
Figure 10 is the building-block of logic of pre-discriminator.Pre-discriminator is made of resistance pressure-dividing network and the second comparator.The resistor network that resistance pressure-dividing network adopts variable resistor and fixed resistance to consist of is realized dividing potential drop, the reference voltage V that the input of resistance pressure-dividing network is connected and fixed
REFResistance pressure-dividing network is according to the reference voltage V of input
REFProduce threshold voltage V
R, and with V
RExport the reverse input end of the second comparator to.Make the threshold voltage V of resistance pressure-dividing network output by regulating variable resistor
RGreater than signal V
BNoise.The in the same way input of the second comparator receives signal V
B, the second comparator is to signal V
BWith threshold voltage V
RCompare and export pre-distinguishing signal V
PAs signal V
BGreater than threshold voltage V
RThe time pre-distinguishing signal V
PBe high level (expression has pulse signal), otherwise pre-distinguishing signal V
PBe low level (expression does not have pulse signal).
Claims (11)
1. a constant fraction discriminator discriminator circuit is characterized in that the constant fraction discriminator discriminator circuit is made of buffer, pre-discriminator, constant fraction discriminator discriminator and signal synthesizer; Buffer is from outside return pulse signal V
IN, to V
INCarry out obtaining signal V after power amplification and driving force strengthen
B, to pre-discriminator and constant fraction discriminator discriminator output signal V
BPre-discriminator obtains signal V from buffer
B, to V
BJudge, define pulse-free signal, with judging result signal V
PExport to signal synthesizer; The constant fraction discriminator discriminator obtains signal V from buffer
B, according to V
BDetermine timing point, with timing signal V
CExport to signal synthesizer; Signal synthesizer obtains signal V from pre-discriminator
P, obtain signal V from the constant fraction discriminator discriminator
C, obtaining reset signal RST from the outside, signal synthesizer is according to signal V
PWith signal V
CProduce final timing signal V
OUT, reset according to RST.
2. a kind of constant fraction discriminator discriminator circuit as claimed in claim 1 is characterized in that described buffer adopts the aanalogvoltage buffer of wideband low noise, and the band of buffer is wider than V
INBandwidth, the noise of buffer is less than V
INNoise, the delay jitter of buffer is less than the timing error of constant fraction discriminator discriminator circuit expectation, the output current of buffer is greater than the input current sum of pre-discriminator and constant fraction discriminator discriminator, and the output resistance of buffer is less than the parallel connection value of the input resistance of pre-discriminator and constant fraction discriminator discriminator.
3. a kind of constant fraction discriminator discriminator circuit as claimed in claim 1 is characterized in that described constant fraction discriminator discriminator is made of delayer, low pass filter and the first comparator; Delayer receives V from buffer
B, to V
BDelay time, obtain time delayed signal V
D, and with V
DExport the in-phase input end of the first comparator to; Low pass filter receives signal V from buffer
B, to V
BDecay, noise reduction, broadening and time-delay obtain reference signal V
T, with V
TExport the inverting input of the first comparator to; The first comparator is to V
DAnd V
TVoltage compare, to signal synthesizer output signal V
C, work as V
DGreater than V
TThe time, V
CBe high level, otherwise V
CBe low level; V
CThe timing point of rising edge respective pulses signal.
4. a kind of constant fraction discriminator discriminator circuit as claimed in claim 3, it is characterized in that described low pass filter belongs to passive low ventilating filter, adopt single order or multistage RC low pass filter, or single order or multistage RLC low pass filter, low pass filter need meet the following conditions:
4.1 the bandwidth f of low pass filter
PLess than signal V
INBandwidth f
S
4.2 the attenuation coefficient p of low pass filter should be so that the reference signal V that obtains after the decay
TCrest voltage equal V
BThe voltage of rising edge slope maximum point;
If 4.3 low pass filter adopts the RC low pass filter, its resistance, capacitance parameter are according to the bandwidth f that determines
P, attenuation coefficient p, low-pass filter structure and exponent number arrange, if low pass filter adopts the RLC low pass filter, its resistance, inductance, capacitance parameter are according to the bandwidth f that determines
P, attenuation coefficient p, low-pass filter structure and exponent number arrange.
5. a kind of constant fraction discriminator discriminator circuit as claimed in claim 3 is characterized in that described delayer is to input signal V
BDelay time, the signal after the time-delay is V
D, delayer adopts multistage LC network or multistage RLC network, and delayer need meet the following conditions:
5.1 the delay parameter T of delayer
DSatisfy: T
D=T
D1+ T
D2T
D1Be the time-delay of low pass filter, i.e. signal V
TWith signal V
BBetween time-delay, obtain by oscilloscope measurement; T
D2Be signal V
BIn the time interval between rising edge slope maximum point and the peak point, also obtain by oscilloscope measurement;
5.2 delayer structure and progression N according to discriminating precision, the area of circuit, became original and comprehensively determined, adopt N level LC network or RLC network, N is the constant greater than 1.
If 5.3 delayer adopts the LC network, its inductance, capacitance parameter are according to the delay parameter T that determines
D, delayer structure and progression N arrange, if delayer adopts the RLC network, its resistance, inductance, capacitance parameter are according to the delay parameter T that determines
D, delayer structure and progression N arrange.
6. a kind of constant fraction discriminator discriminator circuit as claimed in claim 3 it is characterized in that described the first comparator adopts and has the comparator that hysteresis comparing function and hysteresis comparative voltage can arrange, and the response time of the first comparator is less than signal V
INRise time, noise is less than signal V
INNoise, delay jitter is less than the timing error of constant fraction discriminator discriminator circuit expectation.
7. a kind of constant fraction discriminator discriminator circuit as claimed in claim 1 is characterized in that described pre-discriminator is made of resistance pressure-dividing network and the second comparator; The resistor network that resistance pressure-dividing network adopts variable resistor and fixed resistance to consist of is realized dividing potential drop, the reference voltage V that the input of resistance pressure-dividing network is connected and fixed
REF, resistance pressure-dividing network is according to V
REFProduce threshold voltage V
R, with V
RExport the reverse input end of the second comparator to, make the threshold voltage V of the output of resistance pressure-dividing network by regulating variable resistor
RGreater than signal V
BNoise; The in the same way input of the second comparator receives signal V
B, the second comparator is to V
BAnd V
RCompare and export pre-distinguishing signal V
PWork as V
BGreater than V
RThe time pre-distinguishing signal V
PBe high level, otherwise pre-distinguishing signal V
PBe low level.
8. a kind of constant fraction discriminator discriminator circuit as claimed in claim 1 is characterized in that described signal synthesizer adopts the d type flip flop with reset function, and the delay jitter of this d type flip flop is less than the timing error of constant fraction discriminator discriminator circuit expectation; The data input pin D of d type flip flop receives V from pre-discriminator
P, the input end of clock CLK of d type flip flop receives V from the constant fraction discriminator discriminator
C, the RESET input of d type flip flop receives the reset signal RST of outside input, and the d type flip flop output is the final timing signal V of constant fraction discriminator discriminator circuit output
OUTSignal synthesizer is according to V
PAnd V
CProduce final timing signal V
OUT, as pre-distinguishing signal V
PBe high level and signal V
CSignal V when rising edge occurring
OUTBecome high level by low level, before the next pulse signal arrived, RST resetted to signal synthesizer by reset signal; When not having pulse signal, pre-distinguishing signal V
PBe always low level, even the constant fraction discriminator discriminator is because noise or interference cause false triggering, the output of signal synthesizer is always low level.
9. a kind of constant fraction discriminator discriminator circuit as claimed in claim 3 is characterized in that described the first comparator adopts another kind of connected mode: signal V
DBe connected to inverting input, signal V
TBe connected to in-phase input end, when the first comparator adopts this mode to connect, output signal V
C' with the V of the first connected mode
CShape is identical, polarity is opposite.
10. a kind of constant fraction discriminator discriminator circuit as claimed in claim 3 is characterized in that described LC network refers to the network that the identical lc unit of a plurality of structures consists of, and each unit comprises 1 inductance L and 1 capacitor C; One end of inductance L is the lc unit input, is connected with output or the external input signal of a upper unit, and the other end is the lc unit output, is connected with input or the external output signal of next lc unit; One end of capacitor C is connected with the output of lc unit, and the other end is connected to ground; The RLC network refers to the RLC cell formation network that a plurality of structures are identical, and each unit comprises 1 resistance, 1 inductance L and 1 capacitor C; One end of resistance R is the input of RLC unit, is connected with output or the external input signal of a upper RLC unit, and the other end connects inductance L; Inductance L one end is RLC unit output, is connected inductance L other end contact resistance R with input or the external output signal of next RLC unit; One end of capacitor C is connected with the output of RLC unit, and the other end is connected to ground.
11. a kind of constant fraction discriminator discriminator circuit as claimed in claim 3 is characterized in that described the second comparator adopts another kind of connected mode: signal V
BBe connected to inverting input, threshold voltage V
RBe connected to in-phase input end, when the second comparator adopts this mode to connect, pre-distinguishing signal V
P' with the V of the first connected mode
PShape is identical, polarity is opposite.
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| CN105548671A (en) * | 2016-01-15 | 2016-05-04 | 中山芯达电子科技有限公司 | Voltage threshold value detection output circuit |
| CN107272011A (en) * | 2017-06-01 | 2017-10-20 | 清华大学 | Time point discrimination method, time point discriminator circuit system and LDMS |
| CN107947782A (en) * | 2017-11-28 | 2018-04-20 | 南京优倍电气有限公司 | A kind of circuit for improving optocoupler transmission characteristic |
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| CN108919282A (en) * | 2018-05-17 | 2018-11-30 | 北京航空航天大学 | A kind of laser radar signal moment identification system |
| CN109031249A (en) * | 2018-08-17 | 2018-12-18 | 中科光绘（上海）科技有限公司 | Return laser beam discriminating method based on FPGA |
| CN109031249B (en) * | 2018-08-17 | 2022-08-09 | 中科光绘（上海）科技有限公司 | Laser echo discrimination method based on FPGA |
| CN110492871A (en) * | 2019-09-06 | 2019-11-22 | 电子科技大学 | Along the constant fraction discriminator circuit of timing after a kind of |
| CN111404518A (en) * | 2020-02-25 | 2020-07-10 | 成都天奥测控技术有限公司 | Flexible and adjustable time delay comparison method and system |
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