CN103837739B - Time domain and frequency domain synthesis test device - Google Patents
Time domain and frequency domain synthesis test device Download PDFInfo
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- CN103837739B CN103837739B CN201210492438.7A CN201210492438A CN103837739B CN 103837739 B CN103837739 B CN 103837739B CN 201210492438 A CN201210492438 A CN 201210492438A CN 103837739 B CN103837739 B CN 103837739B
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Abstract
The present invention relates to a kind of test device, particularly relate to the time domain in a kind of electronic measuring instrument field, frequency domain synthesis test device.The time domain of the present invention and frequency domain synthesis test device, including front end signal chain, sampling and image-forming module, data exchange module, main control module, display and user interactive module, interface and expansion module, power module, spectrum analysis module, RF programmable conditioning module, front end signal chain is by sampling and image-forming module and data exchange module communication, RF programmable conditioning module is by spectrum analysis module and main control module communication, and data exchange module electrically connects with main control module, display and user interactive module, interface and expansion module, power module respectively.Test function can be selectively extended for user, Observable time domain and frequency-region signal simultaneously, observe the RF spectrum on any time point, watch frequency spectrum in time or with the change of device state.
Description
Technical field
The present invention relates to a kind of test device, particularly relate to the time domain in a kind of electronic measuring instrument field, frequency domain
Comprehensive test device.
Background technology
Electronic measuring instrument field needs a kind of existing oscillograph function observation medium and low frequency signal, has again spectrum analysis
Instrument function observation high-frequency signal.Meet the test equipment that time domain, frequency domain synthesis testing requirement and cost performance are high,
Its energy quick obtaining time domain, frequency-domain waveform and relevant parameter index, just accurately judging equipment working state
Whether normal, and these Test data generation test texts are entered computer interactive maintenance system.U.S. TEK
The MDO4000 hybrid domain oscillograph of company's up-to-date release in 2011, is provided simultaneously with time domain, frequency domain, time-frequency domain
Deng multiple domain waveform measurement function.MDO4 000 breaches the obstacle between time domain and frequency domain, and it fundamentally changes
RF designs debugging, RF design debugging in, engineer need by the event in frequency domain with cause these events
Time domain phenomenon associates, and mixed signal oscillograph (MSO) is as being both the conventional tool of embedded design test.
Hybrid domain oscillograph will become the new standard with RF functional design that demand increases day by day.For breaks through foreign skill
Art barrier, state's domestic demand develops the device of a kind of time-domain and frequency-domain integration test.
Summary of the invention
The technique effect of the present invention can overcome drawbacks described above, it is provided that a kind of time domain and frequency domain synthesis test device,
It can selectively extend test function for user, simultaneously Observable time domain and frequency-region signal.
For achieving the above object, the present invention adopt the following technical scheme that it include front end signal chain, sampling and
Image-forming module, data exchange module, main control module, display and user interactive module, interface and expansion module,
Power module, spectrum analysis module, RF programmable conditioning module, front end signal chain is by sampling and image-forming module
With data exchange module communication, RF programmable conditioning module is by spectrum analysis module and main control module communication, number
According to Switching Module respectively with main control module, display and user interactive module, interface and expansion module, power supply mould
Block electrically connects.
Native system uses the design of modular thinking to realize.After signal accesses oscillograph, initially enter front end letter
Number chain, decays to signal, amplifies, the link such as filtering, is converted to meet the signal of ADC input requirements,
Send into sampling and image-forming module.The latter is the nucleus module of whole system, and its function is by signal by ADC
Quantify sampling and be converted to digital signal, digital signal is stored and is converted to ripple by digital phosphor imaging engine
Shape image exports.Each module can accept the data of two passages and process, and therefore system needs two together altogether
The sampling of sample and image-forming module.The data of two modules through data exchange module collect and export to display and
User interactive module, presents waveform image to user.This process is calculated by main control computer control, master control
Control instruction and the data of machine convey to sampling and image-forming module also through data exchange module.RF signal accesses
After RF passage, through RF programmable conditioning circuit, spectrum analysis module, the data of module are through data exchange module
Collecting and export to display and user interactive module, presenting spectrum analysis image to user, power module is
System provides reliable and stable power supply.
Front end signal chain includes permutator, impedance transducer, programmable attenuator, program control attenuation module, journey
Control gain module, digital to analog converter, analog input signal connect after permutator respectively by impedance transducer,
Programmable attenuator processes, and is connected with program control attenuation module by permutator, program control attenuation module and program control increasing
Benefit module electrical connection, digital to analog converter electrically connects with program control attenuation module, programme-controlled gain module respectively.
Sampling and image-forming module include double-channel analog/digital transducer, DDR2-SDRAM memory module,
QDR2-SRAM memorizer, cryptographic protocol chip, FPGA module, double-channel analog/digital transducer, DDR2-SDRAM
Memory module, QDR2-SRAM memorizer, cryptographic protocol chip electrically connect with FPGA module respectively.FPGA
Module include sampling controller, storage manager, high-speed figure fluorescence waveform imaging engine, stringization/deserializer,
Random number generator, encryption option manager, sampling controller is by storage manager and high-speed figure fluorescence
Waveform imaging engine electrically connect, high-speed figure fluorescence waveform imaging engine connect respectively stringization/deserializer,
QDR2-SRAM memorizer, waveform arithmetic processor, sampling controller connects trigger controller, storage manager
Connecting storage control, FFT engine respectively, storage control is connected with DDR2-SDRAM memory module,
Stringization/deserializer link order decoder, random number generator electrically connects with encryption option manager, encryption choosing
Part manager electrically connects with cryptographic protocol chip.
Data exchange module includes serialization/solution serial unit, data exchange unit, instruction parser, video
Image superimposition unit, pci bus bridge, serialization/solution serial unit solves with data exchange unit, instruction respectively
Parser electrically connects, and data exchange unit, instruction parser electrically connect with pci bus bridge respectively, and data exchange
Unit electrically connects with video and graph compound unit.
Spectrum analysis module includes attenuator, low pass filter, frequency mixer, intermediate-frequency filter, analog digital conversion
Module, data process and exchange system, variable local oscillator generator, and attenuator connects mixed by low pass filter
Frequently device, frequency mixer passes sequentially through intermediate-frequency filter, analog-to-digital conversion module is connected with data process and exchange system,
Data process and exchange system feeds back to frequency mixer by variable local oscillator generator.
The present invention uses embedded multiprocessor and FPGA to be master control manager, uses Windows to operate system
System, build one not by form and function limited have the function such as oscillograph, spectrum analyzer portable time
Territory frequency domain synthesis test device, can be according to the testing requirement of user to test system flexible configurations, and degree body is customized
Test system, and the Function Extension interface card that system itself is reserved, can selectively extend test merit for user
Can, Observable time domain and frequency-region signal simultaneously, observe the RF spectrum on any time point, viewing frequency spectrum is in time
Or the change with device state.
Accompanying drawing explanation
Fig. 1 is the integral module schematic diagram of the present invention；
Fig. 2 is the front end signal chain module diagram of the present invention；
Fig. 3 is sampling and the image-forming module schematic diagram of the present invention；
Fig. 4 is the data exchange module schematic diagram of the present invention；
Fig. 5 is the spectrum analysis module schematic diagram of the present invention.
Detailed description of the invention
As it is shown in figure 1, the time domain of the present invention and frequency domain synthesis test device, including front end signal chain, sampling
And image-forming module, data exchange module, main control module, display and user interactive module, interface and expanded mode
Block, power module, spectrum analysis module, RF programmable conditioning module, front end signal chain is by sampling and imaging
Module and data exchange module communication, RF programmable conditioning module by spectrum analysis module and main control module communication,
Data exchange module respectively with main control module, display and user interactive module, interface and expansion module, power supply
Module electrically connects
Oscillograph front end signal chain, front end signal chain achieves the amplification of signal, decay, impedance transformation, filter
The signal condition work such as ripple.The theory diagram of this part is as shown in Figure 2:
Front end signal chain includes permutator, impedance transducer, programmable attenuator, program control attenuation module, journey
Control gain module, digital to analog converter, analog input signal connect after permutator respectively by impedance transducer,
Programmable attenuator processes, and is connected with program control attenuation module by permutator, program control attenuation module and program control increasing
Benefit module electrical connection, digital to analog converter electrically connects with program control attenuation module, programme-controlled gain module respectively.
Signal, by probe input system, is sent into impedance transformer after high impedance programmable attenuator is decayed and is entered
The impedance transformation of row 1M Ω to 50 Ω, using the teaching of the invention it is possible to provide the analog bandwidth of about 5 00MHz.When input impedance selects
When being 50 Ω, signal is directly over radio frequency programmable attenuator and decays.Enable signals to after impedance switching
Transmit under Low ESR (50 Ω) environment, realize 500MHz's through programmable attenuator and gain-programmed amplifier
1-2-5 step gain/the decay of analog bandwidth and 2mV ~ 1V/div.For realizing the numeral of gain and displacement
Controlling, this part is provided with two DAC.
Sampling and image-forming module, be the nucleus module of native system, and all related algorithms are all able to reality in FPGA
Existing.The theory diagram of this part is as shown in Figure 3:
Sampling and image-forming module include double-channel analog/digital transducer, DDR2-SDRAM memory module,
QDR2-SRAM memorizer, cryptographic protocol chip, FPGA module, double-channel analog/digital transducer, DDR2-SDRAM
Memory module, QDR2-SRAM memorizer, cryptographic protocol chip electrically connect with FPGA module respectively.
FPGA module includes sampling controller, storage manager, high-speed figure fluorescence waveform imaging engine, string
Change/deserializer, random number generator, encryption option manager, sampling controller is by storage manager and height
Speed digital fluorescence waveform imaging engine electrically connects, and high-speed figure fluorescence waveform imaging engine connects stringization/solution respectively
String device, QDR2-SRAM memorizer, waveform arithmetic processor, sampling controller connects trigger controller, storage
Manager connects storage control, FFT engine, storage control and DDR2-SDRAM memory module respectively
Connecting, stringization/deserializer link order decoder, random number generator electrically connects with encryption option manager,
Encryption option manager electrically connects with cryptographic protocol chip.
As oscillographic core devices, ADC receives the signal of AFE (analog front end) and inputs and be converted to digital signal.
For realizing high sampling rate and the bandwidth of 500MHz of 2.5GSa/s, the selection of ADC is most important.Here select
Select EV8AQ160 type ADC that E2V company produces, there is inside it 8bit of 4 independent 1.25GSa/s
Sub-ADC, and wherein each two ADC can alternately realize the sample rate of 2.5GSa/s, due to each sampling with
Image-forming module configure a piece of EV8AQ160 type ADC process two passages data, the amplitude of ADC, gain and
Timing all can be finely tuned by software it is achieved thereby that higher significance bit.The analog bandwidth of ADC up to 3GHz,
Meet system requirements.
FPGA achieves all signal processing work being input to waveform imaging transmission from digital signal, is product
Core place.FPGA by sampling controller, trigger controller, Waveform storage manager, storage control,
FFT engine and digital phosphor waveform imaging engine composition.Wherein storage control needs plug-in DDR2-SDRAM to deposit
Reservoir module is as wave memorizer, and digital phosphor waveform imaging engine needs plug-in QDR2-SRAM as one-tenth
As memorizer.Signal from ADC enters trigger controller, it is achieved complicated condition trigger mechanism, and right
It is sampled, and by storage and read-out controller, is stored in wave memorizer.If desired, hardware FFT
It is frequency-region signal that engine will carry out FFT to it.The waveform of two passages after imaging passes through serializer/solution
String device (SERDES) is encoded to the serial data of 2.5Gbps and sends, and is simultaneously from the finger of data exchange module
Order and data are sent into also through SERDES and are decoded by instruction decoder, control the running of FPGA.Due to
Each module in FPGA all can process two-way sampled data simultaneously, and the most each sampling uses with image-forming module
1 FPGA.
Owing to this system has multiple option, therefore it is provided with encryption option manager for managing software and hardware choosing
Part.Encryption option administrative section by random generator,.Encryption option manager and the cryptographic protocol core of outside
Sheet forms.The reason arranging this part is the function mandate of managing device, user's mandate, prevents device
Illegally copy and the intellectual property of protection device.Specific practice is: every table apparatus is respectively provided with a unique association
View, this agreement leaves in the protocol chip of main frame.At regular intervals, random generator produces one 32
The random number of position, sends protocol chip to.Protocol chip uses this random number and built-in double secret key agreement to enter
Protocol manager is returned to after row encryption.With built-in double secret key, it is decrypted protocol manager, if agreement
Correctly, can be according to the open function authorized of protocol contents.After using device panel to input corresponding grant number,
Grant number encodes the Enhancement Technology indicating user to agreement simultaneously.
Data exchange module, data exchange module is the data center of system, is responsible for the data communication of modules,
There is provided clock stable, that synchronize for modules simultaneously.Owing to the communication protocol of modules is different, therefore
Data exchange module must have the support of various protocols.Here data exchange module is also made up of a piece of FPGA,
As shown in Figure 4:
Data exchange module includes serialization/solution serial unit, data exchange unit, instruction parser, video
Image superimposition unit, pci bus bridge, serialization/solution serial unit solves with data exchange unit, instruction respectively
Parser electrically connects, and data exchange unit, instruction parser electrically connect with pci bus bridge respectively, and data exchange
Unit electrically connects with video and graph compound unit.
Data exchange module has 4 serializer/deserializers (SERDES), 1 pci bus bridge and 1
Video Controller, is carried out the exchange of each circuit-switched data by MUX.Wherein 2 SERDES connect two samplings respectively
With image-forming module, two other SERDES is standby；Pci bus bridging connects main control module；Video Controller is even
Connect display.During work, instruct by main control computer by pci bus transmission to this module, solve through instruction
Parser resolves, sends into 2 samplings and image-forming module after SERDES encodes, and sampling is formed with image-forming module
It is direct that waveform image data send into Video Controller formation display image by MUX after being decoded by SERDES again
It is sent to display, is sent to main control computer through PCI Bridge simultaneously.
Main control computer, for strengthening oscillographic disposal ability and improving the ease for use of user, main control part is adopted
With the embedded computer system of x86 structure, using the Pentium-M of low-power consumption as primary processor, with
PC-104Plus bus compatible for PCI is as main control computer and the data communication bus of data exchange module.
Peripheral assembly includes keyboard, mouse, liquid crystal display, hard disk drive, CD drive etc., all
Directly can be supported by PC-1 04Plus board.The main process work of main control computer module includes:
(1) GUI(graphic user interface) and HMI(man-machine interaction) operation, respond customer incident, as turned
Dynamic panel runner, button press, mobile mouse, point touching screen etc., and make according to event control system
Response；
(2) read the various states of hardware system and judge according to state and operate；
(3) read Wave data and stored to hard disk drive；
(4) Wave data is carried out advanced analysis, including time-domain analysis, frequency-domain analysis, Time-Frequency Analysis with
And numeric field analysis etc.；
(5) run third party software and realize user-defined function.
Spectrum analysis module is as it is shown in figure 5, include attenuator, low pass filter, frequency mixer, intermediate frequency filtering
Device, analog-to-digital conversion module, data process and exchange system, variable local oscillator generator, and attenuator passes through low pass
Wave filter connects frequency mixer, frequency mixer passes sequentially through intermediate-frequency filter, analog-to-digital conversion module and data process and
Exchange system connects, and data process and exchange system feeds back to frequency mixer by variable local oscillator generator.
First accessing an attenuator in RF input signal, its pad value is stepping, completes gauge internal
Coordination, such as coupling, best operating point etc..Then signal is through low pass filter or preselector, stops
High-frequency signal arrives frequency mixer, prevents out of band signal to be mixed mutually with local oscillator and produces unnecessary frequency response at intermediate frequency,
Signal is through core component frequency mixer.Producing intermediate-freuqncy signal with frequency mixer, intermediate-frequency circuit uses digital intermediate frequency, number
Word intermediate frequency is swept wide fft analysis for narrow and sweep being used in combination of wide frequency sweep analysis for width, optimizes and sweeps
Retouch process so that measuring and can be completed as quickly as possible, intermediate-frequency bandwidth arranges the needs according to real work
Determine.Certainly it can affect other several factors, such as back noise, the distortion factor etc. of signal demodulation.
ADC digital IF intermediate-freuqncy signal, system performs all further steps in a digital manner.FFT calculates
Method realizes time domain to frequency domain transform, the subsequent analysis generation display picture such as spectrogram, code domain figure.Main number
Signal processing module.Simulation IF signal is through transmission band filtering and numeral conversion.Digital Down Convert and sampling
Process is converted into homophase (I) and orthogonal (Q) baseband signal streams A/D sampling point.Trigger module detection signal conditioning,
Control to gather and timing.Base band dsp system uses baseband I and Q signal and trigger message, by FFT, tune
The means such as system analysis, power measurement, Timing measurement and statistical analysis, carry out spectrum analysis.
Panel and outward appearance, device panel is made up of some regions.Very color TFT LCD occupies bigger
Area, lower section is provided with system interface district, lower left comprises on and off switch and USB baseplug, wherein
Long on and off switch of pressing can be with starter, then vice-minister is by then starting shutdown programm, and USB baseplug is the most permissible
Connect keyboard, mouse and mass memory unit etc.；Lower section tundish, containing four bnc connectors, respectively shows
4 input interfaces of ripple device, lower right has spectrum analysis RF input channel, includes on the right side of LCDs
Measure functional select switch district, shortcut and multi-functional regulation wheel district, the right side of device are provided with louvre and outer
Power interface.This device power consumption is less, and the free convection by louvre can meet radiating requirements completely；Outward
Connect power interface can be accessed by the DC source of 8～16V device is powered or to battery charge.The left side of device sets
Having SD/MMC card socket and expresscard slot, the former can be inserted into SD/MMC card as non-volatile memory medium,
The latter can be inserted into special function expansion card and realizes Function Extension and extension.
The behind of device is battery and communication interface.Lithium ion battery bag needed for device can be by electricity behind
Pond groove loads.The communication interface of lower section comprises 2 RS-232 serial line interfaces, can be used to connection standard serial ports and sets
Standby；1 USB device interface can be used to connect host computer and communicates；1 LAN interface can connection standard
Ethernet carries out data communication and remote control/remote measurement.
Man-machine interaction can be by following several approach:
1. panel-switch: panel-switch is the method for most convenient.
2. touch screen: have touch screen on this device liquid crystal display, can use stylus or finger click on and drag
Move various operation.This is a kind of mode of operation.
3. standard USB keyboard/mouse: this device compatibility standard USB keyboard and mouse, can be used to replace touching
Touch screen and panel-switch completes to select and input.Applying in stationary applica-tions, which is both convenient and quick.
4. built-in display: this is the main output mode of this device.Built-in display is that 12 TFT are the most color
LCD, display effect is clearly fine and smooth and brightness is higher.
5. remote data indicator: if applying and wish larger sized display in stationary applica-tions, then can be by dress
The VGA output port external-connection displayer of the side of postponing realizes.Remote data indicator and built-in display will show simultaneously
Test information.Requirement to remote data indicator is that it must support WVGA specification.
Claims (5)
1. a time domain and frequency domain synthesis test device, it is characterised in that include front end signal chain, sampling and imaging
Module, data exchange module, main control module, display and user interactive module, interface and expansion module,
Power module, spectrum analysis module, RF programmable conditioning module, front end signal chain is by sampling and imaging mould
Block and data exchange module communication, RF programmable conditioning module by spectrum analysis module and main control module communication,
Data exchange module respectively with main control module, display and user interactive module, interface and expansion module, electricity
Source module electrically connects；Wherein front end signal chain include permutator, impedance transducer, programmable attenuator,
Program control attenuation module, programme-controlled gain module, digital to analog converter, after analog input signal connects permutator
Processed by impedance transducer, programmable attenuator respectively, be connected with program control attenuation module by permutator,
Program control attenuation module electrically connects with programme-controlled gain module, digital to analog converter respectively with program control attenuation module, journey
Control gain module electrical connection.
Time domain the most according to claim 1 and frequency domain synthesis test device, it is characterised in that sampling and imaging
Module include double-channel analog/digital transducer, DDR2-SDRAM memory module, QDR2-SRAM memorizer,
Cryptographic protocol chip, FPGA module, double-channel analog/digital transducer, DDR2-SDRAM memory module,
QDR2-SRAM memorizer, cryptographic protocol chip electrically connect with FPGA module respectively.
Time domain the most according to claim 2 and frequency domain synthesis test device, it is characterised in that FPGA module bag
Include sampling controller, storage manager, high-speed figure fluorescence waveform imaging engine, stringization/deserializer, with
Machine number maker, encryption option manager, sampling controller is by storage manager and high-speed figure fluorescence
Waveform imaging engine electrically connect, high-speed figure fluorescence waveform imaging engine connect respectively stringization/deserializer,
QDR2-SRAM memorizer, waveform arithmetic processor, sampling controller connects trigger controller, storage tube
Reason device connects storage control, FFT engine, storage control and DDR2-SDRAM memory module respectively
Connecting, stringization/deserializer link order decoder, random number generator electrically connects with encryption option manager,
Encryption option manager electrically connects with cryptographic protocol chip.
Time domain the most according to claim 1 and frequency domain synthesis test device, it is characterised in that data interchange mode
Block include serialization/solution serial unit, data exchange unit, instruction parser, video and graph compound unit,
Pci bus bridge, serialization/solution serial unit electrically connects with data exchange unit, instruction parser respectively,
Data exchange unit, instruction parser electrically connect with pci bus bridge respectively, data exchange unit and video
Image superimposition unit electrically connects.
Time domain the most according to claim 1 and frequency domain synthesis test device, it is characterised in that spectrum analysis mould
Block includes at attenuator, low pass filter, frequency mixer, intermediate-frequency filter, analog-to-digital conversion module, data
Reason and exchange system, variable local oscillator generator, attenuator connects frequency mixer, mixing by low pass filter
Device passes sequentially through intermediate-frequency filter, analog-to-digital conversion module is connected, at data with data process and exchange system
Reason and exchange system feed back to frequency mixer by variable local oscillator generator.
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| CN103837739B true CN103837739B (en) | 2016-12-21 |
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| CN105629016A (en) * | 2014-10-29 | 2016-06-01 | 江苏绿扬电子仪器集团有限公司 | Oscilloscope sampling and imaging system |
| CN105548695A (en) * | 2014-11-03 | 2016-05-04 | 江苏绿扬电子仪器集团有限公司 | Realization system for microwave frequency channel |
| CN105699724B (en) * | 2016-03-25 | 2018-08-14 | 北华航天工业学院 | Long-range hybrid domain analog measurement instrument |
| CN110703127A (en) * | 2019-11-01 | 2020-01-17 | 中国人民解放军海军航空大学 | Airplane cable fault detection device and detection method thereof |
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| CN101504428A (en) * | 2009-03-19 | 2009-08-12 | 优利德科技（东莞）有限公司 | Electronic measurement method and multifunctional electronic measuring instrument |
| CN102062797A (en) * | 2009-11-17 | 2011-05-18 | 北京普源精电科技有限公司 | Oscilloscope with high-frequency path and low-frequency path separation circuit |
| CN102185639A (en) * | 2011-04-27 | 2011-09-14 | 中国电力科学研究院 | Characteristic analyzer used for low-voltage power line carrier wave channel |
| EP2434299A1 (en) * | 2010-09-28 | 2012-03-28 | Tektronix, Inc. | Multi-domain test and measurement instrument |
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| US9157943B2 (en) * | 2010-08-13 | 2015-10-13 | Tektronix, Inc. | Multi-channel frequency domain test and measurement instrument |
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| CN101504428A (en) * | 2009-03-19 | 2009-08-12 | 优利德科技（东莞）有限公司 | Electronic measurement method and multifunctional electronic measuring instrument |
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| EP2434299A1 (en) * | 2010-09-28 | 2012-03-28 | Tektronix, Inc. | Multi-domain test and measurement instrument |
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