CN107480057B - Method for realizing Call Stack function in ICE - Google Patents
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Abstract
The invention discloses a method for realizing Call Stack function in ICE, in the running process of the chip kernel, the method utilizes the Call Stack control module to monitor the Stack series register in the kernel, when the kernel Stack changes, the instruction counting register, the working register and the status register are synchronized to the FPGA global clock and then synchronously mapped to the kernel signal Stack in the Call Stack control module, the method can monitor the kernel Stack, and simultaneously can not affect the running of the kernel. The invention records the PC value when the Stack level changes in the program running process through the Call Stack function, thereby realizing that the lower computer monitors the CPU Stack.
Description
Technical Field
The invention belongs to the technical field of online simulators, and particularly relates to a method for increasing a CallStack function of a chip simulator.
Background
The stack of the core of the chip is changed under the conditions of function call exit, interrupt entry exit and the like. When a user uses the ICE to develop and debug the chip application program, if the ICE can record the change condition of the Stack and return the key registers of the kernels such as the PC, the IR, the WOEK, the STATUS and the like when the Stack is changed to a PC upper computer user, the user can check the running state of the chip kernel through a Call Stack window of the upper computer, thereby positioning and tracking the problem of chip Stack overflow caused by abnormal function Call, interrupt Call and the like in the program.
For example, patent application 201611020255.X discloses an ICE automation test system and a test method, the test system includes two major parts, an upper computer and a lower computer, the upper computer uses a script as a central console of the test system, the lower computer includes: DUT and TB test boards; and the upper computer and the lower computer communicate through an API (application program interface). The automatic test system and the test method can realize digital function tests of all ICE support models, reduce the input of test manpower, greatly reduce manual operation and greatly shorten the test flow. And moreover, the test log is automatically output, so that a tester can conveniently and quickly find problems, and then the chip design is repaired.
However, the patent application does not have the Call Stack function of the chip simulator, and cannot realize the function calling of the user program and the monitoring of the lower computer on the CPU Stack.
Disclosure of Invention
Therefore, the invention has the primary object of providing a method for realizing the Call Stack function in the ICE, which can record the PC value when the Stack number changes in the program running process through the Call Stack function, so as to realize that the lower computer monitors the CPU Stack.
The invention also aims to provide a method for realizing the Call Stack function in the ICE, which can start from the core at the bottom layer of the chip, increase the control of the monitoring circuit of the core and the communication circuit and the communication protocol for transmitting Stack data to the upper computer, has clear structure and good effect, and provides a reliable guarantee means for the user to develop the user program of the chip.
In order to achieve the purpose, the technical scheme of the invention is as follows:
a method for realizing Call Stack function in ICE is characterized in that in the running process of a chip kernel, a Call Stack control module is used for monitoring SP (Stack number register) in the kernel, when the kernel Stack changes, PC (instruction counting register), WORK (working register), STATUS (STATUS register) and the like are synchronized to an FPGA (field programmable gate array) global clock and then synchronously mapped to a kernel signal Stack in the Call Stack control module, and the method can monitor the kernel Stack and cannot influence the running of the kernel.
Further, the method specifically comprises the following steps: when the kernel presses the stack, synchronously pressing the stack; synchronously popping when the kernel pops; in the process, the Call Stack control module can record the Stack number, stop the change of the kernel signal Stack when the Stack overflows (including pressure Stack overflow and pop overflow), record the PC (personal computer) during overflow and return the PC to the upper computer for the user to locate at the code during Stack overflow.
The Call Stack control module comprises a kernel signal synchronization module, a kernel signal Stack module and a Stack reading control module, wherein the kernel signal synchronization module is connected to the kernel signal Stack module, the kernel signal Stack module is connected to the Stack reading control module, the Stack reading control module is controlled by the simulation module, and data in the Stack between responsibility is returned to the upper computer through the simulation module according to the protocol sequence.
The kernel signal synchronization module is used for leading out kernel key signals to the kernel signal synchronization module and then carrying out synchronization processing on the signals, and comprises the following processes:
(1) the stack change request signal generates:
under an FPGA global clock fclk, the kernel stack stage register SP is beat by one beat to generate SP _ r, and push (push) and pop (pop) signals can be generated through combinational logic judgment. When the SP becomes larger, a stack condition occurs, the number of the stack request levels is increased by one, and the stack requests are sequentially from push1 to push; when SP becomes smaller, pop occurs, and the pop request stage number is reduced by one, from pop to pop1 in sequence. When the SP stage reaches the top of the stack, only the stack can be popped, and if the stack is continuously pressed, a stack overflow request signal push _ ovfl is generated; when the SP series reaches the bottom of the stack, the stack can only be pushed, and if the stack is continuously popped, a pop overflow request signal pop _ ovfl is generated.
(2) Kernel critical signal delay:
in the subsequent stack processing module, the kernel key signals are sampled by using push 1-push and pop 1-pop requests, so that signals such as PC, WORK, STATUS (including but not limited to, kernel signals deemed necessary by other users can be monitored) in the kernel need to be subjected to delay hold processing, the relevant signals are beaten for two beats in fclk clock domain, and through the processing, the kernel clock can be synchronized if the kernel clock is asynchronous with the FPGA global clock.
The kernel signal stack module, when first level pushes request push1 is effective, pushes PC, WORK, STATUS on the first level stack, analogizes in turn, and when first level pushes request push is effective, pushes PC, WORK, STATUS on the nth level stack.
And when the nth pop request pop is valid, taking out the PC, the WORK and the STATUS from the nth stack, and repeating the steps, and when the 1 st pop request pop1 is valid, taking out the PC, the WORK and the STATUS from the 1 st stack.
Pressing the stack from the bottom of the stack to the top of the stack; and popping from the stack top to the stack bottom.
Adding a stack overflow field recording function, when the stack number reaches the bottom of the first-stage stack, if the SP continues to pop and the pop _ ovfl request is valid, pressing the PC, the WORK and the STATUS into the (n + 1) th-stage stack, protecting the whole stack, and not allowing stack change any more so as to record a pop field; when the stack level reaches the top of the nth stack, if the SP continues to push the stack and the push _ ovfl request is valid, the PC, the WORK and the STATUS are pushed to the (n + 2) th stack, the whole stack is protected, stack change is not allowed any more, and the situation that the stack is pushed to overflow is recorded.
A stack read control module: in order to cooperate with the original communication protocol of ICE, a stack reading control module is added, and the module is specifically used for finishing operations such as the order and bit width arrangement of stack data transmission, the increase of a packet head and a packet tail and the like.
The invention can realize that the lower computer monitors the CPU stack in the ICE simulation process, records the PC value when the stack level changes in the program running process, and sends the PC value to the upper computer after single step, breakpoint and the like stop, and the user can quickly position the code position of stack change caused by CALL, RETURN, interruption and the like through the display of the upper computer, thereby being capable of quickly finding out abnormal jump of the program.
The method comprises the steps of recording and reporting stack overflow errors, wherein the stack overflow errors comprise PUSH (PUSH stack) overflow and POP (POP stack) overflow, returning a PC (personal computer) when a stack overflows to an upper computer, directly positioning a code when the stack overflows by a user, quickly positioning the stack overflow errors, and recording values of various key special function registers such as return kernel WORK, STATUS and other registers such as interrupt control, SRAM control, FLASH control and peripheral control when the stack changes according to requirements, so that the user can master the environment field of chip operation when the stack changes, and the problem encountered in the debugging process of the user can be positioned.
The Call Stack function is equivalent to transparentizing the process of the ICE running at full speed, a user can check the running process record of the program when the breakpoint (including the data breakpoint) stops, whether the jump of the program is expected or not and whether the change of the Stack is abnormal or not are quickly judged, the means of debugging the program by the user is expanded, the running of the CPU is more transparent and traceable, the program jumping and interruption process is clearer, and the method has great significance for debugging large and complex programs by the user.
Drawings
Fig. 1 is a block diagram of the overall architecture of Call Stack implemented by the present invention.
FIG. 2 is a block diagram of a stack change request signal generation implemented by the present invention.
FIG. 3 is a circuit diagram of a core key signal synchronization implementation circuit implemented by the present invention.
Fig. 4 is a stack architecture diagram implemented by the present invention.
FIG. 5 is a flow chart of stack reading implemented by the present invention.
Fig. 6 is a stack architecture diagram of one specific implementation in which the present invention is implemented.
Fig. 7 is a diagram of a Call Stack packet architecture implemented in fig. 6.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
A method for realizing Call Stack function in ICE is characterized in that in the running process of a chip kernel, a Call Stack control module is used for monitoring SP (Stack level register) in the kernel, when the kernel Stack changes, PC (instruction counting register), WORK (working register), STATUS (STATUS register) and the like are synchronized to an FPGA (field programmable gate array) global clock and then synchronously mapped to a kernel signal Stack in the Call Stack control module.
Further, the method specifically comprises the following steps: when the kernel presses the stack, synchronously pressing the stack; synchronously popping when the kernel pops; in the process, the Call Stack control module can record the Stack number, stop the change of the kernel signal Stack when the Stack overflows (including pressure Stack overflow and pop overflow), record the PC (personal computer) during overflow and return the PC to the upper computer for the user to locate at the code during Stack overflow.
The Call Stack control module comprises a kernel signal synchronization module, a kernel signal Stack module and a Stack reading control module, wherein the kernel signal synchronization module is connected to the kernel signal Stack module, the kernel signal Stack module is connected to the Stack reading control module, the Stack reading control module is controlled by the simulation module, and data in the Stack between responsibility is returned to the upper computer through the simulation module according to the protocol sequence.
The kernel signal synchronization module is configured to extract kernel key signals to the kernel signal synchronization module, and then perform synchronization processing on the signals, as shown in fig. 2, including the following processes:
(1) the stack change request signal generates:
under an FPGA global clock fclk, the kernel stack stage register SP is beat by one beat to generate SP _ r, and push (push) and pop (pop) signals can be generated through combinational logic judgment. When the SP becomes larger, a stack condition occurs, the number of the stack request levels is increased by one, and the stack requests are sequentially from push1 to push; when SP becomes smaller, pop occurs, and the pop request stage number is reduced by one, from pop to pop1 in sequence. When the SP stage reaches the top of the stack, only the stack can be popped, and if the stack is continuously pressed, a stack overflow request signal push _ ovfl is generated; when the SP series reaches the bottom of the stack, the stack can only be pushed, and if the stack is continuously popped, a pop overflow request signal pop _ ovfl is generated.
(2) Kernel critical signal delay:
as shown in fig. 3, in the subsequent stack processing module, the kernel key signals are sampled by using push 1-push and pop 1-pop requests, so that signals such as PC, WORK, STATUS (including but not limited to, all kernel signals deemed necessary by other users can be monitored) in the kernel need to be delayed and held, the relevant signals are processed for two beats in fclk clock domain, and through this process, the kernel clock can be synchronized if the kernel clock is asynchronous with the FPGA global clock.
Kernel signal stack module:
when the first-stage stack pressing request push1 is effective, the first-stage stack is pressed by PC, WORK and STATUS, and the analogy is repeated, and when the first-stage stack pressing request push is effective, the nth-stage stack is pressed by PC, WORK and STATUS.
And when the nth pop request pop is valid, taking out the PC, the WORK and the STATUS from the nth stack, and repeating the steps, and when the 1 st pop request pop1 is valid, taking out the PC, the WORK and the STATUS from the 1 st stack.
Pressing the stack from the bottom of the stack to the top of the stack; and popping from the stack top to the stack bottom.
Adding a stack overflow field recording function, when the stack number reaches the bottom of the first-stage stack, if the SP continues to pop and the pop _ ovfl request is valid, pressing the PC, the WORK and the STATUS into the (n + 1) th-stage stack, protecting the whole stack, and not allowing stack change any more so as to record a pop field; when the stack level reaches the top of the nth stack, if the SP continues to push the stack and the push _ ovfl request is valid, pressing the PC, the WORK and the STATUS into the (n + 2) th stack, protecting the whole stack, and not allowing stack change any more so as to record that the stack is pushed to overflow a site; as shown in fig. 4.
A stack read control module: in order to cooperate with the original communication protocol of ICE, a stack reading control module is added, and the module is specifically used for finishing operations such as the order and bit width arrangement of stack data transmission, the increase of a packet head and a packet tail and the like. FIG. 5 shows the basic flow of stack reads.
Fig. 6 and 7 are diagrams of a Stack structure and a Call Stack packet structure used in a mode of implementing the present invention. In this embodiment, the PC bit width of the chip core is 16bit, the SP stack number is 8, and the communication unit is 1Byte (8 bit).
As shown in fig. 6, in order to match the bit width of the communication unit, the PC is divided into two parts, i.e., an upper eight bit part and a lower eight bit part for pressing.
In the communication control module, a Call Stack data packet is generated first, and as shown in fig. 7, the Call Stack data packet is sent to the upper computer through the ICE original communication path.
Wherein, in the Call Stack data packet:
1. the whole data packet is 256 bytes, unused bits are used as reserved bits for subsequent expansion, and the value of the reserved bits is 0 xFF.
2. The stack corresponds to the stage number without pressing the stack, and the upper eight bits and the lower eight bits of the PC are both 0 xFF.
3. The stack has no overflow, and the ninth and tenth stages PC have 0xFF in both the eight upper and eight lower bits.
4. If the stack overflows, the PC in the overflow process is respectively pushed into the ninth-level stack or the tenth-level stack according to the stack popping overflow or stack pushing overflow, the whole stack is protected, the stack can not be pushed and popped, and the stack site in the overflow process is recorded.
5. The upper computer judges whether the stack overflows or not according to the data of the ninth and tenth levels of stacks (if the two levels of stack data are not 0xFF, the stack overflows), and tells the user that the stack overflows abnormally through popup window printing information.
6. And finally, the 4Byte sequentially sends 0xA5, 0x5A, 0xBA and 0xFF as the Trace Buffer and Call Stack data packet marks.
Therefore, the invention can realize that the lower computer monitors the CPU stack in the ICE simulation process, records the PC value when the stack level changes in the program running process, and sends the PC value to the upper computer after single step, breakpoint and the like stop, and the user can quickly position the code position of stack change caused by CALL, RETURN, interruption and the like through the display of the upper computer, thereby being capable of quickly finding the abnormal jump of the program.
The method comprises the steps of recording and reporting stack overflow errors, wherein the stack overflow errors comprise PUSH (PUSH stack) overflow and POP (POP stack) overflow, returning a PC (personal computer) when a stack overflows to an upper computer, directly positioning a code when the stack overflows by a user, quickly positioning the stack overflow errors, and recording values of various key special function registers such as return kernel WORK, STATUS and other registers such as interrupt control, SRAM control, FLASH control and peripheral control when the stack changes according to requirements, so that the user can master the environment field of chip operation when the stack changes, and the problem encountered in the debugging process of the user can be positioned.
The Call Stack function is equivalent to transparentizing the process of the ICE running at full speed, a user can check the running process record of the program when the breakpoint (including the data breakpoint) stops, whether the jump of the program is expected or not and whether the change of the Stack is abnormal or not are quickly judged, the means of debugging the program by the user is expanded, the running of the CPU is more transparent and traceable, the program jumping and interruption process is clearer, and the method has great significance for debugging large and complex programs by the user.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
Claims (6)
1. A method for realizing Call Stack function in ICE is characterized in that in the running process of a chip kernel, a Call Stack control module is used for monitoring a Stack stage register in the kernel, when the kernel Stack is changed, an instruction counting register, a working register and a state register are synchronously mapped to a kernel signal Stack in the Call Stack control module after being synchronized to an FPGA global clock;
the synchronous mapping specifically comprises: when the kernel presses the stack, synchronously pressing the stack; synchronously popping when the kernel pops; in the process, the Call Stack control module can record the Stack number, stop the change of the kernel signal Stack when the Stack overflows, record the PC when the Stack overflows, and return the PC to the upper computer for the user to position the code when the Stack overflows.
2. A method as claimed in claim 1, wherein the Call Stack control module includes a kernel signal synchronization module, a kernel signal Stack module and a Stack reading control module, the kernel signal synchronization module is connected to the kernel signal Stack module, the kernel signal Stack module is connected to the Stack reading control module, the Stack reading control module is controlled by the simulation module, and data in the Stack between responsibility is returned to the upper computer through the simulation module according to the protocol sequence.
3. The method according to claim 2 for implementing Call Stack function in ICE, wherein the kernel signal synchronization module is used for synchronously processing key kernel signals after the key kernel signals are led out to the kernel signal synchronization module, and the method comprises the following steps:
(1) the stack change request signal generates:
beating the kernel stack stage register SP for one beat to generate SP _ r under an FPGA global clock fclk, and generating push and pop signals through combinational logic judgment; when the SP becomes larger, a stack condition occurs, the number of the stack request levels is increased by one, and the stack requests are sequentially from push1 to push; when SP becomes smaller, pop occurs, the pop request stage number is reduced by one, and pop is carried out from pop to pop1 in sequence; when the SP stage reaches the top of the stack, only the stack can be popped, and if the stack is continuously pressed, a stack overflow request signal push _ ovfl is generated; when the SP stage number reaches the stack bottom, only the stack can be pushed, and if the stack is continuously popped, a pop overflow request signal pop _ ovfl is generated;
(2) kernel critical signal delay:
in the subsequent stack processing module, the kernel key signals are sampled by using push 1-push and pop 1-pop requests, so that the delay hold processing needs to be performed on the PC, WORK, and STATUS signals in the kernel, and the relevant signals are processed by two beats in fclk clock domain, so that the kernel clock can be synchronized if the kernel clock is asynchronous with the FPGA global clock.
4. The method as claimed in claim 2, wherein the kernel signal stacking module, when the first-stage Stack request push1 is valid, pushes the first-stage stacks of PC, WORK and STATUS, and so on, and when the first-stage Stack request push is valid, pushes the nth-stage stacks of PC, WORK and STATUS;
when the nth pop request pop is valid, taking out the PC, the WORK and the STATUS from the nth stack, and so on, and when the 1 st pop request pop1 is valid, taking out the PC, the WORK and the STATUS from the 1 st stack;
pressing the stack from the bottom of the stack to the top of the stack; and popping from the stack top to the stack bottom.
5. A method for implementing Call Stack function in ICE according to claim 4, wherein when the Stack number has reached the bottom of the first Stack at this time, if SP continues to pop, pop _ ovfl request is valid, then PC, WORK, STATUS are pushed to the Stack of the (n + 1) th level, and the whole Stack is protected, Stack change is not allowed any more, to record the pop overflow field; when the stack level reaches the top of the nth stack, if the SP continues to push the stack and the push _ ovfl request is valid, the PC, the WORK and the STATUS are pushed to the (n + 2) th stack, the whole stack is protected, stack change is not allowed any more, and the situation that the stack is pushed to overflow is recorded.
6. The method for implementing Call Stack function in ICE as claimed in claim 2, wherein the Stack reading control module is used for completing the operations of sending sequence of Stack data, arranging bit width, and adding packet head and packet tail.
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| US5134701A (en) * | 1989-02-10 | 1992-07-28 | Hewlett-Packard Co. | Test apparatus performing runtime replacement of program instructions with breakpoint instructions for processor having multiple instruction fetch capabilities |
| CN106649101A (en) * | 2016-11-18 | 2017-05-10 | 芯海科技（深圳）股份有限公司 | ICE automated test system and test method |
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| CN102866982A (en) * | 2012-09-14 | 2013-01-09 | 复旦大学 | Eight-bit complex instruction set central processor based on FPGA (Field Programmable Gata Array) |
| CN102841563B (en) * | 2012-09-26 | 2015-05-13 | 苏州工业园区职业技术学院 | Four-axis high speed dispensing robot servo-control system |
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| US5134701A (en) * | 1989-02-10 | 1992-07-28 | Hewlett-Packard Co. | Test apparatus performing runtime replacement of program instructions with breakpoint instructions for processor having multiple instruction fetch capabilities |
| CN106649101A (en) * | 2016-11-18 | 2017-05-10 | 芯海科技（深圳）股份有限公司 | ICE automated test system and test method |
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