CN101995546B - Automatic test system and method of programmable logic device on basis of boundary scan - Google Patents

Automatic test system and method of programmable logic device on basis of boundary scan Download PDF

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CN101995546B
CN101995546B CN 201010545055 CN201010545055A CN101995546B CN 101995546 B CN101995546 B CN 101995546B CN 201010545055 CN201010545055 CN 201010545055 CN 201010545055 A CN201010545055 A CN 201010545055A CN 101995546 B CN101995546 B CN 101995546B
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device
test
scan
system
boundary
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CN101995546A (en )
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王伶俐
王颖
周学功
童家榕
包杰
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复旦大学
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本发明属于电子技术领域,具体为一种基于边界扫描的可编程逻辑器件自动测试系统与方法。 The present invention belongs to the field of electronic technology, in particular to a programmable logic device based on a boundary scan test system and method automatically. 所述测试方法包括芯片配置文件的生成、下载配置FPGA芯片、测试向量的生成和加载,以及测试结果比较等,并构建了相应的测试系统,全部实现自动化。 The testing method comprising profile generation chip, FPGA chip download configuration, test vector generation and load, and comparing the test results and the like, and build the corresponding test system, fully automated. 本发明由软件自动生成用户待测项目的测试向量,结合JTAG自动下载测试软件实现对用户电路的硬件功能在线测试。 Automatic generation of test vectors of the present invention, the user program to be tested by the software, in conjunction with JTAG testing software for automatic download function hardware subscriber circuit line test. 使用脚本化测试环境,使得一系列繁琐的人工测试操作转化为全自动的软件流程,大大提升测试的速度和准确性。 Scripted testing environment, making a series of tedious manual test operations into a fully automated software process, greatly enhance the speed and accuracy of the test.

Description

基于边界扫描的可编程逻辑器件自动测试系统与方法 Programmable logic devices boundary scan test system and method based on automatic

技术领域 FIELD

[0001] 本发明属于电子技术领域,具体涉及一种可编程器件的自动测试方法。 [0001] The present invention belongs to the field of electronic technology, particularly relates to a method for automatic testing programmable devices.

背景技术 Background technique

[0002] 现场可编程门阵列(Field Programmable Gate Array, FPGA),它是在可编程阵列逻辑(Programmable Array Logic, PAL)、通用阵列逻辑(Generic Array Logic, GAL)、复杂可编程逻辑器件(Complex Programmable Logic Device, CPLD)等可编程器件的基础上进一步发展的产物。 [0002] FPGA (Field Programmable Gate Array, FPGA), which is a programmable array logic (Programmable Array Logic, PAL), Generic Array Logic (Generic Array Logic, GAL), complex programmable logic devices (Complex programmable Logic device, CPLD), etc. was further development based on programmable devices. 它最初作为专用集成电路(Application Specific IntegratedCircuit, ASIC)原型功能验证的途径而出现,既解决了定制电路的不足,又克服了原有可编程器件门电路数有限的缺点。 It was originally used as application specific integrated circuits (Application Specific IntegratedCircuit, ASIC) prototyping and functional verification approach appears not only solve the lack of custom circuits, and overcomes the limited number of original gates of programmable devices disadvantages. [0003] 由于FPGA设计周期短,上市时间快,非重复工程费用(Non-RecursiveEngineering, NRE)低的特点,加之具有动态可重配置的特性,因而在民用通信、消费类电子产品、汽车、医疗等领域中获得了广泛的应用。 [0003] Due to the short FPGA design cycles, faster time to market, non-recurring engineering costs (Non-RecursiveEngineering, NRE) low characteristics, combined with a characteristic dynamically reconfigurable, so in civilian communications, consumer electronics, automotive, medical and other areas of access to a wide range of applications.

[0004] 然而随着FPGA芯片复杂性与密度的爆发式增长,芯片测试面对的挑战也越来越大。 [0004] However, with the FPGA chip complexity and density of explosive growth, the challenges facing the test chip is also growing. 传统的测试方法是将芯片置于特制的开发母板上,将位流文件下载到芯片中,然后通过信号发生器产生指定的输入信号,作用于芯片上的端口,再通过示波器探针或者母版为芯片外接的LED灯等观察各输出引脚的信号是否符合预期,人工判断位流文件的正确性。 The conventional test method is a special development of the chip on the motherboard, the bit stream file downloaded to the chip, and then generates an input signal specified by the signal generator, applied to the port on the chip, and then by an oscilloscope probe or female Version for the external LED lamp to observe the output pin signal is as expected, human judgment accuracy bit stream file. 这种方法效率很低,不可能做批量测试,只能粗略观察有限个输出引脚的信号变化情况,且很容易发生人为错误。 This method is inefficient, it is impossible to do batch test, the observed signal changes can only be roughly limited output pins, and it is prone to human error.

[0005] 第二种测试方法是使用商业的在线调试软件,如Altera公司的SignalTap和Xilinx公司的ChipScope等。 [0005] The second test method is to use a commercial online debugging software, such as Altera's and Xilinx's ChipScope SignalTap so on. 此类调试软件一般和出品公司的设计软件配套使用,能够捕获和显示芯片系统中实时信号的状态[I],但这些调试软件只支持自己公司生产的芯片,整个流程也必须在相应的配套设计软件中进行。 Such software is generally commissioning and production company supporting the use of design software, to capture and display real-time signal chip system status [I], but these debugger software only supports the company's own chip, the entire process must also be appropriate in supporting the design in software. 这种方法通用性不高,不能用于测试自己设计的FPGA芯片和自主的设计软件流程。 This approach is not high versatility, can not be used to test their own design FPGA chip design software and autonomous process.

[0006] 第三种方法是使用商业的测试系统,如安捷伦科技公司的Agilent 93000 PinScale测试机[2]。 [0006] The third method is using a commercial test system, such as Agilent Technologies Agilent 93000 PinScale testing machine [2]. 这种方法具有高通用性、高准确性,但其相应的配套软件较为复杂,学习成本较高,且配套硬件价格极为昂贵,不符合以较低成本进行快速测试的要求。 This method has high versatility, high accuracy, but its corresponding supporting software is more complex, higher cost of learning, and supporting hardware price is extremely expensive, does not meet the requirements for rapid testing at a lower cost.

[0007] 为了克服以上方法的种种缺点,本发明实现了一种基于JTAG( Joint Test ActionGroup) [3]边界扫描技术的自动下载测试方法,满足了快速、准确的批量化测试要求。 [0007] In order to overcome the shortcomings of the above method, the present invention realizes a [3] The method of automatically downloaded Boundary Scan Test JTAG (Joint Test ActionGroup) based on, for fast and accurate mass testing requirements.

[0008] 参考文献 [0008] Reference

[0009] [I]Altera, “Design Debugging Using the SignalTap II Embedded LogicAnalyzer”, 2009 ; [0009] [I] Altera, "Design Debugging Using the SignalTap II Embedded LogicAnalyzer", 2009;

[0010] [2]Verigy, V93000 Technical Documentation Center, “Verigy V93000SmarTest 6.5.3 Help Documentation,,,2010 ; [0010] [2] Verigy, V93000 Technical Documentation Center, "Verigy V93000SmarTest 6.5.3 Help Documentation ,,, 2010;

[0011] [3] IEEE Standards, Piscataway, NJ , “ANSI/IEEE Std 1149. 1-1990Standard Test Access Port and Boundary-Scan Architecture,,, 1993。发明内容 [0011] [3] IEEE Standards, Piscataway, NJ, "ANSI / IEEE Std 1149. 1-1990Standard Test Access Port and Boundary-Scan Architecture ,,, 1993. SUMMARY OF THE INVENTION

[0012] 本发明的目的在于提供一种能满足快速、准确的批量化测试要求,且学习成本低的可编程逻辑器件自动测试系统和方法。 [0012] The object of the present invention is to provide a satisfying rapid and accurate mass test requirements, and low cost programmable logic devices automatic test systems and methods of learning.

[0013] 本发明提供的可编程逻辑器件自动测试方法,是一种基于JTAG (Joint TestAction Group)[3]边界扫描技术的自动下载测试方法。 [0013] The automatic testing method of the present invention provides a programmable logic device, is a testing method automatically downloaded JTAG (Joint TestAction Group) [3] Based on boundary-scan technology. 具体包括芯片配置文件的生成、下载配置FPGA芯片、测试向量的生成和加载,以及测试结果比较等,并构建了相应的测试系统,全部实现自动化,方便用户对设计电路进行硬件仿真,大大提高测试的效率和准确性。 Specifically includes generation chip configuration file, download configuration FPGA chip, generating and loading of test vectors, and test results of the comparison and the like, and build the corresponding test system, fully automated, user-friendly design of circuit hardware emulation greatly improved test efficiency and accuracy. 具体介绍如下: Detailed below:

[0014] I.基于JTAG边界扫描技术 [0014] I.-based JTAG boundary scan

[0015] JTAG测试方法提供了非常高的测试覆盖率,同时无论如何复杂的电路只需要简单的4个端口(如果包含异步重置信号TRST则为5个端口)即可实现测试,该接口又被称作TAP (Test Access Port),这种方案大大减轻了芯片没有足够物理地址用于访问的问题。 [0015] The JTAG test method provides a very high test coverage, while in any case a complicated circuit requires only a simple four ports (asynchronous reset signal TRST, if included, compared with 5 ports) test can be realized, and this interface is called TAP (Test access Port), this approach greatly reduces the chip does not have enough physical address to access problems. 这些TAP端口分别为:测试时钟TCK (输入)、测试方式选择TMS (输入)、串行测试数据输入TDI (输入)、串行测试数据输出TDO (输出)。 The TAP ports are: the TCK test clock (input), test mode select TMS (input), a serial test data input TDI (input), the TDO serial test data output (output).

[0016] JTAG测试的核心部分是TAP控制器,其作用是将串行输入的TMS信号进行译码,使边界扫描系统进入相应的工作模式,并产生该模式下所需要的各个控制信号。 [0016] is the core of the TAP controller JTAG test, its role is to TMS serial input signal for decoding the boundary scan system into the appropriate mode, and generating respective control signals required for this mode. 在IEEEl 149. I标准中,对TMS输入序列和TAP控制器的译码状态给出了如图I所示的状态图,箭头边上的O或I数字表示TMS的值。 In IEEEl 149. I standard, the input decoding of TMS and the TAP controller state sequence given in Figure I a state as shown, the edge of the arrows I O or digital representation of the value of TMS.

[0017] 系统上电后,TAP控制器进入复位(Test-Logic-Reset)状态,首先要设置JTAG的工作模式,为此需要更新指令寄存器,具体状态转换流程如下:“空闲”(Run-Test/Idle),“选择数据寄存器”(Select-DR-Scan),“选择指令寄存器”(Select-IR-Scan),“捕获指令”(Capture-IR),“指令移位”(Shift_IR),“结束I”(Exitl-IR),“指令生效” (Update-IR),最后回到“空闲”状态。 [0017] After the power system, the TAP controller enters the reset (Test-Logic-Reset) state, the first to set the operating mode for JTAG instruction register for this purpose needs to be updated, the specific state transition process is as follows: "Idle" (Run-Test / Idle), "select data register" (select-DR-Scan), "select instruction register" (select-IR-Scan), "capturing order" (capture-IR), "the instruction shift" (Shift_IR), " end I "(Exitl-IR)," the effective date "(Update-IR), and finally return to the" idle "state. 在上述过程中的“捕获指令”状态,旧的指令数据被加载到指令寄存器当中;然后进入到“指令移位”状态,在该状态下,通过TCK的驱动,可以将一条新的特定指令推送到指令寄存器当中去;再到“指令生效”状态,刚才输入到指令寄存器中的指令将被译码并使指令正式生效,指定TDI、TD0端口与特定的数据寄存器相连接(如图2所示);最后,进入到“空闲”状态,等待下一轮控制流程。 In the above-described process of "capturing order" state, the old instruction data is loaded into the instruction register them; and then proceeds to "shift instruction" state, in this state, by driving TCK may be a new push particular instruction which go to the instruction register; then "command active" state, just entered into the instruction register instruction is decoded and instruction into effect, specify TDI, TD0 to a particular port is connected to the data register (shown in Figure 2 ); Finally, go to the "idle" state, waiting for the next round of the flow of control.

[0018] 图2所示的即为测试数据寄存器组,主要包括边界扫描寄存器(BoundaryScan Register),旁路寄存器(Bypass Register),器件标识寄存器(IdentificationRegister),配置寄存器(Config Register)以及指令寄存器(Instruction Register)。 Is the test data register group shown in [0018] FIG 2, including boundary scan register (BoundaryScan Register), a bypass register (Bypass Register), Device Identification (IdentificationRegister), the configuration register (Config Register) and an instruction register ( Instruction Register). 边界扫描寄存器是边界扫描测试中最重要的工作寄存器,它完成测试向量的输入,输出锁存和移位等测试必需的操作(图2外围一圈寄存器即为边界扫描寄存器);旁路寄存器其实就是一个一位寄存器,它将该芯片的边界扫描链短路起来,主要用于多芯片串联测试,也可用于测试JTAG的基本功能是否正常;器件标识寄存器是一个32位的标准寄存器,其内容包含该芯片的版本号、器件型号、制造厂商等信息,可用于测试芯片是否工作正常;配置寄存器主要用于芯片的配置下载和回读,它作为32位总线数据的缓冲器,用来实现配置时的串并转换和回读时的并串转换;指令寄存器即用来选择工作模式的寄存器,根据特定的指令码选择上述的测试数据寄存器组之一连接在TDI和TDO之间。 Boundary scan register is the boundary scan test of the most important working register, which complete the input test vectors, such as testing the output latch and shift operations necessary (FIG. 2 registers outer circle is the boundary scan register); bypass register fact a is a register, which short-circuit the chip boundary scan chain together, is mainly used for multi-chip test series, the basic functions can also be used to test whether the normal JTAG; device identification is a standard 32-bit register, the contents of which comprising when downloading the configuration register used to configure the chip and read back as data bus buffer 32, used for configuration; version number of the chip, device type, manufacturer and other information, it can be used to test whether the chip is working properly the serial to parallel conversion and parallel-serial conversion during readback; instruction register is used to select the operation mode register, selecting one of the sets of test data registers connected between the TDI and TDO according to the particular script. [0019] 要访问由特定指令选定的数据寄存器,仍需要以“空闲”为起点,依次进入“选择数据寄存器”,“捕获数据”(Capture-DR),“数据移位”(Shift-DR),“结束I” (Exitl-DR),“数据生效”(Update-DR),最后回到“空闲”状态。 [0019] To access a specific instruction selected by the data register, still need to be "idle" as a starting point, turn into the "selected data register", "Data Capture" (Capture-DR), "shift data" (Shift-DR ), "end I" (Exitl-DR), "data entry into force" (Update-DR), and finally return to the "idle" state. 以选择了边界扫描寄存器链路为例,在上述过程中的“捕获数据”状态,当前的芯片管脚输出状态数据被捕获至数据寄存器中;然后进入到“数据移位”状态,在该状态下,通过TCK的驱动,可以将一条新的测试向量数据推送到数据寄存器当中去,同时旧的管脚输出状态数据从TDO端口输出;再到“数据生效”状态,刚才输入到数据寄存器中的测试向量将通过锁存器正式加载到芯片管脚上;最后,回到“空闲”状态,完成一轮对测试向量的加载。 Boundary scan register to the selected link, for example, in the above-described process of "capture data" state, the output current of the chip pins state data is captured to the data register; and then proceeds to "shift data" state, in this state, next, by driving TCK, a new test can be pushed to the data register vector data to them, and the old state data output pin is output from the TDO port; then "data active" state, just entered into the data register the official test vectors loaded onto the chip pins through the latch; and finally, return to the "idle" state, a complete load of test vectors.

[0020] 2.基于JTAG的可编程逻辑器件自动测试系统 [0020] 2. Based on the JTAG programmable logic device of the automatic test system

[0021] 为了实现上述的自动测试方法,本发明首先提出了一套用于自动测试的系统。 [0021] To achieve the above automatic testing method, the present invention firstly proposes a system for automated testing. 系统组成如图3所示,分为硬件和软件两大部分:硬件部分包括用于运行自动测试软件的计算机,以及待测的可编程芯片测试板;软件部分包括编译软件、测试向量生成器、串口控制软件以及将它们整合在一起的回归测试系统。 The system components shown in Figure 3, hardware and software is divided into two parts: the hardware includes a computer software run automated tests, and the test chip programmable test board; Compiler software portion comprises test vector generator, serial control software, and integrates them regression test system. 其中: [0022] 所述编译软件,与待测的芯片相配套,它用于将用户的项目工程文件编译成芯片配置文件,该文件下载至FPGA芯片便能将芯片配置成用户所需要的功能。 Wherein: [0022] The compiler software, with a test chip matching, which is used to compile the user's project file to a chip configuration file downloaded to the FPGA chip die is configured to be able to function desired by the user .

[0023] 所述测试向量生成器,使用Perl脚本语言编写,它通过在命令行环境下调用传统的仿真软件(ModelSim工具)对用户的待测设计进行仿真,并将仿真后生成的波形记录文件转换成所需要的测试向量格式。 [0023] The test vector generator, using Perl script language, which is designed to simulate the user by calling a conventional test simulation software (the ModelSim tool) at the command line environment, and after the simulation to generate the waveform record file converted into the desired test vector format. 通过这种方式,可以准确无误地生成各种项目的测试向量,测试向量的覆盖率也能得到有效保证。 In this way, test vectors can be generated accurately projects the coverage of test vectors can be effectively guaranteed.

[0024] 所述串口控制软件,使用C++语言编写,它使用Windows XP操作系统提供的通用链接库控制串口,使其按一定格式发送和接收数据。 [0024] The serial port control software, using C ++ language, it uses the common link library Windows XP operating system provides control of serial port, it sends and receives data in a certain format. 由于JTAG的TAP端口共有4个,分别为TCK、TMS、TDI、TD0,而串口输出的数据共有8位,我们规定对应关系如下: Since the total JTAG TAP port 4, respectively, TCK, TMS, TDI, TD0, and the serial data output from the total of eight, we predetermined correspondence is as follows:

[0025] [0025]

Figure CN101995546BD00061

[0026] 所述回归测试系统,使用平台无关的TCL脚本语言实现,可以无缝地调用上述所有测试子系统。 [0026] The regression test system, using a platform-independent scripting language TCL, seamlessly call all the above tests subsystems. 通过建立回归测试策略,方便用户进行多版本的系统测试,以确认各个版本的修改没有引入新的错误或导致其他代码产生错误。 Through the establishment of regression testing strategy, user-friendly version of the multi-system testing to confirm the various versions of the modification does not introduce new bugs or cause other code to generate an error. 自动回归测试将大幅降低系统测试、维护升级等阶段的成本。 Automated regression testing will significantly reduce system testing, maintenance costs and upgrading phase.

[0027] 3.基于JTAG的可编程逻辑器件自动测试方法 [0027] 3. A JTAG programmable logic device based on the automatic testing method

[0028] 为了完成全自动化测试的目的,本发明的具体步骤如下(如图4所示): [0028] In order to accomplish the purpose of fully automated testing, the specific steps of the present invention are as follows (see Figure 4):

[0029] (I).使用TCL脚本环境自动调用用于生成一系列准备文件的Perl脚本。 [0029] (I). Using the TCL scripting environment automatically calls used to generate a series of preparatory documents of Perl scripts. 该脚本会调用编译软件将用户的项目源程序编译成用于下载配置FPGA芯片的位流文件;同时调用测试向量生成器生成规定格式的测试向量文件。 The script calls the user's software will compile project compile the source code into a bit stream file is used to download the configuration of the FPGA chip; at the same time invoke the test pattern generator generates test vectors specified file format.

[0030] (2).将PC的串口连接至FPGA的JTAG测试端口(TAP),运行串口控制软件控制芯片的JTAG端口,改变其TAP控制器的状态,使之分别运行以下几个测试模式: . [0030] (2) connected to the PC's serial port to the FPGA JTAG test port (TAP), control software running serial chip JTAG port, change the TAP controller state so as to run several test modes are:

[0031] a)测试旁路。 [0031] a) Test bypass. 发送Bypass指令,该指令将旁路寄存器连接至TDI和TDO端口之间,用于测试JTAG是否正常工作。 Bypass sending instructions to the bypass register is connected between TDI and TDO ports for JTAG test is working properly.

[0032] 具体过程为:先控制JTAG状态机进入“指令移位”状态,发送Bypass指令码(测试芯片中为“1111”),再控制状态机进入“数据移位”状态,输入固定的一组数据,再读出TDO的输出,并用软件方法检查输入与输出结果是否一致。 [0032] The specific process is: first controlling JTAG state machine enters "instruction shift" state, the transmission Bypass script (test chip "1111"), then the control state machine enters the "shift data" state, a fixed input sets of data, read out of the TDO output, and is consistent with the input and output software method of checking the result. 如果两组数据一致则表明JTAG正常工作。 If the two sets of data indicates that the JTAG consistent work.

[0033] b)测试标识码。 [0033] b) the test code. 发送IDCode指令,该指令将器件标识寄存器连接至TDI和TDO端口之间,用于测试芯片是否正常工作。 IDCode transmitting instructions to the connecting means identifies registers between TDI and TDO port, for testing the chip is working properly.

[0034] 具体过程为:先控制JTAG状态机进入“指令移位”状态,发送IDCode指令码(测试芯片中为“ 1001”),再控制状态机进入“数据移位”状态,输入随意一组32位的数据,再读出TDO的32位输出,正常情况下输出的数据应该与芯片中预先设定的器件标识码一致。 [0034] The specific process is: first controlling JTAG state machine enters "instruction shift" state, the transmission IDCode script (test chip "1001"), then the control state machine enters the "shift data" state, arbitrary set of inputs 32-bit data 32 read out of the TDO output, the output data is consistent with the chip normally be preset in the device identification code. 如果两组数据一致则表明芯片正常工作。 If the same two sets of data indicates that the chip work.

[0035] c)配置芯片。 [0035] c) chip configuration. 发送ConfigIn指令,该指令将配置寄存器连接至TDI和TDO端口之间,用于下载芯片配置文件。 ConfigIn transmitting instructions to the configuration register is connected between TDI and TDO port for downloading chip configuration file.

[0036] 具体过程为:先控制JTAG状态机进入“指令移位”状态,发送ConfigIn指令码(测试芯片中为“0101”),再控制状态机进入“数据移位”状态,接着读入步骤(I)生成的芯片配置文件,通过TDI端口下载至FPGA芯片,至此芯片的功能已经配置完成。 [0036] The specific process is: first controlling JTAG state machine enters "instruction shift" state, the transmission ConfigIn script (test chip as "0101"), then the control state machine enters the "shift data" state, then reading step (I) generated by the chip configuration file is downloaded to the TDI port by the FPGA chip, the chip so far function has been configured.

[0037] d)测试向量加载和比较。 [0037] d) Comparison test vectors and loading. 发送Extest指令,该指令将边界扫描寄存器连接至TDI和TDO端口之间,用于按照测试向量进行测试验证。 Transmitting Extest instruction, which will be connected to the boundary scan registers between TDI and TDO port, for testing according to the test vectors to verify.

[0038] 具体过程为:先控制JTAG状态机进入“指令移位”状态,发送Extest指令码(测试芯片中为“0000”),再控制状态机进入“数据移位”状态,接着读入步骤(I)生成测试向量文件,通过TDI依次加载各组测试向量,并从TDO读取芯片的输出结果,与预期结果相比较。 [0038] The specific process is: first controlling JTAG state machine enters "instruction shift" state, the transmission Extest instruction code (test chip "0000"), then the control state machine enters the "shift data" state, then reading step (I) generating a test vector file, by sequentially loading each TDI set of test vectors and read from the chip output TDO, compared with the expected results. 如比较结果均一致,则测试通过,否则为不合格。 As the comparison results are consistent, then the test passes, otherwise unqualified.

[0039] (3).统计测试结果,生成波形比较报告。 [0039] (3) statistical test result, generating a waveform comparison report. [0040] 使用TCL脚本环境自动读入待测列表中的下一个项目并重复以上过程。 [0040] Using TCL scripting environment automatically read a list the next item to be tested, and the process is repeated.

附图说明 BRIEF DESCRIPTION

[0041] 图I IEEE标准1149. 1-1990制定的边界扫描状态机。 [0041] FIG 1-1990 I IEEE Standard 1149. The boundary scan state machine developed.

[0042] 图2边界扫描寄存器组。 [0042] FIG 2 the boundary scan register group.

[0043] 图3自动测试系统组成。 [0043] FIG 3 automatic test system.

[0044] 图4自动测试方法流程图。 [0044] 4 automatic testing method flowchart FIG.

具体实施方式 detailed description

[0045] 为了模拟用户的测试需求,我们选取了各式待测例子共计105个,其中纯组合电路例子共计51个,时序电路例子共计56个;从功能上来看,包括简单的加法器、乘法器、比较器、加解密逻辑,也包括复杂的唱歌、VGA端口操控、通信等应用。 [0045] In order to simulate the user needs to test, we selected a total of 105 kinds of test examples, pure combinational circuit example wherein a total of 51, a total of 56 examples of the timing circuit; Functionally, including simple adder, multiplier , comparators, encryption and decryption logic, complex applications including singing, VGA port and control, and communications. 另外,测试板选用的一款FPGA芯片支持JTAG边界扫描技术,并有与之配套的编译软件,满足测试要求。 In addition, the choice of a test board FPGA chip supports JTAG boundary scan technology, and a complete set of compiler software to meet the testing requirements.

[0046] 测试时只需要在命令行环境下输入一项命令,就能对所有105个例子进行综合、编译、下载、测试和统计,全程无需人工操作,极大地方便用户进行重复测试。 [0046] When testing only need to enter the command line environment an order for all 105 examples will be able to carry out a comprehensive, compile, download, test and statistics, the whole without manual operation, which greatly facilitates the user to repeat the test. 经验证,绝大部分例子均能一次性测试通过,而测试失败的例子可以通过查看波形比较报告发现存在的问题,人工修改源文件的相关问题,最终也能测试通过。 Proven, most of the examples can test through a one-time, while examples of failed test can find problems, issues related to artificial modify the source file by viewing the waveform comparison reports, and ultimately be able to test.

[0047] 以简单的加法器项目adder4为例,它的源程序包括adder4. V和adder4_test. V,前者为行为级网表文件,后者为仿真文件。 [0047] In a simple adder project adder4 example, its source comprises adder4. V and adder4_test. V, the former is a behavioral level netlist file, which is a simulation file. 运行回归测试系统时,首先会调用Perl脚本自动生成用于配置芯片的位流文件adder4. bit和测试向量文件adder4. txt。 When you run the regression test system first calls the Perl script automatically generates a bit stream file configuration of the chip adder4. Bit and test vector file adder4. Txt. 接着会调用串口控制软件进行JTAG测试,依次进行旁路测试和标识码测试后,将位流文件下载至FPGA,读入测试向量文件并通过边界扫描链加载测试向量,读出测试的结果后与仿真出的预期结果比较,最后得到波形比较报告文件adder4. rpt。 Subsequently serial control software calls the JTAG test, and bypass test code sequentially testing bit stream file is downloaded to the FPGA, the test vector file and read through the boundary scan chain to load the test vector, and read the test results simulation of the expected results of the comparison, and finally get waveform comparison report file adder4. rpt.

[0048] 在整个测试流程中,用户只需要简单的输入一条命令就能自动完成整个测试流程。 [0048] Throughout the testing process, the user simply need to enter a command will automatically complete the testing process. 而如果使用老式的纯手工测试,不仅效率极低,而且极易发生各种人为错误;再相对于Altera公司的SignalTap和Xilinx公司的ChipScope,这些工具虽然测试准确,但在测试过程中仍然需要一定的手工操作,对于大批量的测试任务,用户仍然需要耗费大量时间和精力进行操作,且其只适用于各自公司生产的芯片;最后对于安捷伦科技公司的Agilent93000 Pin Scale测试机,虽然它的测试准确度、通用性和速度都极高,但也需要用户提前准备好位流文件和测试向量,另外该机器配套的软件使用门槛极高,需要花费大量时间学习其使用方法。 And if you use old-fashioned pure manual testing, not only inefficient, but also extremely easy to various human error; another relative to Altera's SignalTap and Xilinx's ChipScope, these tools Although the test is accurate, but is still in the testing process will take some manual operation for high-volume testing tasks, users still need to spend a lot of time and energy to operate, and it is only applicable to the respective company's chips; and finally for Agilent Technologies Agilent93000 Pin Scale test machine, although it's accurate testing degree, versatility and speed are very high, but it requires the user to be ready ahead of the bit stream file and test vectors, in addition to supporting the machine software using the threshold is very high, it takes a lot of time learning its use.

[0049] 在实际使用本发明提出的自动测试系统和方法时发现,这套工具不仅极大地方便了用户对工程代码的硬件仿真测试,也能够用于对FPGA芯片本身进行硬件测试如互连遍历测试,相当具有实用性。 [0049] In the automatic testing system and method proposed by the present invention found that the actual use, this tool greatly facilitates the user not only hardware engineering simulation test code can be used to test the hardware itself FPGA chip interconnect traversal test, quite practical.

Claims (6)

  1. 1.基于边界扫描的FPGA芯片自动测试系统,其特征在于包括硬件和软件两大部分:硬件部分包括用于运行自动测试软件的计算机,以及待测的FPGA芯片测试板;软件部分包括编译软件、测试向量生成器、串口控制软件以及将它们整合在一起的回归测试系统;其中: 所述编译软件,与待测的FPGA芯片相配套,它用于将用户的项目工程文件编译成芯片配置文件,该文件下载至FPGA芯片,将FPGA芯片配置成用户所需要的功能; 所述测试向量生成器,通过在命令行环境下调用仿真软件,对用户的待测设计进行仿真,并将仿真后生成的波形记录文件转换成所需要的测试向量格式; 所述串口控制软件,使用Windows XP操作系统提供的通用链接库控制串口,使其按一定格式发送和接收数据;相应于JTAG的4个TAP端口:TCK、TMS、TDI、TDO,串口输出的数据共有8位,其对应关系如 1. Automatic FPGA chip boundary scan test system based, comprising two major hardware and software: The computer hardware includes software for running the automatic testing, and the FPGA chip test board to be tested; Software includes translation software, test vector generator, control software, and the serial interface thereof together regression test system; wherein: compiling the software, and tested FPGA chip matching, which is used to compile the user's project file to a chip configuration file, the file is downloaded to the FPGA chip, FPGA chip configured to function desired by the user; the test vector generator, the design of the test to simulate the user's simulation software by calling the command line environment, and after the simulation to generate waveform record file is converted into the required format of test vectors; the serial control software, using a common link library Windows XP operating system provides a control port, it sends and receives data according to a certain format; 4 corresponding to the JTAG TAP port: TCK, data TMS, TDI, TDO, a total of eight serial output, as the corresponding relationship between :
    Figure CN101995546BC00021
    所述回归测试系统,使用平台无关的TCL脚本语言实现,它无缝地调用上述所有测试子系统;通过建立回归测试策略,实现用户进行多版本的系统测试,以确认各个版本的修改没有引入新的错误或导致其他代码产生错误。 The regression test system, using a platform-independent TCL scripting language, it seamlessly invoke all of the above test subsystems; through the establishment of regression testing strategies to achieve the multi-user version of the system test to confirm the various versions of the modifications do not introduce new errors or cause other code to generate an error.
  2. 2. 一种基于边界扫描的FPGA芯片自动测试方法,其特征在于具体步骤如下: (I)使用TCL脚本环境自动调用用于生成一系列准备文件的Perl脚本,该脚本调用编译软件将用户的项目源程序编译成用于下载配置FPGA芯片的位流文件;同时调用测试向量生成器生成规定格式的测试向量文件; (2 )将PC的串口连接至FPGA的JTAG测试端口,运行串口控制软件控制FPGA芯片的JTAG测试端口,改变其TAP控制器的状态,使之分别运行以下几个测试模式: a)、测试旁路 发送Bypass指令,该指令将旁路寄存器连接至TDI和TDO端口之间,用于测试JTAG是否正常工作; b)、测试标识码发送IDCode指令,该指令将器件标识寄存器连接至TDI和TDO端口之间,用于测试FPGA芯片是否正常工作; c)、配置芯片 发送ConfigIn指令,该指令将配置寄存器连接至TDI和TDO端口之间,用于下载FPGA芯片配置文件; d)、测试 An FPGA automatic testing method based on a chip boundary scan, wherein the following steps: (I) using Perl script invoked automatically TCL script environment for generating a series of document preparation, the script calls the user program compiled software compile the source code into a bit stream used to download files for configuring FPGA device; also invoke the test vector generator generates a test vector file of a predetermined format; (2) connected to the PC's serial port to the FPGA JTAG test port, serial control software running FPGA chip JTAG test port, change the TAP controller state so as to run several test modes are: a), the bypass transmission bypass test instructions to the bypass register are connected between the TDI and TDO port, with in JTAG test is working; B), the test code transmission IDCode instructions to the connection means identification registers between TDI and TDO port, for testing the FPGA chip is working properly; C), arranged ConfigIn chip sends instructions, the instruction to configure the register is connected between TDI and TDO ports for downloading FPGA chip profile; D), test 向量加载和比较发送Extest指令,该指令将边界扫描寄存器连接至TDI和TDO端口之间,用于按照测试向量进行测试验证; (3)统计测试结果,生成波形比较报告; (4)使用TCL脚本环境自动读入待测列表中的下一个项目,并重复以上过程。 Comparing transmission and loading vector Extest instruction, which will be connected to the boundary scan register between TDI and TDO port, for testing according to the test vector verification; (3) statistical test result, generating a waveform comparison report; (4) the use of scripts TCL environment automatically read the next item in the list to be tested, and the process is repeated.
  3. 3.根据权利要求2所述的方法,其特征在于所述测试旁路的具体步骤为:先控制JTAG状态机进入“指令移位”状态,发送Bypass指令码,再控制状态机进入“数据移位”状态,输入固定的一组数据,再读出TDO的输出,并用软件方法检查输入与输出结果是否一致;如果两组数据一致则表明JTAG正常工作。 3. The method according to claim 2, wherein said step of testing concrete bypass: first controlling JTAG state machine enters "instruction shift" state, the transmission Bypass script, then the control state machine enters the "shift data bit "state, the input of a fixed set of data read out of the TDO output, and checking methods is consistent with the software input and the output; if the two sets of data are consistent JTAG indicates normal operation.
  4. 4.根据权利要求2所述的方法,其特征在于所述测试标识码的具体步骤为:先控制JTAG状态机进入“指令移位”状态,发送IDCode指令码,再控制状态机进入“数据移位”状态,输入随意一组32位的数据,再读出TDO的32位输出,如果该组数据与芯片内部预设的标识码一致则表明芯片正常工作。 The method according to claim 2, wherein said step of testing the specific identification code: first controlling JTAG state machine enters "instruction shift" state, the transmission IDCode script, then the control state machine enters the "shift data bit "state, the input arbitrary set of 32-bit data, 32-bit output read out of the TDO, if the set of data with the chip inside a preset code indicates that the same chip work.
  5. 5.根据权利要求2所述的方法,其特征在于所述配置芯片的具体步骤为:先控制JTAG状态机进入“指令移位”状态,发送ConfigIn指令码,再控制状态机进入“数据移位”状态,接着读入步骤(I)生成的芯片配置文件,通过TDI端口下载至FPGA芯片。 The method according to claim 2, wherein said chip is configured specific steps: first controlling JTAG state machine enters "instruction shift" state, the transmission ConfigIn script, then the control state machine enters "data shift "state, then reading step (I) to generate a chip configuration file, downloaded to the FPGA chip by the TDI port.
  6. 6.根据权利要求2所述的方法,其特征在于所述测试向量加载和比较的具体步骤为:先控制JTAG状态机进入“指令移位”状态,发送Extest指令码,再控制状态机进入“数据移位”状态,接着读入步骤(I)生成测试向量文件,通过TDI依次加载各组测试向量,并从TDO读取芯片的输出结果,与预期结果相比较,如比较结果均一致,则测试通过,否则为不合格。 6. The method according to claim 2, wherein said step of specific test vectors for the loading and comparison: first controlling JTAG state machine enters "instruction shift" state, the transmission Extest instruction code, then the control state machine enters " data shifting "state, then reading step (I) to generate test vector file, by sequentially loading each TDI set of test vectors and read from the chip output TDO, compared with the expected results, as the comparison result are consistent, then the test passes, otherwise unqualified.
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