CN106841974B - A kind of FPGA test platform and method - Google Patents
A kind of FPGA test platform and method Download PDFInfo
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- CN106841974B CN106841974B CN201611147369.0A CN201611147369A CN106841974B CN 106841974 B CN106841974 B CN 106841974B CN 201611147369 A CN201611147369 A CN 201611147369A CN 106841974 B CN106841974 B CN 106841974B
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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Abstract
The present invention provides a kind of FPGA test platform and method, obtains test case by case-based system module, test case includes test vector, test and excitation and constraint condition；Simulation Control module calls emulation module, and the test vector of test case and test and excitation input emulation module are emulated；Emulation module carries out simulation process according to test vector and test and excitation and obtains simulation result；Bit stream control module calls bit stream generation module, and by test vector and constrains condition entry bit stream generation module；Bit stream generation module generates bit stream according to test vector and constraint condition and inputs fpga chip to be measured；Comparison module obtains the operation result that fpga chip to be measured is exported according to bit stream and test and excitation, and is compared operation result and simulation result to obtain test result.To be advantageously implemented the purpose of automatic test FPGA, the testing efficiency of FPGA is improved, the testing cost of FPGA is also reduced.
Description
Technical field
The present invention relates to electronic technology field more particularly to a kind of FPGA (Field Programmable Gate
Array, field programmable gate array) test platform and method.
Background technique
For the trend for meeting the needs of users and developing, the function of FPGA device is stronger and stronger, extensive and super large
Module has formed a kind of trend of development.FPGA device is after production molding mostly at present, in order to verify the perfect of its function
Property and the stability of work, need to test it, it usually needs technical staff is by test vector and relevant configuration item
After format is converted into corresponding file format manually, then be manually entered into tester table, then by board to FPGA device into
The corresponding test process of row.
Since test file is converted to corresponding lattice manually there is still a need for related technical personnel by the test to FPGA device
Formula, then tested by being manually entered into tester table, for this larger, the survey of the FPGA device of function complexity
Examination, that will make test process become very difficult, cumbersome, need to expend a large amount of manpower and material resources, and in test process, due to
There are During manual operations, therefore also inevitably there is the case where operation error, to influence the normal survey of FPGA device
Examination process reduces testing efficiency.
Summary of the invention
The present invention provides a kind of FPGA test platform and method, the test process for solving existing FPGA device need people
Work manual test process, causes test process to need to expend a large amount of manpower and material resources, and the problem of inefficiency.
In order to solve the above technical problems, the present invention provides a kind of FPGA test platform, comprising:
Case-based system module: for obtaining test case, the test case includes test vector, test and excitation and about
Beam condition；
Simulation Control module inputs the test vector of the test case and test and excitation for calling emulation module
The emulation module is emulated；
Emulation module obtains simulation result for carrying out simulation process according to the test vector and test and excitation；
The test vector and the constraint condition are inputted institute for calling bit stream generation module by bit stream control module
Bitstream generation module；
Bit stream generation module, for generating bit stream according to the test vector and the constraint condition and inputting FPGA to be measured
Chip；
Comparison module, the operation exported for obtaining the fpga chip to be measured according to the bit stream and the test and excitation
As a result, and being compared the operation result and the simulation result to obtain test result.
Further, the FPGA test platform, further includes integrated treatment module, and being used for will in the bit stream control module
Before test vector input institute's bitstream generation module, judge whether the test vector is target network sheet format, if not,
The test vector is converted into target network sheet format.
Further, the case-based system module is also used to generate example catalogue, the example for the test case of acquisition
Include excitation subdirectory, test file subdirectory, emulation subdirectory, comprehensive subdirectory and bit stream subdirectory in catalogue；
The case-based system module is also used to for the test and excitation of the test case being saved in the excitation subdirectory, will
The test vector and constraint condition are saved in the test file subdirectory；
The emulation module is also used to for the simulation result to be saved in the emulation subdirectory；
The integrated treatment module is also used to be converted into the tabular test vector of target network and is saved in the comprehensive son
Catalogue；
Institute's bitstream generation module is also used to for the bit stream to be saved in the bit stream subdirectory.
Further, the emulation module be also used to extract from the simulation result test and excitation input it is described to
Survey fpga chip.
Further, the FPGA test platform further includes parameter configuration module, for configuring the emulation module and position
Flow the calling path of generation module；
The Simulation Control module and the bit stream control module according to the emulation module and bit stream for generating respectively
Call the emulation module and bit stream generation module in the calling path of module.
The present invention also provides a kind of FPGA test methods, comprising:
Test case is obtained by case-based system module, the test case includes test vector, test and excitation and about
Beam condition；
Simulation Control module calls emulation module, and will be described in the test vector of the test case and test and excitation input
Emulation module is emulated；
Emulation module carries out simulation process according to the test vector and test and excitation and obtains simulation result；
Bit stream control module calls bit stream generation module, and the test vector and the constraint condition are inputted institute's rheme
Flow generation module；
Bit stream generation module generates bit stream according to the test vector and the constraint condition and inputs fpga chip to be measured；
Comparison module obtains the operation result that the fpga chip to be measured is exported according to the bit stream and the test and excitation,
And it is compared the operation result and the simulation result to obtain test result.
Further, the FPGA test method further includes that the test vector is inputted institute in the bit stream control module
Before bitstream generation module, integration module judges whether the test vector is target network sheet format, if not, by the test
Vector median filters are target network sheet format.
It further, further include being generated in fact for the test case of acquisition after the case-based system module obtains test case
Example catalogue, in the example catalogue comprising excitation subdirectory, test file subdirectory, emulation subdirectory, comprehensive subdirectory and
Bit stream subdirectory；
And the test and excitation of the test case is saved in the excitation subdirectory, by the test vector and constraint item
Part is saved in the test file subdirectory；
The simulation result is also saved in the emulation subdirectory by the emulation module；
The integrated treatment module is also converted into the tabular test vector of target network and is saved in the comprehensive subdirectory；
The bit stream is also saved in the bit stream subdirectory by institute's bitstream generation module.
Further, the emulation module carries out simulation process according to the test vector and test and excitation and obtains emulation knot
It further include extracting the test and excitation from the simulation result and inputting the fpga chip to be measured after fruit.
Further, the FPGA test method further include: in the Simulation Control module and the bit stream control module
Before calling the emulation module and bit stream generation module respectively, the emulation module and bit stream are configured by configuration parameter module
The calling path of generation module；
The Simulation Control module and the bit stream control module are respectively according to the emulation module and bit stream generation module
Calling path call the emulation module and bit stream generation module.
Beneficial effect
The present invention provides a kind of FPGA test platform and method, passes through case-based system module and obtains test case, test is real
Example includes test vector, test and excitation and constraint condition；Simulation Control module calls emulation module, and by the survey of test case
Trial vector and test and excitation input emulation module are emulated；Emulation module carries out at emulation according to test vector and test and excitation
Reason obtains simulation result；Bit stream control module calls bit stream generation module, and test vector and constraint condition entry bit stream is raw
At module；Bit stream generation module generates bit stream according to test vector and constraint condition and inputs fpga chip to be measured；Comparison module
The operation result that fpga chip to be measured is exported according to bit stream and test and excitation is obtained, and operation result and simulation result are compared
Relatively obtain test result.It to be advantageously implemented the purpose of automatic test FPGA, solves during the test, needs artificial
The problem of manual switch, input dependence test file, caused easy error, inefficiency, the testing efficiency of FPGA is improved,
Also reduce the testing cost of FPGA.
Detailed description of the invention
Fig. 1 is a kind of structural schematic diagram of the FPGA test platform provided in the embodiment of the present invention one；
Fig. 2 is a kind of schematic diagram that the FPGA test platform provided in the embodiment of the present invention one handles multiple test cases；
Fig. 3 is another structural schematic diagram of the FPGA test platform provided in the embodiment of the present invention one；
Fig. 4 is the perform script structural schematic diagram of the FPGA test platform provided in the embodiment of the present invention one；
Fig. 5 is a kind of flow diagram of the FPGA test method provided in the embodiment of the present invention two；
Fig. 6 is another flow diagram of the FPGA test method provided in the embodiment of the present invention two.
Specific embodiment
Below by specific embodiment combination attached drawing, invention is further described in detail.
Embodiment one:
The present embodiment provides a kind of FPGA test platforms, referring to FIG. 1, the FPGA test platform 1 includes: case-based system mould
Block 11, Simulation Control module 12, emulation module 13, bit stream control module 14, bit stream generation module 15 and comparison module 16,
In:
Case-based system module 11, for obtaining test case, the test case includes but is not limited to test vector, test
Excitation and constraint condition, can be to test the complete of FPGA device reliability of operation or function by the test case
Kind property, or the fault detection for FPGA device etc..It should be understood that the test case that case-based system module 11 obtains is extremely
It is one less, it is also general relatively more to need place to be tested generally, due to FPGA device, therefore required for case-based system module 11
The test case of acquisition is also corresponding more, such as dozens of, hundreds of, even more.Case-based system module 11 can specifically obtain
The test case number taken should the actual conditions of the test according to needed for the FPGA device determine, such as the FPGA device to be tested
It is 100 that part, which needs the test case for test, then then available corresponding this 100 surveys of case-based system module 11
Try example.In general, the effect for the FPGA device that different test cases is tested is different, obtained test result is also different.Example
Whether the function a as test case A can be used for testing FPGA device is perfect, obtains test result A；Test case B can be used
It whether there is failure in the function b of test FPGA device, obtain test result B；Test case N can be used for testing FPGA device
Function N it is whether normal, obtain test result N, referring to figure 2..
It will be appreciated by those skilled in the art that case-based system module 11 can once obtain a test case (
It is serial acquisition), multiple examples (that is to say parallel acquisition) can also be obtained simultaneously.It is real that case-based system module 11 obtains test
The mode of example can be with flexible setting.
In the present embodiment, the FPGA test platform 1 further includes Simulation Control module 12, for calling emulation module 13,
By in test case test vector and test and excitation input emulation module 13 emulate.Simulation Control module 12 calls emulation
The method of module 13, the specific can be that calling emulation module 13 by the calling path of emulation module 13.
Emulation module 13 can be imitated when receiving the calling of Simulation Control module 12 according to test vector and test and excitation
True processing obtains simulation result.The simulation result can be function normal, the functional fault, stability height, stability difference etc..
It should be understood that the simulation result should also include test and excitation, emulation module 13 can also be extracted in simulation result
Test and excitation is input in fpga chip to be measured, generates operation result for fpga chip to be measured.It should be understood that emulation mould
The test and excitation according to included in the simulation result that the test vector and test and excitation generate of block 13, with initial Simulation Control
The essence that module 12 is input to the test and excitation of emulation module 13 should be identical, and the test and excitation in simulation result is emulation module
13 in order to guarantee fpga chip to be measured can identify the test and excitation carry out conversion process, to guarantee in emulation module 13
Used test and excitation is identical as the test and excitation of fpga chip to be measured, the simulation result generated respectively both in this way and operation
As a result just there is the meaning of comparison, guarantee that final test result is accurately and effectively.Certainly, test and excitation can also be by setting
It sets after special format converting module is converted and is input to fpga chip to be measured, without emulation module 13 from simulation result
Middle extraction.
Bit stream control module 14 for calling bit stream generation module 15, and by test vector and constrains condition entry bit stream
Generation module 15.Specifically, bit stream control module 14 can call bit stream raw by the file path of bit stream generation module 15
At module 15, and by the test vector in test case and condition entry is constrained into bit stream generation module 15.
Bit stream generation module 15 receives the test vector and constraint item after the calling for receiving bit stream control module 14
Part, and bit stream is generated according to the test vector and constraint condition, and the bit stream of generation is input in fpga chip to be measured.To
Operation result can be exported according to the bit stream and test and excitation by surveying fpga chip.
Comparison module 16 can be used for obtaining the operation result of fpga chip root bit stream and test and excitation output to be measured, and will
The operation result and the simulation result are compared to obtain test result.To judge whether the test case passes through, sentence
Break fpga chip to be measured corresponding function it is whether normal.
The test case of fpga chip to be measured is obtained by case-based system module 11, Simulation Control module 12 calls emulation mould
Block, and test vector in the test case that will acquire and test and excitation are input in emulation module 13, emulation module 13
Just simulation result is emulated and obtained according to test vector and test and excitation, and bit stream control module 14 is for calling bit stream raw
At module 15, and by test vector and constraint condition entry to bit stream generation module 15, so that bit stream is generated, bit stream generation module
15 can also be input to the bit stream of generation fpga chip to be measured, and fpga chip to be measured can be exported according to bit stream and test and excitation
The actual running results of simulation result and fpga chip to be measured are compared by operation result, comparison module 16, obtain test knot
Fruit.During testing fpga chip, realize from test case is obtained to obtaining the automation process of test result, it is not necessary to
Related technical personnel in test conversion testing file format, be manually entered the process of test file, due to being for extensive
Fpga chip, greatly reduce the investment of manpower and material resources, and by FPGA test platform provided by the embodiment, be greatly improved
The testing efficiency of fpga chip.
Referring to figure 3., in the present embodiment, the FPGA test platform 1 can also include integrated treatment module 17 and ginseng
Number configuration modules 18, wherein integrated treatment module 17 can be used for flow control module 14 in place and generate test vector incoming bit stream
Before module 15, judge whether the test vector is target network sheet format, if test vector is not target network sheet format,
Such as test vector is RTL code, the test vector can be converted to target network sheet format, bit stream by integrated treatment module 17
Control module 14 is converted into the tabular test vector of target network again and is input to bit stream generation module 15, so that bit stream generates mould
Block 15 can identify.It should be understood that then integrated treatment module 17 can be no longer when test vector is target network sheet format
Conversion process is carried out, test vector directly can be input to bit stream generation module 15 by bit stream control module 14.
FPGA test platform 1 can also include parameter configuration module 18, generate mould for configuring emulation module 13 and bit stream
The calling path of block 15；Simulation Control module 12 can be used for calling emulation module 13 according to the calling path of emulation module 13,
And test vector and test and excitation are input to emulation module 13 and carry out simulation process；Bit stream control module 14 can be used for basis
Bit stream generation module 15 is called in the calling path of bit stream generation module 15, and test vector and constraint condition entry is raw to bit stream
Processing, which is carried out, at module 15 generates bit stream.
In the present embodiment, case-based system module 11 can be also used for generating example catalogue for the test case of acquisition, can be with
For storing the test vector in test case, test and excitation and constraint condition, and the emulation knot of storage emulation module 13
The bit stream that the tabular test vector of target network, the bit stream generation module 15 that fruit, the conversion of integrated treatment module 17 generate generate.With
Convenient for facilitating debugging to correct in the mistake investigation of test process.Therefore, the example catalogue that the case-based system module 11 generates can
To include: excitation subdirectory, test file subdirectory, emulation subdirectory, comprehensive subdirectory and bit stream subdirectory.
Wherein, case-based system module 11 can be also used for the test and excitation in test case being saved in excitation subdirectory,
Test vector and constraint condition are saved in test file subdirectory；Emulation module 13 can be also used for for simulation result being saved in
Emulate subdirectory；Integrated treatment module 17 can be also used for being converted into the tabular test vector of target network and be saved in comprehensive son
Catalogue；Bit stream generation module 15 can be also used for the bit stream of generation being saved in bit stream subdirectory.To ensure that test test
There is clearly corresponding relationship between file and test result, it, can also be with ten in fpga chip test process when outlet mistake
Divide and easily carry out positioning investigation, improves testing efficiency.Such as can be and find corresponding error correction file, it is put into corresponding file
In folder.
During test fpga chip, case-based system module 11 may obtain multiple (for example, at least two) survey
Example is tried, case-based system module 11 also should be each test case got and generates a corresponding example catalogue, guarantees
Each test case corresponds to an example catalogue.For example, case-based system module 11 is it for the test case X got
The example catalogue of generation can be as shown in the table:
Table 1
It should be understood that there may be the target network tables generated through the conversion of integrated treatment module 17 in comprehensive subdirectory
The test vector of formula, when the test vector in test case is target network sheet format, also without going through integrated treatment module 17
Conversion process, bit stream control module 14 calls directly bit stream generation module 15, and the test vector in test case is input to
In bit stream generation module 15.It therefore may also be sky in comprehensive subdirectory.
In the present embodiment, case-based system module 11 is that the example catalogue that the test case got generates is not limited to motivate
Subdirectory, test file subdirectory, emulation subdirectory, comprehensive subdirectory and bit stream subdirectory, such as can also include IP
Catalogue, for saving the location information of the test case.For example, for the test case M got, case-based system module 11 is
Its example catalogue generated can be as shown in the table:
Table 2
| Directory name | Save content |
| Motivate subdirectory | Test and excitation M |
| Test file subdirectory | Test vector M, constraint condition M |
| Emulate subdirectory | Simulation result M |
| Comprehensive subdirectory | The tabular test vector M of target network |
| Bit stream subdirectory | Bit stream M |
| IP subdirectory | Position M |
In order to better understand the present invention, referring to figure 4., it should be noted that wherein All.bat is imitated in the present embodiment
The treatment process of true control module 12, bit stream control module 14 and integrated treatment module 17 is realized by corresponding scripts language
Concrete mode, All.bat can be named as.In the present embodiment, the treatment process of the Simulation Control module 12 can be with
By the scripting language realization of both formats of bat, tcl, such as calling is realized by Script.bat script unit
Sim.tcl script unit, then the process for calling emulation module 13, Sim.tcl script unit are realized by Sim.tcl script unit
The test vector and test and excitation can also be inputted emulation module, be called automatically to realize by Simulation Control module 12
Emulation module 13, and test vector and test and excitation are automatically entered into the process that emulation module emulates.script.bat
Script unit and sim.tcl script unit can be automatically generated by All.bat, specifically, for example need to only configure in ALL.bat
The calling path parameter of emulation module 13.
To the integrated disposal processing of integrated treatment module 17 in this present embodiment, two kinds of formats of bat, tcl can be passed through
Scripting language realize.Such as realized by Script.bat, Syn.tcl and Syn-do.tcl script unit in Fig. 3,
Middle Script.bat script unit may be implemented to call the process of Syn.tcl script unit, and Syn.tcl script unit can call
Syn-do.tcl script unit, and incite somebody to action the test vector of other corresponding non-targeted netlist formats (such as test vector of RTL)
It is input to Syn-do.tcl script unit, Syn-do.tcl script unit, which is executed, is converted to target network table for the test vector
Formula.To realize the automatic conversion process of test vector format, reduce the processing load of technical staff in FPGA test process,
Improve transfer efficiency.It should be understood that the possible target network sheet format of test vector, it is also possible to which extended formatting works as test
When vector is target network sheet format, it may not be necessary to which 17 conversion process of integrated treatment module can specifically pass through setting
Parameter flag in All.bat is set as flag=00 to control whether using integrated treatment module 17, such as by flag, indicates
Without using integrated treatment module 17, flag=01 is set by flag, indicates to use integrated treatment module 17, it should be understood that
The remaining bit of flag can also be the reserved place of other situations.Wherein, script.bat script unit, syn.tcl script unit
It can be automatically generated with syn_do.tcl script unit, specifically, for example need to only configure integrated treatment module 17 in ALL.bat
Calling path parameter.
The present embodiment, the bit stream control module 14 call bit stream generation module and input test vector and constraint item
The detailed process of part to bit stream generation module 15 may is that be realized by the scripting language of two kinds of formats of bat, tcl.Such as pass through
Script.bat script unit, Pnr-do.tcl script unit and Pnr.tcl script unit realize bit stream control module 14
Concrete processing procedure, Script.bat script cell call Pnr-do.tcl script unit, Pnr-do.tcl script unit can be with
For calling Pnr.tcl script unit, Pnr.tcl script unit can be used for calling bit stream generation module 15, and test is sweared
Amount and constraint condition entry bit stream generation module 15, realize the process for automatically generating bit stream.Wherein script.bat script unit,
Pnr-do.tcl script unit and Pnr.tcl script unit can automatically generate, specifically, can be by ALL.bat
The process for generating bit stream can be completed in the calling path parameter of configuration bit stream generation module 15.
In the present embodiment, FPGA test process includes but is not limited to pass through above-mentioned bat, tcl scripting language to realize, may be used also
To be realized by other corresponding scripting languages.
The embodiment of the present invention provides a kind of FPGA test platform, the FPGA test platform 1 include case-based system module 11,
Simulation Control module 12, emulation module 13, bit stream control module 14, bit stream generation module 15, comparison module 16, integrated treatment mould
Block 17 and parameter configuration module 18.It is used to configure emulation module 13 and bit stream generation module 15 by parameter configuration module 18
Call path, Simulation Control module 12 and bit stream control module 14 for calling path to call 13 He of emulation module according to it respectively
Bit stream generation module 15, wherein Simulation Control module 12 is also used to for test vector and test and excitation being input in emulation module 13
It is emulated to obtain simulation result, bit stream control module 14 is used to input constraint condition and the tabular test vector of target network
To bit stream generation module 15, bit stream is generated by bit stream generation module 15, fpga chip to be measured is raw according to bit stream generation module 15
At bit stream and simulation result in the test and excitation that extracts, generate operation result, comparison module 16 is raw by fpga chip to be measured
At operation result be compared with the simulation result that emulation module 13 generates, obtain test result.Wherein, target network sheet format
Test vector may be by integrated treatment module 17 according in test case test vector conversion generate, it is also possible to
Test vector inherently target network in test case is tabular.To be advantageously implemented automatic test fpga chip
Purpose solves in FPGA test process, needs manually to convert, inputs dependence test file, caused easy error,
The problem of inefficiency, promotes the testing efficiency of FPGA, also reduces FPGA testing cost.
Embodiment two:
The present embodiment provides a kind of FPGA test methods, referring to FIG. 5, the FPGA test method includes:
S11: test case is obtained by case-based system module.
The test case that the case-based system module obtains includes test vector, test and excitation and constraint condition, is passed through
The test case can be to test the FPGA device reliability of operation perhaps integrity of function or for FPGA device
Fault detection etc., it should be appreciated that test case includes at least one, in general, the test that case-based system module obtains is real
Example is there may be multiple, for testing the state of fpga chip different function respectively.When case-based system module obtains test case,
A test case can be once obtained, multiple (at least two) test cases can also be obtained simultaneously.
S12: Simulation Control module calls emulation module, and test vector and test and excitation are inputted emulation module.
Simulation Control module can call emulation module by the calling path of emulation module.
S13: emulation module is emulated to obtain simulation result according to the test vector and test and excitation.
It also include test and excitation in the simulation result, the test and excitation in the simulation result is used directly for be measured
Fpga chip generates operation result.It should be understood that the test in test and excitation and test case in the simulation result
Motivate essence should be identical.Therefore, it can be input to fpga chip to be measured by extracting the test and excitation in simulation result, it can also
With by by the test and excitation in test case obtain after processing transformation with it is defeated after test and excitation identical in simulation result
Enter into fpga chip to be measured.
S14: bit stream control module calls bit stream generation module, and by the test vector and constraint condition in test case
In incoming bit stream generation module.
Bit stream control module includes but is not limited to the calling path by bit stream generation module to call bit stream generation module.
S15: bit stream generation module generates bit stream according to the test vector and constraint condition, and the bit stream of generation is inputted
Fpga chip to be measured.
After the bit stream and corresponding test and excitation that fpga chip to be measured receives the generation of bit stream generation module, reality can be exported
The operation result on border.
S16: comparison module obtains the operation result of fpga chip to be measured, and the operation result and simulation result are carried out
Compare to obtain test result.
For example, can judge reality using simulation result as the judgement benchmark of the operation result of FPGA reality output to be measured
Operation result whether be consistent with simulation result, when judgement be consistent with simulation result when, it may be considered that the test case is
Pass through namely the corresponding function of fpga chip to be measured is normal.When judging FPGA the actual running results to be measured and simulation result not
When being consistent, then judge the test case not over.
In order to which preferably using the present invention, the present embodiment also provides a kind of FPGA test method, please refers to Fig. 6, described
FPGA test method includes:
S21: the calling path of emulation module and bit stream generation module is configured by parameter configuration module.
For the ease of Simulation Control module and bit stream control module respectively to the calling of emulation module and bit stream generation module,
Parameter configuration module includes but is not limited to configure emulation module and bit stream by way of searching automatically or user is manually entered
The calling path of control module.
S22: case-based system module obtains test case, and generates an example mesh for each test case obtained
Record reads each test case therein, and test vector, test and excitation and the constraint condition in each test case is saved
Into corresponding example catalogue.
Each example catalogue that the case-based system module generates includes: excitation subdirectory, test file subdirectory, emulation
Catalogue, comprehensive subdirectory and bit stream subdirectory.Case-based system module reads each test case, and by the survey in each test case
Examination excitation is saved in corresponding excitation subdirectory, and test vector and constraint condition are saved in corresponding test file subdirectory
In.
S23: integrated treatment module judges whether the test vector in test case is target network sheet format, if not, going to
Step S23, if so, going to step S24.
S24: test vector is converted to target network sheet format by integrated treatment module, and it (is converted into target network table
The test vector of formula) it is stored in the synthesis subdirectory under the example catalogue of the test case.
It should be understood that can not make to it when integrated treatment module judges test vector for target network sheet format
Processing.
S25: Simulation Control module calls emulation module, and test and excitation and test vector are inputted emulation module.
The test and excitation and test vector can be from the excitation subdirectories and test file specific item under respective instance catalogue
It is obtained in record.
S26: emulation module carries out simulation process according to test vector and test and excitation and obtains simulation result, and emulation is tied
Fruit is saved in the emulation subdirectory under the example catalogue of corresponding test vector.
S27: bit stream control module calls bit stream generation module, and test vector and constraint condition entry are generated to bit stream
Module.
It should be understood that test vector described here can be the target netlist in example catalogue under comprehensive subdirectory
The test vector of format is also possible to the tabular test vector of the target network directly acquired.For example, the test of the test case
Vector sheet is as target network sheet format, and without integrated treatment module conversion process, therefore and is not stored in the test case
Example catalogue under synthesis subdirectory in.
S28: bit stream generation module generates bit stream according to the test vector and constraint condition, and the bit stream of generation is saved
In bit stream subdirectory under to the example catalogue of the test case.
Fpga chip to be measured can export operation result according to the bit stream and test and excitation.
S29: comparison module obtains the operation result of fpga chip to be measured output, and by the operation result and simulation result
It compares, obtains test result.
To judge whether the test case passes through, judge whether the corresponding function of fpga chip to be measured is normal.
It should be understood that the test process of entire FPGA test case can carry out one at a time, to the test case
After obtaining test result, then next example test is carried out, multiple test cases can also be tested simultaneously, specific test mode can
Flexibly to be set according to actual test situation.
The embodiment of the present invention provides a kind of FPGA test method, configures emulation module by parameter configuration module and bit stream is raw
At the calling path of module；Case-based system module obtains test case, and generates a reality for each test case obtained
Example catalogue reads each test case therein, and test and excitation therein is stored in corresponding excitation subdirectory, by this
The test vector and unbound document of test case are stored in the test file subdirectory under the example catalogue；Integrated treatment mould
Block judges that the test vector of test case is not target network sheet format, is converted into target network sheet format, and will be after conversion
The tabular test vector of target network is stored in the synthesis subdirectory under the example catalogue of the test case；According to the calling
Path, Simulation Control module call emulation module, and test vector and test and excitation are inputted emulation module；Emulation module is according to institute
It states test vector and test and excitation is emulated, obtain simulation result, and the simulation result is saved in the reality of the test case
In emulation subdirectory under example catalogue；Bit stream control module calls bit stream raw according to the calling path of institute's bitstream generation module
At module, and by constraint condition and the tabular test vector incoming bit stream generation module of target network；Bit stream generation module according to
The constraint condition and the tabular test vector of target network generate bit stream, and the bit stream of generation is stored in the test case
In bit stream subdirectory under example catalogue；Fpga chip to be measured can export operation result according to the bit stream and test and excitation；
Comparison module obtains the operation result, and the operation result is compared with the simulation result that emulation module obtains, and obtains
Test result.To be advantageously implemented the automatic test course of fpga chip, artificial conversion testing file format, input are avoided
The complicated processes of test file improve the testing efficiency of FPGA, also reduce manual testing's process error rate and test at
This, is conducive to improve usage experience.
Obviously, those skilled in the art should be understood that each module of aforementioned present invention or each step can be with general
Computing device realizes that they can be concentrated on a single computing device, or be distributed in constituted by multiple computing devices
On network, optionally, they can be realized with the program code that computing device can perform, it is thus possible to be stored in
It is performed by computing device in storage medium (ROM/RAM, magnetic disk, CD), and in some cases, it can be to be different from this
The sequence at place executes shown or described step, perhaps they are fabricated to each integrated circuit modules or by it
In multiple modules or step be fabricated to single integrated circuit module to realize.So the present invention is not limited to any specific
Hardware and software combine.
The above content is specific embodiment is combined, further detailed description of the invention, and it cannot be said that this hair
Bright specific implementation is only limited to these instructions.For those of ordinary skill in the art to which the present invention belongs, it is not taking off
Under the premise of from present inventive concept, a number of simple deductions or replacements can also be made, all shall be regarded as belonging to protection of the invention
Range.
Claims (10)
1. a kind of FPGA test platform characterized by comprising
Case-based system module: for obtaining test case, the test case includes test vector, test and excitation and constraint item
Part；
Simulation Control module will be described in the test vector of the test case and test and excitation input for calling emulation module
Emulation module is emulated；
Emulation module obtains simulation result for carrying out simulation process according to the test vector and test and excitation；
The test vector and the constraint condition are inputted institute's rheme for calling bit stream generation module by bit stream control module
Flow generation module；
Bit stream generation module, for generating bit stream according to the test vector and the constraint condition and inputting FPGA core to be measured
Piece；
Comparison module, the operation knot exported for obtaining the fpga chip to be measured according to the bit stream and the test and excitation
Fruit, and the operation result is compared to obtain test result with the simulation result.
2. FPGA test platform as described in claim 1, which is characterized in that further include integrated treatment module, for described
Before the test vector is inputted institute's bitstream generation module by bit stream control module, judge whether the test vector is target
Netlist format, if not, the test vector is converted to target network sheet format.
3. FPGA test platform as claimed in claim 2, which is characterized in that the case-based system module is also used to as acquisition
Test case generates example catalogue, in the example catalogue comprising excitation subdirectory, test file subdirectory, emulation subdirectory,
Comprehensive subdirectory and bit stream subdirectory；
The case-based system module is also used to for the test and excitation of the test case to be saved in the excitation subdirectory, will be described
Test vector and constraint condition are saved in the test file subdirectory；
The emulation module is also used to for the simulation result to be saved in the emulation subdirectory；
The integrated treatment module is also used to be converted into the tabular test vector of target network and is saved in the comprehensive subdirectory；
Institute's bitstream generation module is also used to for the bit stream to be saved in the bit stream subdirectory.
4. FPGA test platform as described in any one of claims 1-3, which is characterized in that the emulation module is also used to from institute
It states and extracts the test and excitation input fpga chip to be measured in simulation result.
5. FPGA test platform as described in any one of claims 1-3, which is characterized in that further include parameter configuration module, use
In the calling path for configuring the emulation module and bit stream generation module；
The Simulation Control module and the bit stream control module are used for respectively according to the emulation module and bit stream generation module
Calling path call the emulation module and bit stream generation module.
6. a kind of FPGA test method characterized by comprising
Case-based system module obtains test case, and the test case includes test vector, test and excitation and constraint condition；
Simulation Control module calls emulation module, and the test vector of the test case and test and excitation are inputted the emulation
Module is emulated；
Emulation module carries out simulation process according to the test vector and test and excitation and obtains simulation result；
Bit stream control module calls bit stream generation module, and the test vector and the constraint condition are inputted the bit stream life
At module；
Bit stream generation module generates bit stream according to the test vector and the constraint condition and inputs fpga chip to be measured；
Comparison module obtains the operation result that the fpga chip to be measured is exported according to the bit stream and the test and excitation, and will
The operation result and the simulation result are compared to obtain test result.
7. FPGA test method as claimed in claim 6, which is characterized in that the FPGA test method further includes in institute's rheme
Before the test vector is inputted institute's bitstream generation module by flow control module, whether integration module judges the test vector
For target network sheet format, if not, the test vector is converted to target network sheet format.
8. FPGA test method as claimed in claim 7, which is characterized in that further include:
It further include generating example catalogue, the reality for the test case of acquisition after the case-based system module obtains test case
Include excitation subdirectory, test file subdirectory, emulation subdirectory, comprehensive subdirectory and bit stream subdirectory in example catalogue；And
The test and excitation of the test case is saved in the excitation subdirectory, the test vector and constraint condition are saved in institute
State test file subdirectory；
The simulation result is also saved in the emulation subdirectory by the emulation module；
The integrated treatment module is also converted into the tabular test vector of target network and is saved in the comprehensive subdirectory；
The bit stream is also saved in the bit stream subdirectory by institute's bitstream generation module.
9. such as the described in any item FPGA test methods of claim 6-8, which is characterized in that the emulation module is according to the survey
It further include that the test is extracted from the simulation result after trial vector and test and excitation progress simulation process obtain simulation result
It motivates and inputs the fpga chip to be measured.
10. such as the described in any item FPGA test methods of claim 6-8, which is characterized in that the FPGA test method is also wrapped
It includes before the Simulation Control module and the bit stream control module call the emulation module and bit stream generation module respectively,
The calling path of the emulation module and bit stream generation module is configured by configuration parameter module；
The Simulation Control module and the bit stream control module are respectively according to the tune of the emulation module and bit stream generation module
The emulation module and bit stream generation module are called with path.
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| CN110308381A (en) * | 2019-05-29 | 2019-10-08 | 深圳市紫光同创电子有限公司 | A kind of built-in self-test method and system of FPGA input and output logic module |
| CN110457743B (en) * | 2019-06-27 | 2023-12-05 | 芯翼信息科技(上海)有限公司 | Chip detection method based on FPGA |
| CN111123084B (en) * | 2019-12-11 | 2022-03-01 | 中国电子科技集团公司第二十研究所 | TCL language-based digital circuit rapid test method |
| CN113849951A (en) * | 2020-06-28 | 2021-12-28 | 中兴通讯股份有限公司 | Chip simulation method, device, equipment, system and storage medium |
| CN111831566A (en) * | 2020-07-17 | 2020-10-27 | 北京字节跳动网络技术有限公司 | Test method, test device, electronic equipment and computer readable storage medium |
| CN113836852B (en) * | 2021-08-18 | 2024-04-05 | 深圳市紫光同创电子有限公司 | Analog bit stream generation method, device, equipment and storage medium |
| CN113568598B (en) * | 2021-09-26 | 2021-12-14 | 中科亿海微电子科技（苏州）有限公司 | Yosys-based FPGA logic synthesis method and device for realizing summation operation |
| CN118133742A (en) * | 2024-03-14 | 2024-06-04 | 苏州异格技术有限公司 | Bit stream testing method, bit stream testing device, bit stream testing computer device, bit stream testing storage medium and bit stream testing program product |
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| CN101995546B (en) * | 2010-11-16 | 2013-02-27 | 复旦大学 | Automatic test system and method of programmable logic device on basis of boundary scan |
| CN102012957A (en) * | 2010-12-17 | 2011-04-13 | 天津曙光计算机产业有限公司 | Verification method for packet classification logic codes based on five-tuple array |
| US20160320451A1 (en) * | 2014-12-30 | 2016-11-03 | Capital Microelectronics Co., Ltd. | Simulation verification method for fpga function modules and system thereof |
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| CN106202680A (en) * | 2016-07-01 | 2016-12-07 | 深圳市紫光同创电子有限公司 | FPGA configuration control module verification method and device |
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